CN111965523B - Chip testing method - Google Patents
Chip testing method Download PDFInfo
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- CN111965523B CN111965523B CN202010816547.4A CN202010816547A CN111965523B CN 111965523 B CN111965523 B CN 111965523B CN 202010816547 A CN202010816547 A CN 202010816547A CN 111965523 B CN111965523 B CN 111965523B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A chip testing method comprises the steps of obtaining an activity value of a second circuit module in a second chip, and calculating power consumption of a circuit unit in the second circuit module according to the activity value of the second circuit module; calculating the power supply voltage drop of the circuit unit according to the power consumption of the circuit unit; and judging whether the power supply voltage drop of the circuit unit meets the signing standard, and correcting the second chip when the power supply voltage drop of the circuit unit does not meet the signing standard.
Description
Technical Field
The present application relates to single chip testing techniques, and in particular to verification procedures prior to commercialization.
Background
Before the chip is actually produced, a series of analysis and verification needs to be carried out to correct possible defects. The supply voltage drop (IR-drop) is analyzed as one of them.
The power supply Voltage drop refers to a Voltage loss caused by the Voltage supply from the power supply Voltage (Source Voltage) and the Ground Voltage (Ground Voltage) of the integrated circuit to the circuit unit. With the continuous evolution of the semiconductor technology, the width of the metal wire in the power supply network is narrower and narrower, so that the resistance value of the unit wire length is continuously increased, and the power supply voltage is also smaller and smaller, and therefore the influence of the power supply voltage drop on the chip performance is more and more obvious. Therefore, whether the power supply voltage drop analysis (IR-drop analysis) result of the chip satisfies the signature (signoff) standard is an essential step before chip delivery and mass production.
How to efficiently obtain the analysis result of the power supply voltage drop to determine whether the analysis result of the power supply voltage drop meets the signing standard is an important issue in the technical field.
Disclosure of Invention
The present application relates to a fast, efficient and reliable implementation of power supply voltage drop analysis for a single chip.
According to one embodiment of the application, a single-chip testing method includes the steps of obtaining an activity value of a second circuit module in a second chip, and calculating power consumption of a circuit unit in the second circuit module according to the activity value of the second circuit module; calculating the power supply voltage drop of the circuit unit according to the power consumption of the circuit unit; and judging whether the power supply voltage drop of the circuit unit meets the signing standard, and correcting the second chip when the power supply voltage drop of the circuit unit does not meet the signing standard.
The present invention will be described in detail with reference to specific examples thereof in conjunction with the accompanying drawings.
Drawings
FIG. 1 is a flow chart of a method 100 for obtaining a master clock frequency according to an embodiment of the invention;
FIG. 2 is a flow chart of a non-vector power supply voltage drop analysis method 200 according to an embodiment of the invention;
FIG. 3 is a flow chart of a chip testing method 300 based on a non-vector power supply voltage drop analysis method 200 according to an embodiment of the invention;
FIG. 4 is a flowchart of a chip test method 400 of a vector power supply voltage drop analysis method according to an embodiment of the invention; and
fig. 5 is a schematic diagram of a processor 500 according to an embodiment of the invention.
Detailed Description
The following description exemplifies various embodiments of the invention. The following description presents basic concepts of the invention and is not intended to limit the scope of the present invention. The actual scope of the invention is to be defined in the following claims.
The power supply voltage drop analysis (IR-drop analysis) is typically performed based on a waveform file VCD (value change dump), wherein the waveform file VCD is generated based on a Place and Route (PR) database. Because building the floorplan database is synchronized with the floorplan and is completed after the completion of the floorplan and the wiring phases, the power supply voltage drop analysis needs to be performed after the time-consuming floorplan and wiring phases and the generation of the waveform file VCD. A hot spot (IR hotspot) causing a voltage drop of the power supply cannot be found in time, where the hot spot refers to the voltage drop of the power supply of the circuit unit with a ratio of the hot spot to the power supply voltage being greater than a preset value.
Unlike voltage drop analysis based on the VCD vector (vector based) of the waveform file, the present application proposes a non-vector (vector) voltage drop analysis technique that can be performed in synchronization with building a place and route database.
In one embodiment, a processor determines whether the chip design meets a power supply voltage drop signature criterion. The processor integrates the information of the first chip to be used as the basis for the second chip to analyze the power supply voltage drop. After the engineer uploads the information of the first chip to the processor, the processor can directly acquire the information of the first chip and perform power supply voltage drop analysis on the second chip, so that the power supply voltage drop hot spot of the second chip can be found and corrected in early design stage, for example, in the process of building a layout and wiring database.
In one embodiment, the non-vector power supply voltage drop analysis described in the present application is performed by a processor, which includes dividing a first chip into a plurality of circuit modules according to a power supply voltage, obtaining an average activity value (activity) of each circuit module, reversely marking the average activity values to corresponding circuit modules in a second chip, and calculating power consumption and power supply voltage drop of the second chip as activity values of corresponding circuit modules in a circuit unit of the second chip. The average activity value refers to the average value of the turnover Rate (Toggle Rate) of a certain circuit module and all circuit units in a chip within a certain time period, and the turnover Rate refers to the level turnover times of input and output signals of the circuit units in one clock period. Therefore, the waveform file VCD is not needed, and the power supply voltage drop information of the second chip can be simulated by reversely marking the average activity values on the corresponding circuit modules in the second chip, so that the hot spot of the power supply voltage drop can be estimated in advance, and the design of the second chip can be modified in time. In one embodiment, after the first chip is divided into a plurality of circuit modules according to the power supply voltage, the first chip may be further divided into a plurality of circuit modules according to at least one function of the circuit modules, for example, according to a plurality of functions of one circuit module.
According to an embodiment of the invention, by the processor, in the first chip, circuit units corresponding to the same value of power supply voltage are divided into the same circuit module, so that the first chip is divided into at least one circuit module, and the first circuit module represents any circuit module of the first chip; in the second chip, the circuit units corresponding to the same value of the power supply voltage are divided into the same circuit module, so that the second chip is divided into at least one circuit module, and the circuit modules of the second chip comprise at least one second circuit module and possibly at least one third circuit module. Depending on the supply voltage provided, the second circuit module can be matched to the first circuit module with the same supply voltage in the first chip. Depending on the supply voltage provided, the third circuit module cannot be matched to the first circuit module with the same supply voltage in the first chip.
According to another embodiment of the present invention, by the processor, in the first chip, circuit units corresponding to the same value of power supply voltage and the same function are divided into the same circuit module, so that the first chip is divided into at least one circuit module, and the first circuit module represents any circuit module of the first chip; in the second chip, the circuit units corresponding to the same value of power supply voltage and the same function are divided into the same circuit module, so that the second chip is divided into at least one circuit module, and the circuit module of the second chip comprises at least one second circuit module and possibly at least one third circuit module. The second circuit module can be matched to the first circuit module with the same power supply voltage and the same function in the first chip according to the power supply voltage and the function. Depending on the power supply voltage or the function provided, the third circuit module cannot be matched to the first circuit module having the same power supply voltage and the same function in the first chip.
In one embodiment, the average Activity value of the first circuit module of the first chip is calculated by executing the average Activity value obtaining instruction get_activity by the processor, and the average Activity value of the first chip is set to be the average Activity value of the corresponding second circuit module in the second chip. The execution of the average Activity value obtaining instruction get_activity includes obtaining a level inversion frequency (transition density) of the first circuit module and a master clock frequency (main clock frequency), where the level inversion frequency is an average level inversion number of input/output signals of all circuit units of the first circuit module within 1 second.
The level inversion frequency of the first circuit module can be obtained by multiplying the average activity value of the first circuit module by the main clock frequency of the first circuit module, and the expression is as follows:
Transition_density＝Activity×Main_Clk_Freq
the transition_density is the level inversion frequency of the first circuit module, the Activity is an average Activity value, and main_clk_freq is the master clock frequency of the first circuit module. Thus, the average activity value of the first circuit module can be calculated by the following equation:
Activity＝Transition_density/Main_Clk_Freq
the level inversion frequency transparency_density of the first circuit module is obtained by executing a level inversion frequency acquisition instruction by the processor.
Fig. 1 is a flowchart of a method 100 for obtaining a master clock frequency main_clk_freq of a first circuit module according to an embodiment of the invention, where the method 100 is executed by a processor to analyze the first circuit module. In step S102, registers in circuit units in the first circuit module are marked. Step S104 extracts the frequency of the clock signals driving these registers and the number of registers driven per clock signal. In step S106, the frequency of the acquired clock signal and the size of the number of registers driven per clock frequency are compared, and the number of registers driven per clock frequency is ordered. In step S108, a frequency report of the first circuit module is generated according to the information acquired in steps S102 to S106. In step S110, from the frequency report, the frequency of the clock signal with the largest number of driven registers is selected as the master clock frequency main_clk_freq, but when more than one clock signal with the largest number of driven registers is selected, the frequency of the clock signal with the highest speed in the clock signal with the largest number of driven registers is selected as the master clock frequency main_clk_freq. According to an embodiment of the present invention, step S104 may only include extracting the number of registers driven by each clock signal, where step S106 may only include comparing the number of registers driven by each clock frequency, and directly selecting the frequency of the clock signal with the largest number of registers driven as the master clock frequency main_clk_freq in step S110, and when the number of registers driven is more than one, acquiring the frequency of the clock signal with the largest number of registers driven, where the frequency of the clock signal with the highest speed is the master clock frequency main_clk_freq. According to an embodiment of the present invention, step S108 may be omitted, and the processor directly executes the step S106 to select the frequency of the clock signal with the largest number of driven registers as the master clock frequency main_clk_freq, and when the number of driven registers is more than one, the frequency of the clock signal with the highest speed in the clock signal with the largest number of driven registers is the master clock frequency main_clk_freq.
The average Activity value Activity of the first circuit module is calculated based on the level inversion frequency transition_density obtained by the level inversion frequency obtaining instruction and the Main clock frequency main_clk_freq obtained by the method 100 of fig. 1, and the average Activity value Activity of the first circuit module is reversely marked to the second circuit module in the second chip, so as to perform non-vector type power supply voltage drop analysis.
When the second chip has the same or similar function as the first chip, for example, the second chip is a serial hard disk (Serial Advanced Technology Attachment, SATA) chip, or a USB chip, the processor may execute the average Activity value obtaining instruction get_activity on at least one first circuit module in the first chip, so as to support the analysis of the power supply voltage drop of the second chip.
For example, the level inversion frequency obtaining command is started by the average Activity value obtaining command get_activity to obtain that the level inversion frequency of the first circuit module with the power supply voltage of 0.8V is 1.89720e+08. The flow shown in fig. 1 is started to obtain the following information.
The first circuit module involves three frequencies: the first frequency is 800MHz, driving 561 registers; the second frequency is 200MHz, also driving 561 registers; the third frequency is 250MHz, driving 130 registers. The higher speed of the first and second frequencies driving the most registers is the first frequency. The primary operating frequency main_clk_freq of the first circuit block is 800MHz.
Based on the above information, the average activity value of the first circuit module is 0.24, and the average activity value can be applied to non-vector power supply voltage drop analysis of the second circuit module with the power supply voltage of 0.8V of the second chip or to non-vector power supply voltage drop analysis of the second circuit module with the power supply voltage of 0.8V and the same function as the first circuit module.
Fig. 2 is a flowchart of a non-vector power supply voltage drop analysis method 200 according to an embodiment of the invention, and the analysis method 200 is performed by a processor. In step S202, the processor obtains the design content of the second chip from the layout database of the second chip, where the design content includes a logic netlist (netlist) of the second chip, a physical synthesis data file (. Def) and a circuit parasitic parameter file (. Spaf), the physical synthesis data file includes data such as a position of a circuit unit, a line length of a trace, and the circuit parasitic parameter file includes parasitic impedance information of the trace, and the parasitic impedance information includes resistance, capacitance, and inductance information. In step S204, a power and ground network (power and ground net, abbreviated as PG net) is configured, which includes designating a power voltage and a ground voltage for the circuit units, wherein different circuit units may be coupled to different values of the power voltage. In step S206, the file for calculating the power consumption is matched, and the design content and the standard cell library described in step S202 are selected as the file for calculating the power consumption, so as to extract the data used for calculating the power consumption of the second chip, where the standard cell library is used for providing information such as the type of the circuit cell. In step S208, the circuit units in the first chip are divided into the first circuit modules according to the power voltage value or according to the power voltage value and the function, the average activity value of the first circuit module is obtained by the processor, and the average activity value of the first circuit module is reversely marked (activity back annotation) to the corresponding second circuit module in the second chip, that is, the average activity value of the first circuit module is used as the activity value of each circuit unit in the corresponding second circuit module. If the third circuit module exists in the second chip, that is, the corresponding circuit module of the first circuit module does not exist in the first chip, setting input signals of the input ends of the circuit units according to the functions of the circuit units in the third circuit module, and calculating the potential of the output ends of the circuit units so as to obtain the activity value of each circuit unit in the third circuit module. In step S210, switching Power consumption (Switching Power) of the individual circuit unit is calculated according to the flip rate of each circuit unit of the second chip, the design content of the second chip, and the following expression.
P switching ＝0.5×C×V 2 ×Clk_Freq×Activity
Wherein C is the value of the parasitic capacitance at the output of the single circuit cell. V is the value of the supply voltage of the single circuit unit, i.e. the value of the supply voltage of the circuit module in which the single circuit unit is located. Clk_freq is the frequency of the clock signal driving the single circuit cell. These parameters for a single circuit cell can be obtained from the corresponding design content as well as from a library of standard cells. Activity is the Activity value of the single circuit unit reversely marked to the single circuit unit or obtained by setting an input signal to the input end of the single circuit unit. The switching power consumption of each circuit unit of the second chip is calculated by the processor according to the parameters. In step S210, the processor obtains the Leakage Power consumption (Leakage Power) of the second chip, and distributes the Leakage Power consumption (Leakage Power) to each circuit unit, and adds the switching Power consumption and the Leakage Power consumption of each circuit unit to obtain the total Power consumption of each circuit unit. In step S210, the current of each circuit unit is also calculated by the processor according to the total power consumption and the power supply voltage of each circuit unit.
In step S212, a resistor-capacitor matrix of each circuit module in the second chip is established by the processor, the resistor-capacitor matrix includes impedance information of each circuit unit in the second circuit module or the third circuit module, and an effective resistance of each circuit unit is obtained according to the resistor-capacitor matrix, wherein the effective resistance includes a power supply voltage and a ground voltage, a trace resistance of the circuit unit, and a parasitic resistance between traces. In step S214, the processor calculates a power voltage drop (rail calculation) of each circuit unit according to the current of each circuit unit of the second chip obtained in step S210 and the effective resistance obtained in step S212, so as to support the determination of the hot spot of the power voltage drop.
At least one average activity value for the second chip reversely marked in step S208 can be directly read as a constant by the processor, so that the non-vector power supply voltage drop analysis method 200 shown in fig. 2 is very fast to implement.
Fig. 3 is a flowchart of a chip testing method 300 based on the non-vector power voltage drop analysis method 200 according to an embodiment of the invention, and the chip testing method 300 is implemented by a processor. After the layout stage (building the layout database) described in step S302 is completed, the non-vector power supply voltage drop analysis method 200 of fig. 2 is used to perform the non-vector power supply voltage drop analysis of step S304, wherein step S304 is performed after the layout is completed, and no waiting for the routing is required. In step S304, the power supply voltage drop of the second chip is calculated according to the average activity value (activity) of the first chip. In this embodiment, the non-vector power supply voltage drop analysis stage S304 may be performed in synchronization with the wiring. In this way, step S306 may also be performed earlier. In step S306, it is determined whether the power supply voltage drop of the circuit unit of the second chip meets a power supply voltage drop signing standard (signoff criterion), wherein the power supply voltage drop signing standard refers to that the ratio of the power supply voltage drop of the circuit unit to the power supply voltage (i.e. the power supply voltage of the module to which the circuit unit is coupled) is smaller than a preset value, for example, smaller than 10%, wherein the preset value is determined according to a Setup Time (Setup Time). If the power supply voltage drop of the circuit unit in the second chip does not meet the verification standard of the power supply voltage drop, step S308 is executed to correct the design of the second chip. The modified second chip will re-enter step S302, and the operations of step S302 and step S304 are performed again until the power supply voltage drops of all the circuit units of the second chip meet the signature standard. After the power supply voltage drops of all the circuit units of the second chip meet the signature verification standard, the flow proceeds to step S310. In step S310, vector based (vector based) power supply voltage drop analysis is performed on the second chip based on the waveform file VCD, and final verification is performed for the design scheme of the second chip. In step S312, if it is determined by the vector power supply voltage drop analysis that the power supply voltage drop of the circuit unit in the second chip does not meet the verification criterion, the flow proceeds to step S308 to correct the design of the second chip. The modified second chip will re-enter step S302 and step S304. In step S312, if it is determined that the power supply voltage drops of all the circuit units of the second chip meet the signing standard of the power supply voltage drops, the flow proceeds to step S314 to perform the forwarding (Tape out). It is noted that the waveform file VCD is usually ready when proceeding to step S310, and no additional configuration time is required. Because the non-vector power supply voltage drop analysis effect of the present application is quite good, the step S310 is used for determining the reliability of the foregoing non-vector power supply voltage drop analysis performed on the second chip, and in combination with the step S312, it is verified whether the second chip meets the sign-on standard of the power supply voltage drop, so that the time consumed by repeatedly executing the step S310 multiple times can be reduced.
Fig. 4 is a flow chart illustrating a vector power supply voltage drop analysis implemented based on the waveform file VCD, which may be employed as stage S310 of fig. 3. In step S402, the design content of the second chip is obtained from the layout and wiring database of the second chip by the processor, where the design content of the second chip includes a logic netlist (netlist) of the second chip, a physical synthesis data file (. Def) and a circuit parasitic parameter file (. Spaf), the physical synthesis data file includes data such as a position of a circuit unit, a line length of a trace, and the circuit parasitic parameter file includes parasitic impedance information of the trace, and the parasitic impedance information includes resistance capacitance inductance information. In step S404, a power and ground network (power and ground net, abbreviated as PG net) is configured, which includes designating a power voltage and a ground voltage for the circuit units, wherein different circuit units may be coupled to different values of the power voltage. In step S406, the file for calculating the power consumption is matched, and the design content and the standard cell library described in step S402 are selected as the file for calculating the power consumption, so as to extract the data used for calculating the power consumption of the second chip, where the standard cell library is used for providing information such as the kind of the circuit cell. In step S408, the potential inversion data on the signal line in the waveform file VCD is substituted into each circuit unit in the second chip. In step S410, the active values of the circuit units of the second chip, i.e. the level inversion condition of the input/output end, are simulated according to the potential inversion data on the signal line in the substituted waveform file VCD, and the actual working state of the second chip is estimated. In step S412, the switching power consumption of the second chip is calculated according to the level inversion condition of the input/output terminals of each circuit unit of the second chip, and the power supply voltage drop of each circuit unit is calculated in combination with the leakage power consumption and the impedance data of the second chip.
Fig. 5 is a schematic diagram of a processor 500 according to an embodiment of the invention, where the processor 500 is used to implement test verification and analysis of a second chip. After uploading the design 502 of the second chip to the processor 500, the layout (building a layout database), the non-vector power supply voltage drop analysis, and the hot spot determination of the power supply voltage drop are performed through the functional modules 504, 506, and 508 of the processor 500, respectively, and the report 512 is output detailing the hot spot of the power supply voltage drop. In particular, the processor 500 includes a data file storing at least one average activity value 510 for the first chip. The non-vector power supply voltage drop analysis operation performed by function block 506 may obtain the at least one average activity value 510 by reading the data file.
Although the invention has been described with respect to the preferred embodiments, it is not intended to limit the invention thereto, and those skilled in the art will appreciate that many changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of chip testing, comprising:
the method comprises the steps of obtaining an activity value of a second circuit module in a second chip, wherein the activity value of the second circuit module in the second chip is obtained based on an activity value of a circuit module in a first chip, the activity value of the circuit module in the first chip is a turnover rate of a circuit unit in the first chip, and the turnover rate is the level turnover times of input and output signals in the circuit unit in one clock cycle;
calculating the power consumption of the circuit units in the second circuit module according to the activity value of the second circuit module;
calculating the power supply voltage drop of the circuit unit according to the power consumption of the circuit unit; and
judging whether the power supply voltage drop of the circuit unit meets the sign-on standard,
and correcting the second chip when the power supply voltage drop of the circuit unit does not meet the sign-on standard.
2. The chip testing method of claim 1, comprising:
the first chip is divided into at least one first circuit module, wherein each first circuit module has a power supply voltage.
3. The chip testing method of claim 2, comprising:
and taking the activity value of the first circuit module as the activity value of the second circuit module, wherein the power supply voltage of the second circuit module is the same as the power supply voltage of the first circuit module.
4. The chip testing method of claim 2, comprising:
acquiring the level inversion frequency of the first circuit module;
judging the main operation frequency of the first circuit module; and
and dividing the level inversion frequency by the main operation frequency to obtain an activity value of the first circuit module.
5. The chip testing method of claim 4, wherein,
the primary operating frequency is the fastest frequency of the frequencies used by the most registers in the first circuit module.
6. The chip testing method of claim 1, wherein,
the second circuit module includes at least one of the circuit units.
7. The chip testing method of claim 1, comprising:
and calculating the current of the circuit unit according to the power consumption and the power supply voltage of the circuit unit.
8. The chip testing method of claim 7, comprising:
and establishing a resistance-capacitance matrix of the circuit unit, and calculating the power supply voltage drop of the circuit unit according to the current of the circuit unit and the resistance-capacitance matrix.
9. The chip testing method according to claim 1, wherein after the layout of the second chip, the second chip is tested according to the activity value of the second circuit module.
10. The chip testing method of claim 1, comprising:
and when the power supply voltage drop of the circuit unit meets the signing standard, verifying the judging result according to the waveform file of the second chip.
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