CN106291300B - Chip pressure drop, the test method of structure and chip improved method - Google Patents
Chip pressure drop, the test method of structure and chip improved method Download PDFInfo
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- CN106291300B CN106291300B CN201510272047.8A CN201510272047A CN106291300B CN 106291300 B CN106291300 B CN 106291300B CN 201510272047 A CN201510272047 A CN 201510272047A CN 106291300 B CN106291300 B CN 106291300B
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Abstract
The present invention provides a kind of chip pressure drops, the test method and chip improved method of structure.In the test method of chip pressure drop, by obtaining point-to-point resistance value (including the second equivalent resistance of the first equivalent resistance and multiple functional modules between any two between external voltage input terminal and each functional module), and the static current of lcd numerical value of each functional module, form resistance characteristic matrix MiiWith the column matrix N of static current of lcdi, and by MiiMultiply NiObtain chip voltage drop value, the above method can it is accurate, convenient and rapidly obtain chip in each functional module voltage drop value, the rapidly pressure drop value information of reaction chip each section, to objectively obtain the voltage drop value distributed data of each section on chip, and then accurate and quick information is provided for the improvement of subsequent chip structure, to improve the progress of chip manufacturing entirety.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of chip pressure drop, structure test method and core
Piece improved method.
Background technique
All devices in the full chip of integrated circuit are all the supply voltages obtained needed for it by power grid, in electricity
In stream transmission procedure, due to the presence of the resistance of power grid material, meeting power grid can be consumed when electric current flows through electric power network
Electric energy reduces the received voltage of each device institute to cause pressure drop, referred to as IR drop to each device.
The IR drop of each device can reduce the switching speed and noise margin of device, even result in logic error.With super
The continuous promotion of the integrated level and working frequency of large scale integrated chip, influences more next caused by operation of the pressure drop to chip
It is bigger, for this purpose, how to test the pressure drop of chip, become more and more important to be improved to chip.
The voltage drop detection of existing chip detects full chip usually using business tool (Commercial Tools), from
And obtain the IR drop information of full chip.But the voltage drop detection method process of existing chip is cumbersome, the period is long, it is time-consuming to take
The IR drop information feedback of power, chip is slow, so that influencing chip improves progress.
For this purpose, the detection method of chip pressure drop how is improved, the voltage drop detection process of facilitating chip, to improve chip I R
The problem of drop information feedback speed is those skilled in the art's urgent need to resolve.
Summary of the invention
The technical issues of technical solution of the present invention is solved be to provide a kind of chip pressure drop, structure test method and
Chip improved method, with facilitating chip IR drop detect process, improve chip I R drop information feedback speed, and to chip into
Row improves, and improves the performance of chip.
In order to solve the above-mentioned technical problem the test method of chip pressure drop provided by the invention.
In the test method of the chip pressure drop, the chip include substrate, multiple functional modules on substrate with
And the interconnection line layer for connecting each functional module；
The functional module connects external voltage input terminal by the interconnection line layer；And each functional module passes through interconnection line
Layer is electrically connected；
The test method of the chip pressure drop includes:
Obtain the first equivalent resistance between the external voltage input terminal and each functional module；
Obtain the second equivalent resistance of multiple functional modules between any two；
The resistance characteristic matrix M of the chip is established based on first equivalent resistance and the second equivalent resistanceii, i is core
The number of functional module in piece, wherein the element of line n be include RnmAnd Rnn, wherein RnmIt is m-th of functional module to n-th
The Resistance Influence numerical value of functional module, RnnFor the first equivalent resistance of n-th of functional module；The Rnm=(Rnn+Rmm+rnm)/
2-rnm, wherein rnmThe second equivalent resistance between n-th of functional module and m-th of functional module；
Establish the column matrix N of the static current of lcd of each functional modulei, the element of line n is the power consumption electricity of n-th of functional module
Fluxion value In；
With the resistance characteristic matrix MiiMultiply the column matrix Ni, obtain the corresponding voltage drop value of each functional module.
Optionally, the external voltage input terminal includes multiple external voltage pins, and the multiple functional module connects simultaneously
Connect multiple external voltage pins.
Optionally, the external voltage input terminal is power voltage input terminal, and the functional module includes power voltage terminal
Mouthful；
The functional module connects the supply voltage that external voltage input terminal includes: the functional module by interconnection line layer
Port connects the power voltage input terminal by the interconnection line layer；
It includes: that the supply voltage port of each functional module passes through institute that each functional module is electrically connected by interconnection line layer
Interconnection line layer is stated to link together；
The functional module further includes ground voltage port, and the ground voltage port of the functional module passes through the interconnection
Ground voltage input terminal outside the connection of line layer.
Optionally, the external voltage input terminal is ground voltage input terminal, and the functional module includes ground voltage terminal
Mouthful；
The functional module connects the ground voltage that external voltage input terminal includes: the functional module by interconnection line layer
Port connects the ground voltage input terminal by the interconnection line layer；
It includes: that the ground voltage port of each functional module passes through institute that each functional module is electrically connected by interconnection line layer
Interconnection line layer is stated to link together；
The functional module further includes supply voltage port, and the supply voltage port of the functional module passes through the interconnection
Power voltage input terminal outside the connection of line layer.
Optionally, the interconnection line layer includes the supply voltage port and power supply electricity for connecting each functional module
Press the power interconnection line layer of input terminal, and ground voltage port for connecting each functional module and ground voltage it is defeated
Enter the ground connection interconnection line layer at end；
It includes: that the ground voltage port of each functional module passes through institute that each functional module is electrically connected by interconnection line layer
It states ground connection interconnection line layer to link together, and same ground voltage input terminal is connected by ground connection interconnection line layer；
The power interconnection line layer includes a plurality of discrete power interconnection line, and a plurality of discrete power supply
Interconnection line is separately connected external different power voltage input terminal；
The ground voltage port of the multiple functional module passes through a plurality of discrete power interconnection line layer connection
Different power voltage input terminals.
Optionally, the interconnection line layer is the multilayered structure for including multilayer interconnection line.
Optionally, the chip further includes the power switch being mounted on the interconnection line layer, and the power switch is located at
Between the functional module and external voltage input terminal；
The step of obtaining the first equivalent resistance between the external voltage input terminal and each functional module includes: to obtain simultaneously
Equivalent resistance after taking the power switch to be connected, first equivalent resistance includes external voltage input terminal and each functional module
Between interconnection line layer equivalent resistance and power switch equivalent resistance.
The present invention also provides a kind of chip improved methods, including, it is obtained by the test method of above-mentioned chip pressure drop
The voltage drop value of each functional module；
The voltage drop value of each functional module and the critical pressure depreciation of each functional module are compared, if voltage drop value is greater than critical
The functional module is then judged as functional module to be optimized by voltage drop value；
Interconnection structure is formed on the chip, to connect the functional module to be optimized and external voltage input
End, or other function module and external voltage input terminal to connect the functional module periphery to be optimized reduce institute
The first equivalent resistance between functional module and external voltage input terminal to be optimized is stated, to reduce the function mould to be optimized
The voltage drop value of block.
Optionally, the step of formation interconnection structure includes:
Remove segment chip；
At the position of removal segment chip, is formed and connect the functional module to be optimized and external voltage input terminal
Interconnection structure.
Optionally, the step of chip further includes the filling metal in the dielectric layer on substrate, removes segment chip is wrapped
It includes:
Remove the filling metal.
Optionally, the interconnection line layer includes multilayer interconnection line, and the interconnection line layer is located at the multiple functional module
Top；The multiple functional module layer is the multilayered structure for including multilayer functional module；
The step of removing segment chip includes: removal between undermost interconnection line layer and the functional module of top layer
Filling metal；
The step of forming interconnection structure on the chip includes: to make having removed formation interconnection structure at filling metal
The interconnection structure is parallel to the interconnection line removed above filling metal；
Conductive plunger is formed between parallel interconnection structure and interconnection line, to connect the functional module to be optimized and outer
Portion's voltage input end.
Optionally, having removed the interconnection line above filling metal is the external voltage input terminal and function mould to be optimized
Interconnection line between block.
Invention further provides a kind of test method of chip structure, the chip includes substrate, more on substrate
A functional module, and the interconnection line layer for connecting each functional module；
The functional module connects external voltage input terminal by interconnection line layer；And each functional module passes through interconnection line layer electricity
It links together；
The interconnection line layer be include multilayer interconnection line, wherein n-th layer interconnection line have square resistance Rn；
The test method of chip structure, comprising:
Obtain the third equivalent resistance between the external voltage input terminal and each functional module；
Obtain the 4th equivalent resistance of multiple functional modules between any two；
In the step of obtaining the third equivalent resistance and four equivalent resistances, the tool obtained to equivalent resistance is loaded into
The square resistance of 1st layer to a layers of interconnection line, and set a+1 layers to the square resistance of b layers of interconnection line as 0,
In, b is the interconnections in interconnection line layer, and b >=a > 0；
The first resistor feature matrix M of the chip is established based on the third equivalent resistance and the 4th equivalent resistanceii
(a), i be chip in functional module number, wherein the element of line n be include RnmAnd Rnn, wherein RnmFor m-th of function mould
Resistance Influence numerical value of the block to n-th of functional module, RnnFor the first equivalent resistance of n-th of functional module；The Rnm=(Rnn+
Rmm+rnm)/2-rnm, wherein rnmThe second equivalent resistance between n-th of functional module and m-th of functional module；
Obtain the 5th equivalent resistance between the external voltage input terminal and each functional module；
Obtain the 6th equivalent resistance of multiple functional modules between any two；
In the step of obtaining the 5th equivalent resistance and six equivalent resistances, the tool obtained to equivalent resistance is loaded into
The square resistance of 1st layer to a-1 layers of interconnection line, and a layers are set to the square resistance of b layers of interconnection line as 0；
The second resistance feature matrix M of the chip is established based on the 5th equivalent resistance and the 6th equivalent resistanceii(a-
1)；
Obtain resistance correlation matrix M (a)=M of a layers of interconnection lineii(a)-Mii(a-1)；
Obtain the resistance correlation matrix of each interconnection line layer；
By comparing the relationship of the element of same position in the corresponding resistance correlation matrix of different interconnection lines, analyze described mutual
The performance of connecting line layer, to test chip structure.
Optionally, by comparing in the resistance correlation matrix of different interconnection line layers, the step of the relationship of the element of same position
It suddenly include: in the corresponding resistance correlation matrix of the different interconnection line of comparison, on diagonal of a matrix locating for the 1st column element of the 1st row
The relationship of same position element.
Compared with prior art, technical solution of the present invention has the advantage that
In the pressure fall-off test method of chip of the present invention, first based on first between external voltage input terminal and each functional module
The second equivalent resistance of equivalent resistance and multiple functional modules between any two obtains the Resistance Influence number between each functional module
Value, establishes resistance characteristic matrix M later with the Resistance Influence numerical value and the first equivalent resistanceii；And establish each functional module
Static current of lcd column matrix Ni；Again with the resistance characteristic matrix MiiMultiply the column matrix Ni, it is corresponding to obtain each functional module
Voltage drop value.In above-mentioned technical proposal, by obtaining point-to-point resistance value (including external voltage input terminal and each function mould
The second equivalent resistance of the first equivalent resistance and multiple functional modules between any two between block) and each functional module
Static current of lcd numerical value forms resistance characteristic matrix MiiWith the column matrix N of static current of lcdi, and by MiiMultiply NiChip voltage drop value is obtained,
The above method can voltage drop value that is accurate, convenient and rapidly obtaining each functional module in chip, rapidly reaction chip each section
Pressure drop value information, to objectively obtain the voltage drop value distributed data of each section on chip, and then change for subsequent chip structure
Into accurate and quick information is provided, to improve the progress of chip manufacturing entirety.
Detailed description of the invention
Fig. 1 is the flow diagram of the test method of chip pressure drop of the present invention；
Fig. 2 is the structural schematic diagram of chip structure in one embodiment of test method of chip pressure drop of the present invention；
Fig. 3 is chip and power voltage input terminal connection configuration figure in Fig. 2；
Fig. 4 is chip and a kind of schematic diagram of connection structure of power voltage input terminal in Fig. 2；
Fig. 5 is the structural schematic diagram of another embodiment of chip structure in the test method of chip pressure drop of the present invention；
Fig. 6 is the flow diagram of chip improved method of the present invention；
Fig. 7 is the structural schematic diagram of one embodiment of chip improved method of the present invention；
Fig. 8 is the flow diagram of the test method of chip structure of the present invention.
Specific embodiment
As described in background, all devices in the full chip of integrated circuit are all needed for obtaining it by power grid
Supply voltage, but in electric current transmission process, the resistance of power grid itself can consume electric energy, to cause to press to each device
It drops (IR drop), so that actually received voltage is less than the voltage being pre-designed to each device.Especially with semiconductor technology
It is constantly progressive, integrated circuit feature size constantly reduces, and the interconnection line in power grid narrows so that resistance in power grid
Increase, increases so as to cause the pressure drop of each device.As the improvement power grid of semiconductor technology is to pressure drop caused by each device
It is increasing for the performance influence of chip, as the voltage drop value of chip can directly increase the time delay in chip path.
For this purpose, needing to carry out pressure fall-off test to chip during chip design and chip are gone into operation, with the pressure of detection chip
Whether depreciation controls in critical pressure depreciation (i.e. chip can bear pressure drop maximum value) range.If voltage drop value is greater than critical pressure drop
Value needs in time to improve chip.During chip design and chip are gone into operation, IR Drop analysis has critically important meaning
Justice.
In chip processes, the pressure fall-off test multiple to chip is generally required, and improve technique, until chip meets pressure
Test passes drop.But it is existing time-consuming and laborious by way of business tool detection chip pressure drop, seriously affect chip manufacturing
Technique.
For this purpose, the present invention provides a kind of chip pressure drops, the test method and chip improved method of structure.With reference to Fig. 1,
The test method of the chip pressure drop includes:
Step S11 obtains the first equivalent resistance between the external voltage input terminal and each functional module；
Step S12 obtains the second equivalent resistance of multiple functional modules between any two；
Step S13 establishes the resistance characteristic matrix of the chip based on first equivalent resistance and the second equivalent resistance
MiiAnd the column matrix N of the static current of lcd of each functional modulei；
Wherein, in resistance characteristic matrix MiiIn, i is the number of functional module in chip, and wherein the element of line n is to include
RnmAnd Rnn, wherein RnmIt is m-th of functional module to the Resistance Influence numerical value of n-th of functional module, RnnFor n-th of functional module
The first equivalent resistance；The Rnm=(Rnn+Rmm+rnm)/2-rnm, wherein rnmFor n-th of functional module and m-th of functional module
Between the second equivalent resistance；
In the column matrix N of static current of lcdiIn, the element of line n is the static current of lcd numerical value I of n-th of functional modulen；
Step S14, with the resistance characteristic matrix MiiMultiply the column matrix Ni, obtain the corresponding pressure drop of each functional module
Value.
The test method of chip pressure drop can be accurate, convenient and rapidly obtains each functional module in chip through the invention
Voltage drop value, the rapidly pressure drop value information of reaction chip each section, to objectively obtain the voltage drop value point of each section on chip
Cloth data, and then accurate and quick information is provided for the improvement of subsequent chip structure, to improve the progress of chip manufacturing entirety.
In order to keep the purpose of the present invention, feature and effect more obvious and easy to understand, with reference to the accompanying drawing to of the invention
Specific embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here mode, therefore the present invention is not limited by the specific embodiments disclosed below.
Embodiment 1
Fig. 2 and Fig. 3 is the schematic diagram of one embodiment of test method of chip pressure drop of the present invention.
It is worth noting that, the chip that the present embodiment method is applicable in can be full chip (Full Chip), it is also possible to
Common chip, or only some functional area in chip.Especially it is emphasized that the present embodiment can be suitable for full core
The pressure fall-off test of piece: since full chip is extensive device, including several hundred million in addition tens scale device, in conventional Simulated hand
Section it is lower can not Straight simulation, embodiment can be directed to it is multiple to tens or several hundred functional modules not etc. possessed by full chip, into
Row effectively emulation and pressure fall-off test.
And chip pressure fall-off test method provided in this embodiment, it is preferably adapted for each function of chip digital circuit region
The pressure fall-off test of module.
In the present embodiment, the chip includes: substrate, multiple functional modules on substrate, and each for connecting
The interconnection line layer of functional module.The functional module has included the devices such as transistor, and the interconnection line layer is equivalent to power supply
Network.The functional module connects external voltage input terminal by the interconnection line layer, and then obtains voltage at runtime.
Optionally, the interconnection line layer is multilayered structure, including multilayer interconnection line, is passed through between each layer interconnection line logical
Pore structure (via) connection.
It is electrically connected between multiple functional modules on the chip by the interconnection line layer.
It it is noted that the multiple functional module uses one or more layers structural arrangement, and include one in same layer
Or multiple functional modules, simultaneously the scope of protection of the present invention is not limited for the arrangement mode of the multiple functional module.
The functional module includes the supply voltage port for connecting external power voltage input terminal, and for connecting
Connect the ground voltage port of external ground voltage input terminal；The power voltage input terminal is used to provide power supply to the chip
Voltage, the ground voltage input terminal is for making the chip ground.
The interconnection line layer includes power interconnection line layer and ground connection interconnection line layer；The power interconnection line layer is for connecting function
The supply voltage port and power voltage input terminal of energy module, ground connection electricity of the ground connection interconnection line layer for linkage function module
Pressure side mouth and ground voltage input terminal.
It include the first functional module 11, the second functional module 12, third on the chip 10 in the present embodiment with reference to Fig. 2
Multiple functional modules such as functional module 13 and the 4th functional module 14, wherein the first functional module 11 includes the first supply voltage
Port 21 and the first ground voltage port 31, the second functional module 12 include second source voltage port 22 and the second ground voltage
Port 32, third functional module 13 include third power supply voltage port 23 and third ground voltage port 33, the 4th functional module
14 include the 4th supply voltage port 24 and the 4th ground voltage port 34.
The power voltage input terminal Vdd connects first supply voltage port 21, second by power interconnection line layer
The power voltage terminal of each functional modules such as supply voltage port 22, third power supply voltage port 23 and the 4th supply voltage port 24
Mouthful, so that the power interconnection line layer be made to connect each functional module；The ground voltage input terminal Vss passes through ground connection interconnection line layer
Connect first ground voltage port 31, the second ground voltage port 32, third power supply voltage port 23 and the 4th ground connection electricity
The ground voltages ports such as pressure side mouth 34, so that the ground connection interconnection line layer connects each functional module.
In the present embodiment, using external power voltage input terminal Vdd as the external electrical in the test method of chip pressure drop
Press input terminal.
First supply voltage port 21, second source voltage port 22, third power supply voltage port 23 and the 4th electricity
The supply voltage port of each functional module such as source voltage port 24 is by the power interconnection line layer by first functional module
11, each functional module such as the second functional module 12, third functional module 13 and the 4th functional module 14 is electrically connected, from
And each functional module is made to connect the same power voltage input terminal Vdd.
Optionally, in the present embodiment, an external voltage input terminal includes multiple external voltage pins, the multiple function
It touches module while connecting the multiple external voltage pin.
In conjunction with reference Fig. 3 and Fig. 4, in the present embodiment, the power voltage input terminal Vdd includes multiple supply voltage pin
40, the supply voltage port 21,22,23,24 ... of each functional module 11,12,13,14 ... on the chip 10 passes through institute
It states power interconnection line layer and connects the multiple supply voltage pin 40, thus from the multiple supply voltage pin to each function mould
Block conveys voltage.
In the present embodiment, the test method of chip pressure drop includes:
In conjunction with reference Fig. 1 and Fig. 2, step S11 is first carried out, obtains the between external voltage input terminal and each functional module
One equivalent resistance.
In the present embodiment, the step S11 includes: the supply voltage port for obtaining each functional module and each supply voltage
The first equivalent resistance between pin 40, comprising: the first functional module 11 is equivalent to first between each supply voltage pin 40
Resistance R11, the second functional module 12 to the first equivalent resistance R between each supply voltage pin 4022……。
First equivalent resistance include specific functional module supply voltage port and each supply voltage pin 40 it
Between power interconnection line layer resistance value.Such as, the first equivalent electricity between the first functional module 11 and each supply voltage pin 40
Hinder R11Including the power interconnection line between each supply voltage pin 40 and the first supply voltage port 21 of the first functional module 11
The resistance summation of layer.
In addition, when carrying out pressure fall-off test to chip (or chip some functional area), at chip (or functional area)
Interconnection line on power switch (not shown) is housed, the power switch is located at some described functional module and external voltage
Between input terminal, for controlling the closure of route, with the operation of control function module, first equivalent resistance includes outer at this time
The equivalent resistance of the equivalent resistance and power switch itself of interconnection line layer between portion's voltage input end and each functional module.
Step S12 is executed later, obtains the second equivalent resistance of multiple functional modules between any two.
In the present embodiment, the step S12 include: obtain the supply voltage port of each functional module between any two etc.
Imitate resistance, comprising: the second equivalent resistance r between the first functional module 11 and the second functional module12, the first functional module 11 and
Second equivalent resistance r between three functional modules 1313... second etc. between the second functional module 12 and the first functional module 11
Imitate resistance r21, the second equivalent resistance r between the second functional module 12 and third functional module 1323……
Wherein, second equivalent resistance includes the electricity connected between the supply voltage port of specific two functional modules
The resistance value of source interconnection line layer.Such as, the second equivalent resistance r between the first functional module 11 and the second functional module 1212Including
Between first supply voltage port 21 of the first functional module 11 and the second source voltage port 22 of the second functional module 12
The resistance of power interconnection line layer.
And first the second equivalent resistance r between functional module 11 and the second functional module 1212, with the second functional module
12 and first the second equivalent resistance r between functional module 1121It is equal.
It is worth noting that, the method for obtaining first equivalent resistance and the second equivalent resistance is the existing skill in this field
Art can be obtained by resistance test equipment, and details are not described herein.
Later, step S13 is executed, the resistance of the chip is established based on first equivalent resistance and the second equivalent resistance
Feature matrix MiiAnd the column matrix N of the static current of lcd of each functional modulei；
Wherein, in resistance characteristic matrix MiiIn, i is the number of functional module in chip, and wherein the element of line n is to include
RnmAnd Rnn, the resistance feature matrix M of foundationiiAre as follows:
Wherein Rnn is the first equivalent resistance of n-th of functional module, RnmIt is m-th of functional module to n-th of functional module
Resistance Influence numerical value, the Rnm=(Rnn+Rmm+rnm)/2-rnm, wherein rnm is n-th of functional module and m-th of function mould
The second equivalent resistance between block.
Such as, R12It is the second functional module 12 to the Resistance Influence numerical value of the first functional module 11, and R12=(R11+R22+
r12)/2-r12.It follows that R12=R21。
The column matrix N of the static current of lcd of foundationiAre as follows:
The wherein element I of line nnFor the static current of lcd numerical value of n-th of functional module.
Such as, I1For the static current of lcd numerical value of the first functional module 11.
It is worth noting that, the method for obtaining the static current of lcd numerical value of each functional module is state of the art,
Details are not described herein.
Forming the resistance feature matrix MiiWith the column matrix N of static current of lcdiAfterwards, step S14 is executed, it is special with the resistance
Property matrix MiiMultiply the column matrix Ni, obtain the corresponding voltage drop value of each functional module.
Wherein, Δ Vn is the voltage drop value of the n-th functional module.Such as the voltage drop value that Δ V1 is the first functional module 11.
In the present embodiment, the supply voltage port of each functional module on chip is external same by the connection of power interconnection line layer
One power voltage input terminal.Using the power voltage input terminal as external power input, the power supply of each functional module is obtained
The first equivalent resistance and each functional module between voltage port and the power voltage input terminal between any two second etc.
Imitate resistance；And pass through the second equivalent electricity corresponding between corresponding first equivalent resistance of each functional module and each functional module
Resistance, the Resistance Influence numerical value of each functional module of acquisition between any two；It is equivalent based on the Resistance Influence numerical value and first later
Resistance establishes the resistance characteristic matrix M of chipii, resettle the column matrix N of the static current of lcd of each functional modulei, and with the electricity
Hinder feature matrix MiiMultiply the column matrix Ni, obtain the corresponding voltage drop value of each functional module.Above scheme can accurately, it is convenient and
The voltage drop value of each functional module in chip is rapidly obtained, rapidly the pressure drop value information of reaction chip each section, thus objective
Ground obtains the voltage drop value distributed data of each section on chip, and then for the improvement of subsequent chip structure provides accurate and quickly believes
Breath.
Embodiment 2
With continued reference to Fig. 2, ground voltage input terminal Vss connects first ground voltage port by ground connection interconnection line layer
31, the ground voltages port such as the second ground voltage port 32, third power supply voltage port 23 and the 4th ground voltage port 34 from
And connect each functional module.
The present embodiment 2 is roughly the same with the technical solution of embodiment 1, and difference is only that, in the present embodiment, with outside
Ground voltage input terminal Vss is as the external voltage input terminal in the test method of chip pressure drop.
First ground voltage port 31, the second ground voltage port 32, third ground voltage port 33 and the 4th connect
The ground voltage port of each functional module such as ground voltage port 34 is by the ground connection interconnection line layer by first functional module
11, each functional module such as the second functional module 12, third functional module 13 and the 4th functional module 14 is electrically connected, and
It is grounded simultaneously.
Optionally, the ground voltage input terminal Vss is similar to the power voltage input terminal Vdd in embodiment 1, described to connect
Ground voltage input terminal Vss includes multiple ground voltage pins, and the multiple functional module connects the multiple ground voltage simultaneously
Pin.
The structure of above-mentioned ground voltage pin is similar to supply voltage mount structure in above-described embodiment 1, no longer superfluous herein
It states.
In the present embodiment, in Fig. 1 in the test method of chip pressure drop:
Step S11 is executed, the first equivalent resistance between external voltage input terminal and each functional module is obtained, comprising:
Using the equivalent resistance between the ground voltage port of each functional module and each ground voltage pin as described
One equivalent resistance.
In the present embodiment, first equivalent resistance includes ground voltage port and each ground connection electricity of specific functional module
The resistance value of ground connection interconnection line layer between pressure pipe foot.Such as, first between the first functional module 11 and each ground voltage pin
Equivalent resistance R11It is mutual including the ground connection between each ground voltage pin and the first ground voltage port 31 of the first functional module 11
The resistance summation of connecting line layer.
Step S12 is executed, the second equivalent resistance of multiple functional modules between any two is obtained, comprising:
Using the equivalent resistance of the ground voltage port of specific two functional modules between any two as the second equivalent resistance.
In the present embodiment, second equivalent resistance includes the ground voltage port for connecting specific two functional modules
It is grounded the resistance value of interconnection line layer.Such as, the second equivalent resistance r between the first functional module 11 and the second functional module 1212Packet
It includes between the first ground voltage port 31 of the first functional module 11 and the second ground voltage port 32 of the second functional module 12
Ground connection interconnection line layer resistance.
It is similar to above-described embodiment 1, in the present embodiment, between the first functional module 11 and the second functional module 12 second
Equivalent resistance r12, the second equivalent resistance r between the second functional module 12 and the first functional module 1121It is equal.
Later, step S13 is executed, the resistance of the chip is established based on first equivalent resistance and the second equivalent resistance
Feature matrix MiiAnd the column matrix N of the static current of lcd of each functional modulei；And step S14, with the resistance characteristic matrix
MiiMultiply the column matrix Ni, obtain the corresponding voltage drop value of each functional module.
The step S13 and step S14 is similar to implementing 1, and details are not described herein.
In the present embodiment, the ground voltage port of each functional module on chip is external same by ground connection interconnection line layer connection
One ground voltage input terminal.It is grounded input terminal using the ground voltage input terminal as outside, obtains the ground connection of each functional module
Equivalent resistance between voltage port and the ground voltage input terminal obtains each functional module two as the first equivalent resistance
It is equivalent as the second equivalent resistance between two ground voltage ports；And by corresponding first equivalent resistance of each functional module with
And corresponding second equivalent resistance of each functional module, the Resistance Influence numerical value of each functional module of acquisition between any two；Base later
The resistance characteristic matrix M of chip is established in the Resistance Influence numerical value and the first equivalent resistanceii, resettle the function of each functional module
The column matrix N of power consumption streami, and with the resistance characteristic matrix MiiMultiply the column matrix Ni, obtain the corresponding pressure of each functional module
Depreciation.Above scheme equally can accurately, it is convenient and rapidly obtain chip in each functional module voltage drop value, rapidly react
The pressure drop value information of chip each section to objectively obtain the voltage drop value distributed data of each section on chip, and then is subsequent
Chip structure, which improves, provides accurate and quick information.
Embodiment 3
In conjunction with reference Fig. 5, Fig. 5 is another chip structure schematic diagram.
Chip 100 in Fig. 5 is roughly the same with 10 structure of chip in Fig. 2, including multiple functional modules and interconnection line
Layer, and the interconnection line layer includes the electricity of the supply voltage port and power voltage input terminal for connecting each functional module
Source interconnection line layer, and the ground connection interconnection of ground voltage port and ground voltage input terminal for connecting each functional module
Line layer, difference are:
The power interconnection line layer includes a plurality of discrete power interconnection line, and a plurality of discrete power supply
Interconnection line is separately connected external different power voltage input terminal, identical to apply to the different functional module of the chip 100
Or it is different voltage.
The supply voltage port of the multiple functional module passes through a plurality of discrete power interconnection line layer connection
Different power voltage input terminals.
It such as, include five-function module 15, the 6th functional module 16, the 7th functional module 17 and the in the chip 100 of Fig. 5
Eight functional modules 18.Wherein five-function module 15 includes the 5th supply voltage port 25 and the 5th ground voltage port 35, the
Six functional modules 16 include the 6th supply voltage port 26 and the 6th ground voltage port 36, the 7th functional module 17 include the 7th
Supply voltage port 27 and the 7th ground voltage port 37, the 8th functional module 18 include the 8th supply voltage port 28 and the 8th
Ground voltage port 38.
6th supply voltage of the 5th supply voltage port 25 and the 6th functional module 16 of the five-function module 15
Port 26 connects the first supply voltage port Vdd1 by the first power interconnection line (not indicating in figure)；7th functional module 17
8th supply voltage port 28 of supply voltage port 27 and the 8th functional module 18 (is not marked by second source interconnection line in figure
Show) connection second source voltage port Vdd2.The first power interconnection line and second source interconnection line are not connected with.
On the chip, each functional module be electrically connected by interconnection line layer include: each functional module ground connection electricity
Pressure side mouth is grounded interconnection line layer by same and links together, and connects external same ground voltage input terminal Vss1.Such as
In Fig. 5, the 5th ground voltage port 35 of the five-function module 15, the 6th functional module 16 the 6th ground voltage port
36, the 7th ground voltage port 37 of the 7th functional module 17 and the 8th ground voltage port 38 of the 8th functional module 18 are logical
The same external same ground voltage input terminal Vss1 of ground connection interconnection line layer connection is crossed, to be grounded.
The present embodiment, in the test method of chip pressure drop, using the ground voltage input terminal Vss1 as chip pressure drop
External voltage input terminal in test method.At this point, even if multiple functional modules pass through external different power supply electricity on chip 100
Pressure input terminal inputs different voltage, but using the same ground voltage input terminal Vss1 that the multiple functional module connects as core
External voltage input terminal in the test method of piece pressure drop, equally can accurately, it is convenient and rapidly obtain chip in each function
The voltage drop value of module, thus the pressure drop value information of reaction chip each section, to objectively obtain the pressure drop of each section on chip
Distribution value data.
In each step S11, S12, S13 and S14 and embodiment 2 in the test method of the chip pressure drop of the present embodiment 3
Chip pressure drop test method in each step S11, S12, S13 and S14 it is similar, details are not described herein.
The present invention also provides a kind of improved methods of chip.
With reference to Fig. 6, the improved method of the chip includes:
Step S21 is executed, the voltage drop value of each functional module is obtained by the test method of chip pressure drop.
The test method of the chip pressure drop can be used what any embodiment in the test method of said chip pressure drop obtained
The voltage drop value of chip.
Later, step S22 is executed, by the critical pressure drop numerical value of the modeled pressure drop numerical value of each functional module and each functional module
It compares, if modeled pressure drop numerical value is greater than critical pressure depreciation, which is judged as functional module to be optimized.
In chip design technology, according to the structure and effect of functional module each on chip, a critical pressure depreciation is set,
The maximum voltage drop value that i.e. each functional module can be born, if the voltage drop value that the test of functional module obtains is less than or equal to described face
Boundary's voltage drop value, then the functional module is qualified, conversely, then the functional module is unqualified, the underproof functional module be will affect
The performance of chip.
It, will be each after the voltage drop value that each functional module is obtained by the test method of said chip pressure drop in the step S22
The voltage drop value of the measurement of functional module is made comparisons with the critical pressure depreciation of each functional module, to obtain underproof functional module
(functional module i.e. to be optimized).
Step S23 is being executed later, is forming interconnection structure (i.e. new interconnection line) on the chip, it is described to connect
Functional module and external voltage input terminal to be optimized, or other function to connect the functional module periphery to be optimized
Energy module and external voltage input terminal, first between the reduction functional module to be optimized and external voltage input terminal are equivalent
Resistance.
External voltage input terminal in the step S23 is that the external voltage in the test method of said chip pressure drop is defeated
Enter end, can be according to the actual situation external power voltage input terminal, can also be external ground voltage input terminal.
In conjunction with reference Fig. 7, the functional module 19 is functional module to be optimized, is originally only connected by interconnection line 51
The external voltage pin 41 of external voltage input terminal, the improved method of the chip include: on the chip 100, described
Between functional module 19 and external voltage pin 41 to be optimized, is formed and connect the functional module 19 and external electrical to be optimized
The new interconnection line 52 and 53 of pressure pipe foot 41, the new interconnection line 52 and 53 is used as interconnection structure, to reduce the function mould
Resistance between block 19 and external voltage pin 41, and then reduce the voltage drop value of functional module 19 to be optimized.
In the present embodiment, formed interconnection structure the step of include:
Remove segment chip；
And at the position of the chip in removal part, is formed and connect the functional module to be optimized and external voltage input
Hold interconnection structure.The removal segment chip includes part interconnection layer, substrate and the other structures removed in chip.
Optionally, chip further includes the dielectric layer on the substrate, and filling metal is formed in the dielectric layer,
The step of filling metal does not contact with the interconnection line layer and functional module, removes the interconnection line layer includes: removal
The filling metal forms interconnection structure to remove the position of filling metal in the chip.Removal filling metal will not influence core
The precision of piece and the performance of chip.
In optinal plan, the interconnection line layer of the chip includes multilayer interconnection line, and the multiple functional module layer is to include
The multilayered structure of multilayer functional module；And the interconnection line layer is located above the multiple functional module.
At this point, optionally, the step of removing interconnection line layer includes: that removal is located at undermost interconnection line layer and top layer
Filling metal between functional module.
The step of forming interconnection structure on the chip includes: to be formed in parallel with to be located at the filling metal removed
The interconnection structure of the interconnection line above filling metal removed；Conductive insert is formed between parallel interconnection structure and interconnection line
Plug, to connect the functional module to be optimized and external voltage input terminal.
Still optionally further, the interconnection line above the filling metal is the external voltage input terminal (external electrical
Pressure input terminal can be understood as power pin) and functional module to be optimized between interconnection line.
In the pressure drop research of the chip, inventors have found that interconnection line and each functional module between each functional module
With the interconnection line between external voltage input terminal, the pressure drop of different functional modules can be had an impact, and the closer function of distance
The influence of generation between energy module is bigger.
It, can be by changing to preferred functional module periphery in another embodiment of the improved method of chip of the present invention
Functional module and external voltage input terminal between interconnecting construction, to reduce the pressure drop to preferred functional module
Value；And the interconnection line between the distance functional module and external voltage input terminal closer to preferred functional module is changed, it is right
It is more obvious in the voltage drop value influence of functional module to be optimized.
Specifically, in another embodiment, after determining functional module to be optimized, selected distance functional module week
The a certain functional module on side, the functional module for defining selection is objective function module；
Optionally, below the interconnection line between the objective function module and external voltage input terminal, and it is located at the top
Functional module and bottom interconnection line between dielectric layer in be formed with filling metal；In addition, the objective function module
It is positioned as close to the functional module to be optimized.
Later, the interconnection line between the objective function module and external voltage input terminal is obtained；And it is obtained in dielectric layer
Fetch bit is located at the objective function module and external voltage input between the functional module of the top and the interconnection line of bottom
Filling metal below interconnection line between end；
The filling metal is removed again, and forms interconnection structure at the filling metal removed, and the interconnection structure is flat
Interconnection line of the row between the objective function module and external voltage input terminal, and in the parallel interconnection structure and interconnection line
Between form conductive plunger, to change the structure of the interconnection line between the objective function module and external voltage input terminal.
Above by change to the interconnection between the functional module and external voltage input terminal on preferred functional module periphery
The structure of line similarly helps to reduce the voltage drop value to preferred functional module.
Especially change when described to not have below the interconnection line between preferred functional module and external voltage input terminal
When filling metal, by changing to the interconnection line between the functional module and external voltage input terminal on preferred functional module periphery
Structure, voltage drop value to preferred functional module can be reduced, to promote core under the premise of reducing influences chip precision
Piece performance.
Chip improved method of the present invention obtains each functional module in chip in the test method by said chip pressure drop
After voltage drop value, interconnection structure (i.e. new interconnection line) is formed on chip, to connect the functional module to be optimized and outer
Portion's voltage input end, or functional module and external voltage input terminal for connecting the energy module periphery to be optimized, drop
The first equivalent resistance between the low functional module to be optimized and external voltage input terminal, to reduce the function mould on chip
The pressure drop numerical value of block optimizes chip performance.
Embodiment 4
In addition, the present invention also provides a kind of test methods of chip structure.
The structure of the chip is identical as the chip structure in each embodiment of the test method of said chip pressure drop comprising
The chip includes substrate, multiple functional modules on substrate, and the interconnection line layer for connecting each functional module.Institute
Stating functional module includes: connecting external voltage input terminal by interconnection line layer；And each functional module is electrically connected by interconnection line layer
Together；
In addition, the interconnection line layer of the chip is multilayered structure comprising multilayer interconnection line.
In chip design, the structure of each interconnection line layer can be designed for the specific requirement of chip, so that it is guaranteed that chip
The performances such as energy consumption, thus each layer of interconnection line all has determining square resistance.In the present embodiment, the side of the interconnection line of n-th layer
Block resistance is Rn。
And in multilayer interconnection line, the interconnection line of adjacent layer is connected by through-hole structure (via) structure.The specific knot of chip
Structure refers to the above content, and details are not described herein.
The defects of however in chip actual fabrication process, process deviation can be based on, caused for through-hole offset, thus shadow
Ring the chip performance being subsequently formed.
For this reason, it may be necessary to test chip structure, with detect chip middle interconnection line layer and original design layout it
Between error.
The test method of chip structure of the present invention can effectively and accurately detect the interconnection line of existing defects, and then improve
Chip structure.
With reference to Fig. 8, the verification method of the present embodiment chip includes:
It executes step S31: obtaining the third equivalent resistance between the external voltage input terminal and each functional module；
Later, it executes step S32: obtaining the 4th equivalent resistance of multiple functional modules between any two；
In above-mentioned first equivalent resistance and the second equivalent resistance, need to be loaded into point-to-point resistance test equipment in file letter
Breath, the file information include: chip layout design file (such as LVS file, LVS full name be Layout Versus
Schematic), the square resistance of each interconnection line, for identification title of each functional module etc. in the design layout of chip.
In the step of obtaining the third equivalent resistance and four equivalent resistances, the tool obtained to equivalent resistance is loaded into
The square resistance of 1st layer to a layers of interconnection line, the Ra such as R1, R2 ...；And a+1 layers are set to the side of b layers of interconnection line
Block resistance value is 0, wherein b is the interconnections in interconnection line layer, and b >=a > 0.
Later, step S33 is executed, establishes the first of the chip based on the third equivalent resistance and the 4th equivalent resistance
Resistance characteristic matrix Mii(a), i be chip in functional module number, wherein the element of line n be include RnmAnd Rnn, wherein Rnm
It is m-th of functional module to the Resistance Influence numerical value of n-th of functional module, RnnFor the first equivalent resistance of n-th of functional module；
The Rnm=(Rnn+Rmm+rnm)/2-rnm, wherein rnmSecond between n-th of functional module and m-th of functional module is equivalent
Resistance.
Establish the resistance characteristic matrix MiiSpecific method chip pressure drop as above test method embodiment described in,
This is repeated no more.
Then step S34 is executed, the 5th equivalent resistance between the external voltage input terminal and each functional module is obtained；
Step S35 is executed, the 6th equivalent resistance of multiple functional modules between any two is obtained；
In the step of obtaining the 5th equivalent resistance and six equivalent resistances, the tool obtained to equivalent resistance is loaded into
The square resistance of 1st layer to a-1 layers of interconnection line, the Ra-1 such as R1, R2 ...；And set a layers to b layers interconnection line
Square resistance is 0；
Then step S36 is executed, establishes the second of the chip based on the 5th equivalent resistance and the 6th equivalent resistance
Resistance characteristic matrix Mii(a-1)；
Step S37 is executed, resistance correlation matrix M (a)=M of a layers of interconnection line is obtainedii(a)-Mii(a-1)；
Step S38 is executed again, and the resistance correlation matrix of each interconnection line is obtained by the above method；
Specifically, the step of above-mentioned S31~S37 being carried out to each layer of interconnection line, to obtain each layer of interconnection line pair
Resistance correlation matrix M (1), M (2) ... the M (b) answered.
Such as,
Step S39 is finally executed, by comparing the element of same position in the corresponding resistance correlation matrix of different interconnection lines
Relationship, the performance of the interconnection line layer is analyzed, to test chip structure.
In the present embodiment, the specific steps of the step S39 include: by comparing the different corresponding resistance phases of interconnection line
It closes in matrix, the relationship of the element of the same position on diagonal of a matrix locating for the element along the 1st row the 1st column, it is every to detect
Whether the performance of one layer of interconnection line meets the requirements, to test chip structure.
For example, in the chips, under being generally much smaller than for the contribution of chip overall electrical resistance positioned at the interconnection line of top layer
Contribution of each layer interconnection line in side for chip overall electrical resistance, thus, the corresponding resistance Correlation Moment of each interconnection line is a burst of, is located at the 1st
The element that row the 1st arranges should be less than the element for being located at the 2nd row the 2nd column.But in step S39, if a certain layer interconnection line is corresponding
During resistance Correlation Moment is a burst of, the element of the 1st row the 1st column is greater than the element for being located at the 2nd row the 2nd column, at this time the of the interconnection line layer
One layer or the second layer have defect.
Such as, R1 in comparative analysis M (1)11And R1iiR2 in each element on the diagonal and M (2)11And R2iiPlace
Each element on diagonal line, to analyze the performance of the first layer interconnection line and second layer interconnection line.Usually in R111And R1iiInstitute
In each element on the diagonal, R111Minimum, if R111Greater than R122Or R133……R1ii, or, the R2 in M (2)11Be greater than
R211Other elements R2 on the diagonal22Or R233……R2iiThen first layer interconnection line may then have defect.
Using the verification method of chip of the present invention, can the interconnection line layer structure of rapidly and efficiently proofing chip whether meet
Design requirement, and rapidly and efficiently detection obtains the interconnection line to go wrong.
Although the invention has been described by way of example and in terms of the preferred embodiments, but it is not for limiting the present invention, any this field
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, anything that does not depart from the technical scheme of the invention, and according to the present invention
Technical spirit any simple modifications, equivalents, and modifications to the above embodiments, belong to technical solution of the present invention
Protection scope.
Claims (14)
1. a kind of test method of chip pressure drop, the chip includes substrate, multiple functional modules and use on substrate
In the interconnection line layer for connecting each functional module；
The functional module connects external voltage input terminal by the interconnection line layer；And each functional module passes through interconnection line layer electricity
It links together；
It is characterized in that, the test method of the chip pressure drop includes:
Obtain the first equivalent resistance between the external voltage input terminal and each functional module；
Obtain the second equivalent resistance of multiple functional modules between any two；
The resistance characteristic matrix M of the chip is established based on first equivalent resistance and the second equivalent resistanceii, i is in chip
The number of functional module, wherein the element of line n be include RnmAnd Rnn, wherein RnmIt is m-th of functional module to n-th of function
The Resistance Influence numerical value of module, RnnFor the first equivalent resistance of n-th of functional module；The Rnm=(Rnn+Rmm+rnm)/2-rnm,
Wherein rnmThe second equivalent resistance between n-th of functional module and m-th of functional module；
Establish the column matrix N of the static current of lcd of each functional modulei, the element of line n is the static current of lcd number of n-th of functional module
Value In；
With the resistance characteristic matrix MiiMultiply the column matrix Ni, obtain the corresponding voltage drop value of each functional module.
2. the test method of chip pressure drop as described in claim 1, which is characterized in that the external voltage input terminal includes more
A external voltage pin, the multiple functional module connect multiple external voltage pins simultaneously.
3. the test method of chip pressure drop as claimed in claim 1, which is characterized in that the external voltage input terminal is supply voltage
Input terminal, the functional module include supply voltage port；
The functional module connects the supply voltage port that external voltage input terminal includes: the functional module by interconnection line layer
The power voltage input terminal is connected by the interconnection line layer；
Each functional module be electrically connected by interconnection line layer include: each functional module supply voltage port by it is described mutually
Connecting line layer links together；
The functional module further includes ground voltage port, and the ground voltage port of the functional module passes through the interconnection line layer
Ground voltage input terminal outside connection.
4. the test method of chip pressure drop as claimed in claim 1, which is characterized in that the external voltage input terminal is ground voltage
Input terminal, the functional module include ground voltage terminal mouth；
The functional module connects the ground voltage port that external voltage input terminal includes: the functional module by interconnection line layer
The ground voltage input terminal is connected by the interconnection line layer；
Each functional module be electrically connected by interconnection line layer include: each functional module ground voltage port by it is described mutually
Connecting line layer links together；
The functional module further includes supply voltage port, and the supply voltage port of the functional module passes through the interconnection line layer
Power voltage input terminal outside connection.
5. the test method of chip pressure drop as claimed in claim 4, which is characterized in that the interconnection line layer includes each for connecting
The supply voltage port of the functional module and the power interconnection line layer of power voltage input terminal, and it is each described for connecting
The ground voltage port of functional module and the ground connection interconnection line layer of ground voltage input terminal；
It includes: that the ground voltage port of each functional module is connect by described that each functional module is electrically connected by interconnection line layer
Ground interconnection line layer links together, and connects same ground voltage input terminal by ground connection interconnection line layer；
The power interconnection line layer includes a plurality of discrete power interconnection line, and a plurality of discrete power interconnection
Line is separately connected external different power voltage input terminal；
The ground voltage port of the multiple functional module is different by a plurality of discrete power interconnection line layer connection
Power voltage input terminal.
6. the test method of chip pressure drop as claimed in claim 1, which is characterized in that the interconnection line layer be include multilayer interconnection line
Multilayered structure.
7. the test method of chip pressure drop as claimed in claim 1, which is characterized in that the chip further includes being mounted on the interconnection
Power switch on line layer, the power switch is between the functional module and external voltage input terminal；
The step of obtaining the first equivalent resistance between the external voltage input terminal and each functional module includes: to obtain institute simultaneously
Equivalent resistance after stating power switch conducting, first equivalent resistance includes between external voltage input terminal and each functional module
Interconnection line layer equivalent resistance and power switch equivalent resistance.
8. a kind of chip improved method, which is characterized in that pass through the test method of the chip pressure drop as described in claim 1~7
Obtain the voltage drop value of each functional module；
The voltage drop value of each functional module and the critical pressure depreciation of each functional module are compared, if voltage drop value is greater than critical pressure drop
Value, then be judged as functional module to be optimized for the functional module；
Interconnection structure is formed on the chip, connecting the functional module to be optimized and external voltage input terminal, or
It is the other function module and external voltage input terminal to connect the functional module periphery to be optimized, reduces described to excellent
The first equivalent resistance between the functional module and external voltage input terminal of change, to reduce the pressure of the functional module to be optimized
Depreciation.
9. chip improved method as claimed in claim 8, which is characterized in that formed interconnection structure the step of include:
Remove segment chip；
At the position of removal segment chip, the interconnection for connecting the functional module to be optimized and external voltage input terminal is formed
Structure.
10. chip improved method as claimed in claim 9, which is characterized in that chip further includes in the dielectric layer on substrate
Filling metal, remove segment chip the step of include:
Remove the filling metal.
11. chip improved method as claimed in claim 10, which is characterized in that the interconnection line layer includes multilayer interconnection line, and
The interconnection line layer is located above the multiple functional module；The multiple functional module is the multilayer for including multilayer functional module
Structure；
The step of removing segment chip includes: removal filling out between undermost interconnection line layer and the functional module of top layer
Fill metal；
The step of forming interconnection structure on the chip includes: to make described having removed formation interconnection structure at filling metal
Interconnection structure is parallel to the interconnection line removed above filling metal；
Conductive plunger is formed between parallel interconnection structure and interconnection line, to connect the functional module to be optimized and external electrical
Press input terminal.
12. chip improved method as claimed in claim 11, which is characterized in that the interconnection line removed above filling metal is institute
State the interconnection line between external voltage input terminal and functional module to be optimized.
13. a kind of test method of chip structure, the chip includes substrate, multiple functional modules on substrate, and
For connecting the interconnection line layer of each functional module；
The functional module connects external voltage input terminal by interconnection line layer；And each functional module is electrically connected by interconnection line layer
Together；
The interconnection line layer be include multilayer interconnection line, wherein n-th layer interconnection line have square resistance Rn；
It is characterized in that,
Obtain the third equivalent resistance between the external voltage input terminal and each functional module；
Obtain the 4th equivalent resistance of multiple functional modules between any two；
In the step of obtaining the third equivalent resistance and four equivalent resistances, the tool obtained to equivalent resistance is loaded into the 1st
Layer and sets a+1 layers to the square resistance of b layers of interconnection line as 0 to the square resistance of a layers of interconnection line, wherein
B is the interconnections in interconnection line layer, and b >=a > 0；
The first resistor feature matrix M of the chip is established based on the third equivalent resistance and the 4th equivalent resistanceii(a), i is
The number of functional module in chip, wherein the element of line n be include RnmAnd Rnn, wherein RnmIt is m-th of functional module to n-th
The Resistance Influence numerical value of a functional module, RnnFor the first equivalent resistance of n-th of functional module；The Rnm=(Rnn+Rmm+
rnm)/2-rnm, wherein rnmThe second equivalent resistance between n-th of functional module and m-th of functional module；
Obtain the 5th equivalent resistance between the external voltage input terminal and each functional module；
Obtain the 6th equivalent resistance of multiple functional modules between any two；
In the step of obtaining the 5th equivalent resistance and six equivalent resistances, the tool obtained to equivalent resistance is loaded into the 1st
Layer and sets a layers to the square resistance of b layers of interconnection line as 0 to the square resistance of a-1 layers of interconnection line；
The second resistance feature matrix M of the chip is established based on the 5th equivalent resistance and the 6th equivalent resistanceii(a-1)；
Obtain resistance correlation matrix M (a)=M of a layers of interconnection lineii(a)-Mii(a-1)；
Obtain the resistance correlation matrix of each interconnection line layer；
By comparing the relationship of the element of same position in the corresponding resistance correlation matrix of different interconnection lines, the interconnection line is analyzed
The performance of layer, to test chip structure.
14. the test method of chip structure as claimed in claim 13, which is characterized in that by comparing the electricity of different interconnection line layers
It hinders in correlation matrix, the step of relationship of the element of same position includes: the corresponding resistance Correlation Moment of the different interconnection line of comparison
In battle array, the relationship of same position element on diagonal of a matrix locating for the 1st column element of the 1st row.
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| CN111965523B (en) * | 2020-08-14 | 2023-05-09 | 上海兆芯集成电路有限公司 | Chip testing method |
| CN116953490B (en) * | 2023-09-19 | 2023-12-26 | 西安智多晶微电子有限公司 | Method, device and system for measuring internal voltage drop of FPGA chip |
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