CN111953352B - Data compression display method and device based on FPGA system and storage medium - Google Patents
Data compression display method and device based on FPGA system and storage medium Download PDFInfo
- Publication number
- CN111953352B CN111953352B CN202010859277.5A CN202010859277A CN111953352B CN 111953352 B CN111953352 B CN 111953352B CN 202010859277 A CN202010859277 A CN 202010859277A CN 111953352 B CN111953352 B CN 111953352B
- Authority
- CN
- China
- Prior art keywords
- data
- fpga
- sampling rate
- fpga system
- compression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/60—General implementation details not specific to a particular type of compression
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a data compression display method, equipment and a storage medium based on an FPGA system, belonging to the field of data signal testing, and the method mainly comprises the following processes: in the operation process of the system, the data collected by the system is divided into two paths: the first path is directly stored in DDR3 in the FPGA system; the second path is compressed and stored into an RAM in the FPGA system; when the equivalent sampling rate is greater than or equal to the real-time sampling rate, reading the collected data points from the DDR3 for display according to the time of the screen pixel points; when the equivalent sampling rate is less than the real-time sampling rate, compressing the acquired data into 2 bits according to every N data, storing the data into the RAM of the FPGA, and after the data are acquired, reading the acquired data points from the RAM for display. The data compression display method provided by the disclosure can prevent effective information from being missed and display more waveform information.
Description
Technical Field
The disclosure belongs to the field of data signal testing, and particularly relates to a data compression display method and device based on an FPGA system and a storage medium.
Background
The statements herein merely provide background related to the present disclosure and may not necessarily constitute prior art.
The digital channel of the logic analyzer system has the vertical resolution of 1 bit, and the data only have 0 and 1, which represent the low level and high level of the signal. And when the real-time sampling rate is greater than the equivalent sampling rate, one screen pixel point corresponds to a plurality of sampling points. When data is read from a storage area for screen display, a traditional method is to directly extract data points and read points corresponding to time in the storage area according to the time of the screen points, and the method has the defect that whether jump edges exist between the extracted points or not is missed.
Disclosure of Invention
Aiming at the technical problems in the prior art, the present disclosure provides a data compression display method, device and storage medium based on an FPGA system. The data compression display method can prevent effective information from being missed and display more waveform information.
At least one embodiment of the present disclosure provides a data compression display method based on an FPGA system, which includes the following processes:
in the operation process of the system, the data collected by the system is divided into two paths: the first path is directly stored in DDR3 in the FPGA system; the second path is compressed and stored into an RAM in the FPGA system;
when the equivalent sampling rate is greater than or equal to the real-time sampling rate, reading collected data points from DDR3 for display according to the time of screen pixel points;
and when the equivalent sampling rate is less than the real-time sampling rate, compressing the acquired data into 2 bits according to every N data, storing the data into the RAM of the FPGA, and reading the acquired data points from the RAM for display after the data are acquired.
And further, temporarily storing the remaining data with the number less than N into a buffer area in the FPGA system, and continuously compressing the data with the data collected next time.
Furthermore, in the process of compressing data, the compressed data can be stored in a management module in the FPGA system, and after the management module needs to remember the trigger address data, the data is stored in an RAM of the FPGA system.
Further, the main process of compressing the collected data into 2 bits according to every N data is as follows:
(1) receiving parameters by the FPGA;
(2) and calculating the equivalent sampling rate, comparing the equivalent sampling rate with the real-time sampling rate, and judging whether compression is needed.
(3) Initializing a storage area, and compressing the storage area until the storage area does not receive a trigger signal;
(4) and after receiving the trigger signal, the post-trigger counter starts counting, and the compression is finished after the number of post-trigger compression points is reached.
Further, the parameters in step (1) include time base, storage depth, compression coefficient and post-trigger compression point number.
Further, in step (2), the equivalent sampling rate and the real-time sampling rate are obtained through the time base and the storage depth.
Furthermore, the first path of the data collected by the system is directly stored in the FPGA through speed reduction processing.
Further, the data rate of the first path in the acquired data is 312.5MHz, and the bit width is 8 bits; the second way has a data rate of 156.25MHz, 16 bits wide.
At least one embodiment of the present disclosure further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the data compression display method based on the FPGA system when executing the program.
At least one embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a data compression display method based on an FPGA system as described in any one of the above.
The beneficial effects of this disclosure are as follows:
the data compression display method provided by the present disclosure adopts 2 bits to represent one data, and each pixel point has three states to represent: high, low and change, if the data is high, it can be represented by "11", if the data is low, it can be represented by "00", if the change, there is a jump edge, it is represented by "10", "01", so that when the data is extracted and displayed, it can prevent from missing effective information, and display more waveform information.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to be construed as limiting the disclosure.
FIG. 1 is a diagram illustrating logic waveform data displayed under the prior art and the disclosed method;
fig. 2 is a schematic diagram of FPGA data processing provided in an embodiment of the present disclosure;
fig. 3 is a flowchart of compression control during FPGA runtime provided in the embodiment of the present disclosure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
In the description of the present disclosure, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present disclosure.
As shown in fig. 1, the digital channel of the logic analyzer system has a vertical resolution of 1 bit, and has only 0 and 1 data, which represent the low and high states of the signal. And when the real-time sampling rate is greater than the equivalent sampling rate, one screen pixel point corresponds to a plurality of sampling points. When data is read from a storage area for screen display, a traditional method is to directly extract data points and read points corresponding to time in the storage area according to the time of the screen points, and the method has the defect that whether jump edges exist between the extracted points or not is missed.
The data compression display method provided by the disclosure adopts 2 bits to represent one data, and each pixel point has three states: if the corresponding data on the pixel point is not changed, the data is represented by 11 if the data is high, the data is represented by 00 if the data is low, and a jumping edge exists if the data is changed, the jumping edge is represented by 10 and 01, so that effective information can be prevented from being missed when the data is read and displayed, and more waveform information can be displayed.
Further, if the method provided by the present disclosure is adopted, software is used to determine whether the jump edge information exists in all the points, all the data points need to be read into the memory, when the storage depth is large, the data size is huge, and the time consumed for reading data and compressing the algorithm is long, so that the screen refreshing requirement cannot be met. In specific application, data compression is realized in an FPGA system, so that the efficiency of data compression can be greatly improved, and the requirement of screen refreshing is met.
As shown in fig. 2, the data processing method of the internal FPGA system of the logic analyzer provided in this embodiment mainly includes two types, one is that acquired data is directly stored to DDR3 through speed reduction processing; and secondly, compressing equivalent data in the running state and storing the equivalent data into the RAM.
Specifically, when the system runs, data acquired by the system is mainly divided into two paths, wherein one path of data is stored to DDR3 at a rate of 312.5MHz and with a bit width of 8 bits; and the other path of data with the speed of 156.25MHz and the bit width of 16 bits enters a data compression module and is finally stored into the RAM.
Specifically, when the acquired data is read from a storage area in the logic analyzer, when the equivalent sampling rate is greater than or equal to the real-time sampling rate, the software reads the acquired data points from the DDR3 of the FPGA system for display according to the time of the screen pixel points;
but when the equivalent sampling rate is less than the real-time sampling rate, equivalent data compression is required. And the data storage and compression module is used for setting a compression coefficient N and a compressed data amount. And compressing every N data of the 16-bit data acquired and input by the second path into 2 bits, and storing the 2 bits into the RAM of the FPGA system. The size of the RAM of the FPGA system is 4kbit, and data with less than N number left in the compression process can be temporarily stored in a buffer area in the FPGA system, and compressed after forming N data with the next 16-bit data. When the required amount of data is reached, the compression is ended.
It should be noted that. In the operation compression process, compressed data can be stored in an FPGA system management module firstly, the FPGA system management module needs to remember a trigger address and then stores the compressed data into an RAM address, and finally, after data acquisition is finished, interruption is generated, and software can read the data from the RAM for display.
Further, in this embodiment, the compression control process during the FPGA operation mainly includes the following steps:
the method comprises the following steps: receiving a fpga parameter;
step two: calculating an equivalent sampling rate, comparing the equivalent sampling rate with the real-time sampling rate, and judging whether compression is needed;
step three: initializing a storage area, and compressing the storage area until the storage area does not receive a trigger signal;
step four: after receiving the trigger signal, the post-trigger counter starts counting, and the compression is finished after the number of post-trigger compression points is reached.
Specifically, as shown in fig. 3, the FPGA system first receives parameters such as time base, storage depth, compression coefficient, post-trigger compression point number set by software. Wherein, the time base and the storage depth obtain an equivalent sampling rate and a real-time sampling rate, and whether compression is enabled is judged; and the post-trigger compression point number is used for judging the compressed point number after triggering.
It should be noted that the storage area RAM of the FPGA system is only 4kbit, and when the storage depth is deep, the compression point in the RAM is prevented from being covered.
If the compression needs to be started, the initialization buffer area and the RAM storage area in the FPGA system are compressed all the time before the trigger signal does not arrive. Every N data are compressed into 2 bits and stored in the RAM of the FPGA. Less than N data are temporarily stored in the buffer area, and are compressed after forming N data with the next 16-bit data. When the trigger signal comes, the compression counter is triggered to count after being started, and when the required data volume is reached, the compression is finished.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present disclosure and not to limit, although the present disclosure has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present disclosure without departing from the spirit and scope of the technical solutions, and all of them should be covered in the claims of the present disclosure.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (9)
1. A data compression display method based on an FPGA system is characterized in that:
in the operation process of the system, the data collected by the system is divided into two paths: the first path of collected data is subjected to speed reduction processing and directly stored in DDR3 in the FPGA system; the equivalent data in the second operation state can be compressed and stored in an RAM in the FPGA system;
when the equivalent sampling rate is greater than or equal to the real-time sampling rate, reading the collected data points from the DDR3 for display according to the time of the screen pixel points;
when the equivalent sampling rate is smaller than the real-time sampling rate, compressing the acquired data into 2 bits according to every N data, storing the 2 bits into the RAM of the FPGA, and reading the acquired data points from the RAM for displaying after the data are acquired;
the main steps of compressing the collected data into 2 bits according to every N data are as follows:
(1) receiving parameters by the FPGA;
(2) calculating an equivalent sampling rate, comparing the equivalent sampling rate with the real-time sampling rate, and judging whether compression is needed;
(3) initializing a storage area, and compressing the storage area until the storage area does not receive the trigger signal;
(4) and after receiving the trigger signal, the post-trigger counter starts counting, and the compression is finished after the number of post-trigger compression points is reached.
2. The data compression display method based on the FPGA system as recited in claim 1, wherein: and temporarily storing the remaining data with the number less than N into a buffer area in the FPGA system, and continuously compressing the data with the data acquired next time.
3. The data compression display method based on the FPGA system as recited in claim 1, characterized in that: and in the process of compressing the data, the compressed data can be stored in a management module in the FPGA system, and after the management module needs to remember the trigger address data, the data is stored in an RAM of the FPGA system.
4. The data compression display method based on the FPGA system as recited in claim 1, characterized in that: the parameters in the step (1) comprise time base, storage depth, compression coefficient and post-trigger compression point number.
5. The data compression display method based on the FPGA system as recited in claim 1, characterized in that: and (2) obtaining the equivalent sampling rate and the real-time sampling rate through the time base and the storage depth.
6. The data compression display method based on the FPGA system as recited in claim 1, characterized in that: the first path of the data collected by the system is directly stored in the FPGA through speed reduction processing.
7. The data compression display method based on the FPGA system as recited in claim 1, characterized in that: the data rate of the first path in the acquired data is 312.5MHz, and the bit width is 8 bits; the second way has a data rate of 156.25MHz and a bit width of 16 bits.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement a method for data compression display based on an FPGA system as claimed in any one of claims 1 to 7.
9. A computer-readable storage medium, on which a computer program is stored, wherein the program, when executed by a processor, implements a method for data compression display based on an FPGA system as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010859277.5A CN111953352B (en) | 2020-08-24 | 2020-08-24 | Data compression display method and device based on FPGA system and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010859277.5A CN111953352B (en) | 2020-08-24 | 2020-08-24 | Data compression display method and device based on FPGA system and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111953352A CN111953352A (en) | 2020-11-17 |
| CN111953352B true CN111953352B (en) | 2022-09-30 |
Family
ID=73359849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010859277.5A Active CN111953352B (en) | 2020-08-24 | 2020-08-24 | Data compression display method and device based on FPGA system and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111953352B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117424606B (en) * | 2023-12-18 | 2024-04-16 | 成都行芯科技有限公司 | Waveform data compression method, device, electronic device and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8305903B1 (en) * | 2008-03-31 | 2012-11-06 | C Speed, Llc | Data acquisition system for test and measurement signals |
| CN102820853A (en) * | 2011-06-06 | 2012-12-12 | 特克特朗尼克公司 | Interleaved digital down-conversion on a test and measurement instrument |
| CN103604964A (en) * | 2013-11-15 | 2014-02-26 | 中国电子科技集团公司第四十一研究所 | Method for improving digital channel waveform capture rate of mixed oscilloscope |
| CN105610525A (en) * | 2015-12-23 | 2016-05-25 | 宁波大学 | Broadband compressed spectrum sensing method based on sub-band matching selection |
| CN106324312A (en) * | 2016-08-03 | 2017-01-11 | 深圳市鼎阳科技有限公司 | Method for oscilloscope to rapidly and precisely read data in vertical direction and oscilloscope |
| CN110311686A (en) * | 2019-07-11 | 2019-10-08 | 南京信息工程大学 | A kind of pseudorandom equivalent sampling signal reconfiguring method of compressed sensing |
-
2020
- 2020-08-24 CN CN202010859277.5A patent/CN111953352B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8305903B1 (en) * | 2008-03-31 | 2012-11-06 | C Speed, Llc | Data acquisition system for test and measurement signals |
| CN102820853A (en) * | 2011-06-06 | 2012-12-12 | 特克特朗尼克公司 | Interleaved digital down-conversion on a test and measurement instrument |
| CN103604964A (en) * | 2013-11-15 | 2014-02-26 | 中国电子科技集团公司第四十一研究所 | Method for improving digital channel waveform capture rate of mixed oscilloscope |
| CN105610525A (en) * | 2015-12-23 | 2016-05-25 | 宁波大学 | Broadband compressed spectrum sensing method based on sub-band matching selection |
| CN106324312A (en) * | 2016-08-03 | 2017-01-11 | 深圳市鼎阳科技有限公司 | Method for oscilloscope to rapidly and precisely read data in vertical direction and oscilloscope |
| CN110311686A (en) * | 2019-07-11 | 2019-10-08 | 南京信息工程大学 | A kind of pseudorandom equivalent sampling signal reconfiguring method of compressed sensing |
Non-Patent Citations (1)
| Title |
|---|
| 一种基于FPGA的高速波形采集与实时数据压缩方法;宋光德等;《电子测量与仪器学报》;20040330;第18卷(第01期);第47-51页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111953352A (en) | 2020-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2317247A (en) | Displaying buffer accesses | |
| CN111953352B (en) | Data compression display method and device based on FPGA system and storage medium | |
| CN104978739A (en) | Image object selection method and apparatus | |
| CN103139567B (en) | The method and apparatus of a kind of image compression and decompression | |
| CN108716916B (en) | Distributed parallel star point centroid extraction method based on superblock and FPGA implementation device | |
| CN110737600A (en) | Collapse statistical data display method and device, computer equipment and storage medium | |
| US4513395A (en) | Apparatus and method for acquiring multiple groups of data signals from a synchronous logic system | |
| CN107169057B (en) | Method and device for detecting repeated pictures | |
| CN112185453A (en) | Read interference test method and device, computer readable storage medium and electronic equipment | |
| CN105204799B (en) | A kind of raising method of multichannel storage logic analyser display refresh rates deeply | |
| US8381234B2 (en) | System and method for managing applications having logical pointer and flag | |
| CN114741266B (en) | Page white screen duration determination method and device, electronic equipment and storage medium | |
| CN107478884B (en) | A kind of method and oscillograph of quick display waveform search result | |
| CN112764673B (en) | Hyperspectral linear array data storage rate optimization method, device and storage medium | |
| CN115048309B (en) | Non-intrusive APP software performance test method and system | |
| CN111131812A (en) | Broadcast time testing method and device and computer readable storage medium | |
| CN109783024A (en) | Data storage handling method and device | |
| CN112199131B (en) | Page detection method, device and equipment | |
| CN116736234B (en) | FPGA-based radar data acquisition method, system and device | |
| CN117331847B (en) | Automatic test method and system supporting graphic interface | |
| CN112035314B (en) | Memory leakage monitoring method and device and electronic equipment | |
| CN111046012B (en) | Method and device for extracting inspection log, storage medium and electronic equipment | |
| CN117215439A (en) | Touch coordinate determination method and device and electronic equipment | |
| CN116303024A (en) | Method, system, electronic device and storage medium for acquiring interface information of android application during running | |
| Usama et al. | PyEye: An Integrated Approach for Signal Integrity Assessment and Eye Diagram Generation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 266555 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Applicant after: CLP kesiyi Technology Co.,Ltd. Address before: 266555 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Applicant before: CHINA ELECTRONICS TECHNOLOGY INSTRUMENTS Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |