CN111952446A - Structure of resistive random access memory and forming method thereof - Google Patents
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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Abstract
A structure of a resistive random access memory and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a bottom electrode on the substrate; forming a resistance change layer on the bottom electrode; forming a top electrode on the resistive layer; and forming a first protective layer on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistive layer. The performance of the formed resistive random access memory is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a structure of a resistive random access memory and a forming method thereof.
Background
In Integrated Circuit (IC) devices, Resistive Random Access Memory (RRAM) is an emerging technology for next-generation nonvolatile Memory devices. A resistive random access memory is a memory structure that includes an array of resistive random access memory cells, each of which uses a resistance value rather than charge to store a small amount of data. Specifically, each resistive random access memory cell includes a resistive material layer, the resistance of which may be adjusted to show a logical "0" or a logical "1".
In advanced technology nodes, the component size is scaled down and the size of the memory device is correspondingly reduced, which requires that the precision of each process for forming the resistive random access memory is correspondingly improved to meet the requirement for high performance of the resistive random access memory.
However, the performance of the conventional resistive random access memory still needs to be improved.
Disclosure of Invention
The invention aims to provide a structure of a resistive random access memory and a forming method thereof, which can improve the performance of the resistive random access memory.
In order to solve the above technical problem, the present invention provides a method for forming a resistive random access memory cell, including: providing a substrate; forming a bottom electrode on the substrate; forming a resistance change layer on the bottom electrode; forming a top electrode on the resistive layer; and forming a first protective layer on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistive layer.
Optionally, the process for forming the first protection layer includes: and (5) a deposition process.
Optionally, the material of the first protective layer comprises a nitride, carbide or carbonitride.
Optionally, the material of the first protection layer includes silicon nitride or silicon carbonitride.
Optionally, the thickness range of the first protection layer includes: 100nm to 200 nm.
Optionally, before forming the first protection layer, the method further includes: forming a second protective layer on the surface of the top electrode; forming the first protective layer on the second protective layer.
Optionally, after forming the first protection layer on the top surface of the top electrode, the sidewall surface of the top electrode, and the sidewall surface of the resistive layer, the method further includes: and forming an isolation layer on the substrate and the surface of the first protection layer.
Optionally, the method for forming the resistive layer and the top electrode includes: forming a resistance change layer material on the surface of the substrate and the surface of the bottom electrode; forming a top electrode material layer on the resistance change layer material; forming a first mask layer on the top electrode material layer, wherein a part of the top electrode material layer is exposed by the first mask layer; and etching the top electrode material layer and the resistance change layer material by taking the first mask layer as a mask to form the top electrode and the resistance change layer.
Optionally, before forming the resistance change layer material on the surface of the substrate and the surface of the bottom electrode, the method further includes: and forming an etching stop layer on the substrate, wherein the etching stop layer is also positioned on the surface of the side wall of the bottom electrode, and the surface of the etching stop layer is lower than or flush with the top surface of the bottom electrode.
Optionally, the forming method of the bottom electrode includes: forming a bottom electrode material layer on the surface of the substrate; forming a second mask layer on the surface of the bottom electrode material layer, wherein the second mask layer exposes a part of the surface of the bottom electrode material layer; and etching the bottom electrode material layer by taking the second mask layer as a mask until the surface of the substrate is exposed, and forming the bottom electrode on the substrate.
Optionally, the substrate includes: a substrate; the device layer is positioned on the substrate and comprises a device structure positioned on the substrate, an interconnection structure electrically connected with the device structure and a dielectric layer, wherein the dielectric layer is positioned on the surface of the substrate, the surface of the device structure and the surface of the interconnection structure, and the top surface of the interconnection structure is exposed out of the dielectric layer; the bottom electrode is located on the surface of the interconnection structure.
Optionally, the material of the bottom electrode comprises a metal; the metal comprises tungsten or titanium nitride.
Optionally, the material of the resistance change layer comprises a transition metal oxide; the transition metal oxide includes hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, or titanium oxide.
Optionally, the material of the top electrode comprises a metal, and the metal comprises copper, aluminum, tungsten, or titanium nitride.
Correspondingly, the invention also provides a resistive random access memory unit formed by adopting any one of the methods, which comprises: a substrate; a bottom electrode on the substrate; a resistance change layer on the bottom electrode; a top electrode on the resistive layer; and the first protective layer is positioned on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistive layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the protective layer is formed on the side wall of the resistance-change layer to protect the side wall of the resistance-change layer, the protective layer can prevent external impurities from invading the resistance-change layer, so that the side wall of the resistance-change layer is not easy to oxidize in a subsequent process, the appearance and the material of the resistance-change layer are not easy to change in a subsequent process, and the uniformity of the appearance and the size of the resistance-change layer and the stability of the material of the resistance-change layer are improved. Therefore, the protective layer is formed, so that the resistance uniformity of the resistive layer in each resistive random access memory unit can be improved, the consistency of the electrical performance of each resistive random access memory unit is further improved, and the performance of the resistive random access memory is improved.
Drawings
FIG. 1 is a cross-sectional view of a RRAM structure according to the present invention;
fig. 2 to 9 are schematic cross-sectional structural diagrams of a forming process of a resistive random access memory according to an embodiment of the invention.
Detailed Description
As described in the background art, the performance of the resistive random access memory formed in the prior art needs to be improved. The following description and analysis are made in conjunction with a structure of a resistance random access memory.
Fig. 1 is a schematic cross-sectional view of a resistive random access memory structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a resistance random access memory structure thereon, the resistance random access memory structure includes a bottom electrode 101 located on the substrate 100, a resistance layer 102 located on the bottom electrode 101, and a top electrode 103 located on the resistance layer 102, and the substrate 100 includes a dielectric layer 104 covering the top and sidewalls of the top electrode 103 and the sidewalls of the resistance layer 102.
In the structure of the resistive random access memory, the dielectric layer 104 is made of silicon oxide, the resistive layer 102 is made of transition metal oxide, and the transition metal oxide is incompletely oxidized transition metal oxide.
After the top electrode 103 and the resistive random access memory 102 are formed, a dielectric layer 104 completely covering the resistive random access memory structure needs to be formed on the substrate to perform a subsequent process, and the forming process of the dielectric layer 104 is a chemical vapor deposition process. Since the material of the dielectric layer usually includes an oxide, the reaction gas of the chemical vapor deposition process includes an oxygen-containing gas, and since the material of the resistive layer 102 is an incompletely oxidized transition metal oxide, the oxygen can oxidize the resistive layer 102 from the position of the sidewall of the resistive layer 102, and the sidewall of the resistive layer 102 is oxidized, which may cause the volume of the resistive layer 102 to increase, the thickness of the sidewall of the resistive layer 102 in the direction perpendicular to the substrate 100 is increased, which may cause the thickness of the resistive layer 102 to be non-uniform, which may cause the resistance of the resistive layer of each resistive random access memory unit to be non-uniform, which may affect the performance of the resistive random access memory unit.
In order to solve the problems, the invention provides a resistive random access memory and a forming method thereof, wherein a protective layer is formed on the side wall of a resistive layer to protect the side wall of the resistive layer, so that the resistive layer cannot be oxidized in the subsequent process of forming a dielectric layer, and the problem that the resistance of the resistive layer of each resistive random access memory unit is not uniform due to the fact that the thickness of the side wall of the resistive layer is changed because the side wall of the resistive layer is oxidized to cause the thickness change of the side wall of the resistive layer is avoided, so that the uniformity of the electrical performance of each resistive random access memory unit is improved, and the performance of the resistive random access memory is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 9 are schematic cross-sectional structural diagrams of a forming process of a resistive random access memory according to an embodiment of the invention.
Referring to fig. 2, a substrate is provided.
In this embodiment, the substrate includes a base 200, a device layer 300 on the base 200, and the device layer 300 includes a device structure (not shown) on the base 200, an interconnect structure (not shown) electrically connected to the device structure, and a dielectric layer (not shown) on the surface of the base 200, the surface of the device structure, and the surface of the interconnect structure, and the dielectric layer exposes the top surface of the interconnect structure.
The material of the substrate 200 comprises monocrystalline silicon, polycrystalline silicon, amorphous silicon or a semiconductor material of silicon, germanium, silicon germanium and gallium arsenide; in this embodiment, the material of the substrate 200 is monocrystalline silicon.
In this embodiment, the material of the dielectric layer includes silicon oxide; in other embodiments, the material of the dielectric layer comprises silicon nitride.
In this embodiment, the device structure includes a gate structure; in other embodiments, the device structure can be other than a gate structure.
In this embodiment, the interconnect structure includes a metal wire; in other embodiments, the interconnect structure can be other than a metal wire.
In other embodiments, the substrate includes a base and a dielectric layer on the base, and the substrate can be free of a device layer on the base.
In this embodiment, a bottom electrode is subsequently formed on the substrate. Please refer to fig. 3 to fig. 4.
Referring to fig. 3, a bottom electrode material layer 201 is formed on the surface of the substrate; a second mask layer 202 is formed on the surface of the bottom electrode material layer 201, and the second mask layer 202 exposes a portion of the surface of the bottom electrode material layer 201.
The process of forming the bottom electrode material layer 201 includes a physical vapor deposition process, an electroplating process, or an electroless plating process. In this embodiment, the process of forming the bottom electrode material layer 201 includes a physical vapor deposition process.
The material of the bottom electrode material layer 201 includes tungsten or titanium nitride.
The material of the second mask layer 202 includes photoresist.
Referring to fig. 4, the bottom electrode material layer 201 is etched with the second mask layer 202 as a mask until the surface of the substrate is exposed, and the bottom electrode 204 is formed on the substrate, where the bottom electrode 204 is located on the surface of the interconnection structure in the substrate.
In this embodiment, the process of etching the bottom electrode material layer 201 includes an anisotropic dry etching process.
In this embodiment, after the bottom electrode 204 is formed, the second mask layer 202 is removed; the process of removing the second mask layer 202 includes an ashing process.
Referring to fig. 5, after removing the second mask layer 202, an etch stop layer 205 is formed on the substrate, where the etch stop layer 205 is also located on the sidewall surface of the bottom electrode 204.
The method for forming the etching stop layer 205 comprises the following steps: forming the etch stop layer material (not shown) on the substrate surface and the sidewalls and top surface of the bottom electrode 204; the etch stop layer material is polished using a chemical mechanical polishing process until the top surface of the bottom electrode 204 is exposed.
In this embodiment, the material of the etch stop layer 205 includes silicon nitride or silicon carbide nitride; the process for forming the etch stop layer material includes a chemical vapor deposition process.
The etching stop layer 205 is used for protecting the substrate when a resistance change layer and a top electrode are formed on the bottom electrode 204 in the following step, so as to prevent the substrate from being damaged by etching.
In this embodiment, the surface of the etch stop layer 205 is flush with the top surface of the bottom electrode 204; in other embodiments, the etch stop layer 205 surface is lower than the top surface of the bottom electrode 204.
The significance of the etch stop layer 205 surface being below or flush with the top surface of the bottom electrode 204 is: if the surface of the etching stop layer 205 is higher than the top surface of the bottom electrode 204, the contact area between the resistance change layer formed on the surface of the bottom electrode 204 and the bottom electrode 204 is too small or cannot be contacted, and the small contact area between the resistance change layer and the bottom electrode 204 will cause the contact resistance between the resistance change layer and the bottom electrode 204 to be increased, thereby increasing the power consumption of the device and being not beneficial to the improvement of the device performance; failure to contact the resistance change layer with the bottom electrode 204 may result in an open circuit and affect device performance.
In this embodiment, after the etching stop layer 205 is formed, a resistance change layer is formed on the bottom electrode 204; and forming a top electrode on the resistance change layer. Please refer to fig. 6 to 7.
Referring to fig. 6, a resistance change layer material layer 210 is formed on the surface of the substrate and the surface of the bottom electrode 204; forming a top electrode material layer 211 on the resistance change layer material layer 210; a first mask layer 213 is formed on the top electrode material layer 211, and the first mask layer 213 exposes a portion of the top electrode material layer 211.
In this embodiment, before forming the first mask layer 213, a second protection layer material layer 212 is formed on the surface of the top electrode material layer 211.
The material of the resistance change layer material layer comprises transition metal oxide; in this embodiment, the material of the resistance change layer material layer includes hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, or titanium oxide; the process of forming the resistance change layer material layer 210 includes a chemical vapor deposition process.
The material of the top electrode material layer comprises a metal; in this embodiment, the material of the top electrode material layer includes copper, aluminum, tungsten, or titanium nitride.
The process of forming the top electrode material layer 211 includes a physical vapor deposition process, an electroplating process, or an electroless plating process; in the present embodiment, the process of forming the top electrode material layer 211 includes a physical vapor deposition process.
In this embodiment, a second passivation layer 212 is formed on the top electrode material layer 211. The second protective layer material comprises silicon nitride or silicon carbonitride; the process of forming the second protective layer material 212 includes a chemical vapor deposition process. The second protective layer material is used to protect the top electrode material layer 211 from being damaged in the subsequent process.
In other embodiments, the second passivation layer 212 can be formed on the surface of the top electrode material layer 211.
In this embodiment, the first mask layer 213 includes a patterned photoresist.
Referring to fig. 7, the top electrode material layer 211 and the resistive layer material layer 210 are etched by using the first mask layer 213 as a mask to form a resistive layer 310 and a top electrode 311 on the surface of the resistive layer.
In this embodiment, before etching the top electrode material layer 211, etching the second protection layer material layer 212 by using the first mask layer 213 as a mask to form a second protection layer 312 on the surface of the top electrode 311.
In this embodiment, the process of etching the second protective layer material layer 212, the top electrode material layer 211 and the resistance change layer material layer 210 includes an anisotropic dry etching process.
In this embodiment, during the etching of the second protective layer material layer 212, the top electrode material layer 211 and the resistance change layer material layer 210, a portion of the etch stop layer 205 is also etched.
In this embodiment, the second protection layer 312 is used to protect the top surface of the top electrode 311, so as to prevent the top electrode from being damaged or oxidized by etching in the subsequent process, thereby affecting the performance of the device. In other embodiments, the second protective layer 312 may not be present.
In this embodiment, after the second protection layer 312, the top electrode 311 and the resistance change layer 310 are formed, the first mask layer 213 is removed; the process of removing the first mask layer 213 includes an ashing process.
Referring to fig. 8, a first passivation layer 401 is formed on the top surface of the second passivation layer 312, the sidewall surface of the top electrode 311, and the sidewall surface of the resistive layer 310.
The material of the first protective layer 401 includes nitride, carbide, or carbonitride; in this embodiment, the material of the first protection layer 401 includes silicon nitride or silicon carbonitride.
In this embodiment, the process of forming the first protection layer 401 includes a deposition process.
In this embodiment, the thickness range of the first protection layer includes: 100nm to 200 nm.
The significance of forming the first protective layer 401 on the top surface of the second protective layer 312, the sidewall surface of the top electrode 311, and the sidewall surface of the resistive layer 310 is: the first protective layer 401 formed on the surface of the side wall of the resistive random access memory unit 310 protects the side wall of the resistive random access memory unit 310, and prevents the side wall of the resistive random access memory unit 310 from being oxidized in a subsequent isolation layer forming process, so that the side wall of the resistive random access memory unit 310 is prevented from being oxidized to increase the volume and cause the thickness of the resistive random access memory unit 310 to change, the uniformity of the thickness of the resistive random access memory unit 310 is improved, the uniformity of the resistance of the resistive random access memory unit is improved, the uniformity of the electrical performance of the resistive random access memory unit is improved, and the performance of the resistive random access memory is improved.
The significance of selecting silicon nitride or silicon carbide nitride as the material of the first protective layer 401 is: oxygen is not involved in the formation process of the silicon nitride or the silicon carbide nitride, so that the side wall of the resistance change layer 310 is prevented from being oxidized due to contact with the oxygen; meanwhile, the silicon nitride or silicon carbonitride has a compact structure, so that oxygen in a subsequent process for forming the isolation layer can be effectively blocked, and the side wall of the resistance change layer 310 is prevented from being oxidized due to oxygen contact.
The significance of selecting the thickness range of the first protective layer 401 to be 100nm to 200nm is: if the thickness of the first protection layer 401 is less than 100nm, the protection effect of the first protection layer 401 on the side wall of the resistance-change layer 310 is weak, the meaning of forming the first protection layer 401 on the side wall surface of the resistance-change layer 310 is lost, the first protection layer 401 does not play an expected role, and meanwhile, the process with too small thickness is difficult to control accurately; if the thickness of the first protection layer 401 is greater than 200nm, the thicker first protection layer 401 is not compatible with the logic of the circuit, which may affect the performance during the period.
Referring to fig. 9, after forming a first protective layer 401, an isolation layer 402 is formed on the substrate and on the first protective layer 401.
In this embodiment, after forming the first protection layer 401 and before forming the isolation layer 402, a second stop layer (not shown) is further formed on the substrate and on the surface of the first protection layer 401; in other embodiments, the second stop layer may not be formed.
In the present embodiment, the material of the isolation layer 402 includes silicon oxide; the process of forming the isolation layer 402 includes a chemical vapor deposition process.
In this embodiment, the isolation layer 402 serves as a mutual isolation for semiconductor structures formed subsequently on the substrate.
Accordingly, an embodiment of the present invention further provides a resistive random access memory formed by the method, please refer to fig. 9, which includes:
a substrate;
a bottom electrode 204 located on the substrate;
a resistive layer 310 on the bottom electrode 204;
a top electrode 311 on the resistive layer 310;
and a first protective layer 401 on top and sidewall surfaces of the top electrode 311 and sidewall surfaces of the resistive layer 310.
The following description will be made with reference to the accompanying drawings.
In this embodiment, the substrate includes a base 200 and a device layer 300 on the base 200.
In this embodiment, the substrate further has an etch stop layer 205, the bottom electrode 204 is located in the etch stop layer 205, the etch stop layer 205 is also located on a sidewall surface of the bottom electrode 204, and a surface of the etch stop layer 205 is lower than or flush with a top surface of the bottom electrode 204.
In this embodiment, the method further includes: a second protective layer 312 on the surface of the top electrode 311, wherein the first protective layer 401 is located on the second protective layer 312.
In this embodiment, the method further includes: an isolation layer 402 disposed on the substrate and on the surface of the first protection layer 401.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method for forming a resistive random access memory cell, comprising:
providing a substrate;
forming a bottom electrode on the substrate;
forming a resistance change layer on the bottom electrode;
forming a top electrode on the resistive layer;
and forming a first protective layer on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistive layer.
2. The method for forming the resistive random access memory cell according to claim 1, wherein the process for forming the first protective layer comprises: and (5) a deposition process.
3. The method of forming a resistive random access memory cell according to claim 1, wherein the material of the first protective layer comprises a nitride, carbide, or carbonitride.
4. The method of forming the resistive random access memory cell according to claim 3, wherein the material of the first protective layer comprises silicon nitride or silicon carbonitride.
5. The method of forming a resistive random access memory cell according to claim 1, wherein the range of the thickness of the first protective layer comprises: 100nm to 200 nm.
6. The method of forming a resistive random access memory cell according to claim 1, further comprising, prior to forming the first protective layer: forming a second protective layer on the surface of the top electrode; forming the first protective layer on the second protective layer.
7. The method of forming a resistive random access memory cell according to claim 1, further comprising, after forming a first protective layer on a top surface of the top electrode, a sidewall surface of the top electrode, and a sidewall surface of the resistive layer: and forming an isolation layer on the substrate and the surface of the first protection layer.
8. The method of forming a resistive random access memory cell according to claim 1, wherein the method of forming the resistive layer and the top electrode comprises: forming a resistance change layer material on the surface of the substrate and the surface of the bottom electrode; forming a top electrode material layer on the resistance change layer material; forming a first mask layer on the top electrode material layer, wherein a part of the top electrode material layer is exposed by the first mask layer; and etching the top electrode material layer and the resistance change layer material by taking the first mask layer as a mask to form the top electrode and the resistance change layer.
9. The method for forming a resistive random access memory cell according to claim 8, wherein before forming the resistive layer material on the surface of the substrate and the surface of the bottom electrode, the method further comprises: and forming an etching stop layer on the substrate, wherein the etching stop layer is also positioned on the surface of the side wall of the bottom electrode, and the surface of the etching stop layer is lower than or flush with the top surface of the bottom electrode.
10. The method of forming a resistive random access memory cell according to claim 1, wherein the method of forming the bottom electrode comprises: forming a bottom electrode material layer on the surface of the substrate; forming a second mask layer on the surface of the bottom electrode material layer, wherein the second mask layer exposes a part of the surface of the bottom electrode material layer; and etching the bottom electrode material layer by taking the second mask layer as a mask until the surface of the substrate is exposed, and forming the bottom electrode on the substrate.
11. The method of forming a resistive random access memory cell according to claim 1, wherein the substrate comprises: a substrate and a device layer on the substrate; the device layer comprises a device structure positioned on the surface of the substrate, an interconnection structure electrically connected with the device structure and a dielectric layer; the dielectric layer is positioned on the surface of the substrate, the surface of the device structure and the surface of the interconnection structure, and the top surface of the interconnection structure is exposed out of the dielectric layer; the bottom electrode is located on the surface of the interconnection structure.
12. The method of forming a resistive random access memory cell according to claim 1, wherein the material of the bottom electrode comprises a metal; the metal comprises tungsten or titanium nitride.
13. The method of forming a resistive random access memory cell according to claim 1, wherein a material of the resistive layer comprises a transition metal oxide; the transition metal oxide includes hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, or titanium oxide.
14. The method of forming a resistive random access memory cell according to claim 1, wherein the material of the top electrode comprises a metal comprising copper, aluminum, tungsten, or titanium nitride.
15. A resistive random access memory cell formed by the method of any one of claims 1 to 14, comprising:
a substrate;
a bottom electrode on the substrate;
a resistance change layer on the bottom electrode;
a top electrode on the resistive layer;
and the first protective layer is positioned on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistive layer.
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