CN111952250A - Manufacturing method of array substrate and array substrate - Google Patents
Manufacturing method of array substrate and array substrate Download PDFInfo
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- CN111952250A CN111952250A CN202010795067.4A CN202010795067A CN111952250A CN 111952250 A CN111952250 A CN 111952250A CN 202010795067 A CN202010795067 A CN 202010795067A CN 111952250 A CN111952250 A CN 111952250A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
Abstract
The invention provides a manufacturing method of an array substrate and the array substrate, a first insulating layer and an active layer film which cover a first metal layer are sequentially formed on a substrate, wherein the etching rate of the active layer film is greater than that of the first insulating layer, the active layer film and the first insulating layer are overlapped up and down, the active layer film is used as a guide layer of the first insulating layer when in hole opening, the active layer film and the first insulating layer are opened at the position corresponding to the first contact hole, a first contact hole penetrating through the active layer film and the first insulating layer from top to bottom can be formed, due to the different etching rates of the active layer film and the first insulating layer, the active layer film is guided when in hole opening, the undercut problem of the first insulating layer at the lower part is avoided, meanwhile, a good taper angle can be obtained at the position of the first contact hole, so that the risk of wire breakage of a second metal layer filled into the first contact hole later is avoided, the yield of the product is effectively improved, a new photomask is not needed, and the cost is saved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of an array substrate and the array substrate.
Background
The liquid crystal display device has the advantages of good picture quality, small volume, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, is dominant in the field of flat panel display, and is widely applied to electronic equipment such as a liquid crystal television, a mobile phone, a Personal Digital Assistant (PDA), a digital camera, a computer screen or a notebook computer screen. A liquid crystal display device includes opposing Color Filter substrates (CF) and thin film transistor array substrates (TFT array) and a liquid crystal layer (LC layer) interposed therebetween.
In a conventional process for manufacturing a tft array substrate, it is sometimes necessary to form a through hole (through hole) in an insulating layer, where the insulating layer includes a single composite layer or a multi-layer structure stacked independently, and since a taper (taper) trimming film cannot be added to the insulating layer and the density of the upper portion is inconsistent with that of the lower portion, an undercut (undercut) phenomenon may occur at the through hole of the insulating layer during etching, and the taper of the sidewall of the insulating layer is curved or right-angled, and the sidewall of the insulating layer is prone to form a sharp angle, and the thickness of the insulating layer is relatively thick, for example, to achieve the goal of forming a through hole in the insulating layer
Above, because of the unusual situation of trompil appears easily in the limitation of productivity this moment, cause the not good problem of contact, produce the undercut and can lead to the broken string when follow-up other rete fills downthehole, and then influence display panel's display function.
Disclosure of Invention
The invention aims to provide a manufacturing method of an array substrate and the array substrate, which can improve the undercut condition of an insulating layer and prevent the subsequent layers from being disconnected.
The invention provides a manufacturing method of an array substrate, which comprises the following steps:
providing a substrate, wherein the substrate comprises a display area and a non-display area positioned at the periphery of the display area;
forming a first metal layer on the substrate, and patterning the first metal layer in the non-display area to form a first lead;
forming a first insulating layer covering the first metal layer on the substrate;
forming an active layer thin film covering the first insulating layer on the first insulating layer, forming a first contact hole penetrating the active layer thin film and the first insulating layer, the first contact hole being positioned above the first lead, an etching rate of the active layer thin film being greater than an etching rate of the first insulating layer;
and forming a second metal layer on the first insulating layer, and patterning the second metal layer in the non-display area to form a second lead, wherein the second lead is filled in the first contact hole and is electrically connected with the first lead.
Further, after the step of forming the first contact hole penetrating through the active layer thin film and the first insulating layer, patterning the active layer thin film to form a silicon island in the display region, wherein a region of the active layer thin film other than the region corresponding to the silicon island is removed.
Further, before the step of forming the first contact hole penetrating the active layer film and the first insulating layer, patterning the active layer film to form a silicon island in the display region and an etching guide portion in the non-display region, the etching guide portion corresponding to a position of the first contact hole.
Further, the etching guide and the first insulating layer under the etching guide are patterned to form the first contact hole penetrating the etching guide and the first insulating layer.
Further, the second lead covers the etching guide part, and the facing area of the second lead on the substrate is larger than that of the etching guide part on the substrate.
Further, the first insulating layer is formed by a chemical vapor deposition method using a reaction gas including silane, ammonia, and nitrogen.
Further, the flow rate of the silane is controlled to be 1860-2100sccm and the flow rate of the ammonia is controlled to be 15400-17300sccm in the high-speed film forming state of the first insulating layer; and controlling the flow range of the silane to be 600-700sccm and the flow range of the ammonia gas to be 7600-9000sccm in a low-speed film forming state.
Further, the first contact hole is formed by adopting an etching process, when the active layer thin film is etched at a position corresponding to the first contact hole, introduced gas of the etching process comprises sulfur hexafluoride gas, helium gas and chlorine gas, the flow range of the sulfur hexafluoride gas is 310sccm-500sccm, the flow range of the helium gas is 100sccm-300sccm, the flow range of the chlorine gas is 2100sccm-2200sccm, the pressure range adopted by the etching process is 40-50mTorr, and the power range adopted by the etching process is 5000-; when the first insulating layer is etched at the position corresponding to the first contact hole, the introduced gas of the etching process comprises sulfur hexafluoride gas, oxygen and helium, the flow range of the sulfur hexafluoride gas is 510sccm-600sccm, the flow range of the helium is 600 sccm-1000 sccm, and the pressure range adopted by the etching process is 160-170 mTorr.
Further, the method further comprises: before the step of forming the first metal layer on the substrate, forming a third metal layer on the substrate, and patterning the third metal layer in the non-display area to form a third lead;
forming a second insulating layer covering the third lead on the substrate, the third lead and the second insulating layer being formed between the first metal layer and the substrate;
forming the first insulating layer and the active layer thin film on the second insulating layer, and performing patterning processing on the active layer thin film, the first insulating layer and the second insulating layer in the non-display region to form a second contact hole penetrating through the active layer thin film, the first insulating layer and the second insulating layer, wherein the etching rate of the second insulating layer is less than or equal to that of the first insulating layer;
the second lead is filled in the second contact hole and is electrically connected with the third lead.
The invention also provides an array substrate which is manufactured by the manufacturing method of the array substrate.
The invention provides a manufacturing method of an array substrate and the array substrate, wherein a first insulating layer and an active layer film which cover a first metal layer are sequentially formed on a substrate, the etching rate of the active layer film is greater than that of the first insulating layer, the active layer film and the first insulating layer are overlapped up and down, the active layer film is used as a guide layer of the first insulating layer when in hole opening, the active layer film and the first insulating layer are opened at the position corresponding to the first contact hole, a first contact hole which penetrates through the active layer film and the first insulating layer from top to bottom can be formed, due to the different etching rates of the active layer film and the first insulating layer, the active layer film is guided when in hole opening, the problem that the first insulating layer below generates undercut is avoided, meanwhile, a good taper angle can be obtained at the position of the first contact hole, so that the risk of wire breakage of a second metal layer which is filled into the first contact hole later is avoided, the yield of the product is effectively improved, a new photomask is not needed, and the cost is saved.
Drawings
Fig. 1 is a schematic plan view illustrating an array substrate according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a first contact hole of an array substrate according to an embodiment of the invention;
fig. 3a to 3l are schematic views illustrating a manufacturing process of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of a second contact hole of an array substrate according to an embodiment of the invention;
fig. 5a to 5l are schematic views illustrating a manufacturing process of an array substrate according to a second embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Example one
The manufacturing method of the array substrate comprises the following steps: as shown in figures 1 to 3l,
a substrate 10 is provided, the substrate 10 comprises a display area 101 and a non-display area 102 located at the periphery of the display area 101, and the array substrate is manufactured on the substrate 10 in the display area 101 and the non-display area 102 at the same time. Specifically, the substrate 10 is a transparent substrate 10, for example, made of glass.
A first metal layer (not shown) is formed on the substrate 10, and patterning is performed on the first metal layer to form a gate electrode 111 and a scan line (not shown) in the display region 101, and to form a first lead 113 in the non-display region 102, where the first lead 113 is electrically connected to the scan line. Specifically, the material of the first metal layer is made of Mo (molybdenum), Al (aluminum), Mo (molybdenum) which are stacked, and the first metal layer is exposed, developed, and etched, thereby forming the gate electrode 111, the scan line, and the first wiring 113.
A first insulating layer 12 covering the first metal layer is formed on the substrate 10, i.e., the first insulating layer 12 covers the gate electrode 111, the scan line, and the first wiring 113.
An active layer film 13 covering the first insulating layer 12 is formed on the first insulating layer 12, and the active layer film 13 and the first insulating layer 12 are stacked up and down to form a composite structure layer. The active layer thin film 13 is, for example, an amorphous silicon (a-Si) layer, but is not limited thereto.
The active layer thin film 13 and the first insulating layer 12 in the non-display area 102 are patterned to form a first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12, the first contact hole 120 is positioned above the first lead 113, the first lead 113 is exposed through the first contact hole 120, and an etching Rate (ER, Etch Rate) of the active layer thin film 13 is greater than that of the first insulating layer 12. The active layer film 13 is an upper layer film layer of the first insulating layer 12, and the active layer film 13 is a guide layer of the first insulating layer 12 when the active layer film 13 is opened, and the active layer film 13 and the first insulating layer 12 are opened at positions corresponding to the first contact holes 120, so that the first contact holes 120 penetrating through the active layer film 13 and the first insulating layer 12 from top to bottom can be formed.
Specifically, the step of forming the first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12 includes:
as shown in fig. 3a, a first photoresist layer 21 is formed on the active layer film 13.
As shown in fig. 3b, the first photoresist layer 21 is exposed and developed through a mask to form a patterned photoresist layer, the first photoresist layer 21 includes an opaque region, i.e., the remaining photoresist material, and a transparent region, i.e., the region where the photoresist material is removed after development, the transparent region corresponds to the position where the active layer film 13 and the first insulating layer 12 need to be removed, and the active layer film 13 is exposed from the transparent region.
As shown in fig. 3c, the active layer film 13 and the first insulating layer 12 under the light-transmitting region are etched away. Specifically, the etching is performed by dry etching, the thickness of the active layer thin film 13 is smaller than that of the first insulating layer 12, and when the active layer thin film 13 is etched through, the first insulating layer 12 is exposed from the active layer thin film 13, and then the etching of the first insulating layer 12 is started.
It should be noted that the etching has anisotropy, and the etching strength in the longitudinal direction on the substrate 10 is greater than that in the lateral direction. Because the etching rates of the active layer film 13 and the first insulating layer 12 are different, the etching rate of the active layer film 13 is higher, after the active layer film 13 is etched through, the position to be etched of the first contact hole 120 is preliminarily reserved, the side wall of the corresponding hole of the active layer film 13 serves as a guide or transition effect for etching the first insulating layer 12, and then when the first insulating layer 12 is etched, the upper active layer film 13 gradually retreats, and a film layer with a lower etching rate serves as a guide layer, so that the transverse etching strength is compensated.
Since the first insulating layer 12 has a relatively high density, the etching time of the first exposed portion is relatively long, and the upper surface of the first insulating layer 12 is in contact with the active layer thin film 13, so that the etching gas hardly reacts with the upper surface of the first insulating layer 12, and the etching gas is only etched obliquely downward by the guide of the sidewall of the active layer thin film 13 as the active layer thin film 13 gradually recedes and the first insulating layer 12 is further etched, thereby forming the first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12, and the sidewall of the first insulating layer 12 corresponding to the first contact hole 120 has a gentle slope, and exhibits a good taper angle (slope of a cross section after etching), and has no undercut (undercut) phenomenon.
As shown in fig. 3d, an ashing process is used to remove the opaque regions of the first photoresist layer 21.
Further, the etching rate of the active layer thin film 13 can be increased or the etching rate of the first insulating layer 12 can be decreased by changing the film formation and etching parameters. Specifically, the first insulating layer 12 is formed using a silicon nitride (SiNx) material using a Chemical Vapor Deposition (CVD) method using reaction gases including silane (SH4), ammonia (NH3), and nitrogen (N2), and the active layer film 13 using reaction gases including silane, hydrogen, and phosphane (PH 3).
Wherein, the flow rate of the silane is controlled to be 1860-; the flow rate of the silane is controlled to be within the range of 600-. Other related gas flows can be referred to in the prior art and are not described in detail herein. Specifically, in the present embodiment, the flow rate of silane was 1860sccm and the flow rate of ammonia was 17300sccm in the high-speed film formation state; the flow rate of silane in the low-speed film formation state was 600sccm, and the flow rate of ammonia gas was 9000 sccm.
For good etching, the active layer thin film 13 is patterned by etching in the ECCP mode, and when the active layer thin film 13 is etched through, the first insulating layer 12 is etched by using the RIE mode.
When the active layer thin film 13 is etched at the position corresponding to the first contact hole 120, the introduced gas of the etching process comprises sulfur hexafluoride (SF6) gas, helium (He) gas and chlorine (Cl2), the flow rate of the sulfur hexafluoride ranges from 310sccm to 500sccm, the flow rate of the helium ranges from 100sccm to 300sccm, the uniformity of the plasma (plasma) is effectively increased, the flow rate of the chlorine ranges from 2100sccm to 2200sccm, the pressure adopted by the etching process ranges from 40 mTorr to 50mTorr (mTorr), the power adopted by the etching process ranges from 5000 +6000W, and the ECCP adopts double power, so the used power is double power, and the etching rate of the active layer thin film 13 is effectively increased. In this embodiment, the specific parameters of the etching process include a pressure of 50mTorr, a power of 6000W +6000W, a flow rate of sulfur hexafluoride of 500sccm, a flow rate of helium of 300sccm, and a flow rate of chlorine of 2200 sccm.
When the first insulating layer 12 is etched at the position corresponding to the first contact hole 120, the introduced gas in the etching process comprises sulfur hexafluoride gas, oxygen gas and helium gas, the flow rate of the sulfur hexafluoride gas ranges from 510sccm to 600sccm, the flow rate of the helium gas ranges from 600sccm to 1000sccm, the uniformity of the plasma is effectively increased, and the pressure adopted by the etching process ranges from 160-170 mTorr. In the present embodiment, the specific parameters of the etching process are, for example, the pressure is 170mTorr, the flow rate of sulfur hexafluoride is 600sccm, and the flow rate of helium is 1000 sccm.
Preferably, after etching the first contact hole 120 penetrating the active layer film 13 and the first insulating layer 12, the taper angle of both sides of the first insulating layer 12 can be controlled to be about 30 °, even lower than 30 °, and the average value of the critical dimension deviation (CD bias) after the active layer film 13 and the first insulating layer 12 are co-etched is about 0.37 μm, demonstrating that the degree of influence of the first insulating layer 12 on the line width is relatively small in the second etching.
In this embodiment, as shown in fig. 3e to 3g, after the step of forming the first contact hole 120 penetrating the active layer film 13 and the first insulating layer 12, the second photoresist layer 22 is coated on the active layer film, the active layer film 13 is exposed, developed and etched to form the silicon island 131 in the display region 101, and the region of the active layer film 13 corresponding to the region other than the silicon island 131 is removed. As shown in fig. 3h, the second photoresist layer 22 is removed.
Further, as shown in fig. 3i to 3l, a second metal layer 14 is formed on the first insulating layer 12 and the silicon island 131, a third photoresist layer 23 is coated on the second metal layer 14, and the second metal layer 14 is exposed, developed and etched to form a source electrode 141, a drain electrode 142 and a data line (not shown) in the display region 101, and a second wire 143 in the non-display region 102, wherein the second wire 143 is filled in the first contact hole 120 and electrically connected to the first wire 113, so as to achieve conduction, and since a sidewall of the first insulating layer 12 contacting the second wire 143 has a smooth slope, the second wire 143 is not broken. The third photoresist layer 23 is removed.
It should be noted that, as shown in fig. 4, in order to obtain a narrower limit frame, the method further includes forming a third metal layer on the substrate 10 before the step of forming the first metal layer on the substrate 10, that is, disposing the third metal layer below the first metal layer, and patterning the third metal layer in the non-display region 102 to form the third lead 151. The third lead 151 is connected to an external circuit to transmit signals.
A second insulating layer 16 covering the third wiring 151 is formed on the substrate 10, and the third wiring 151 and the second insulating layer 16 are formed between the first metal layer and the substrate 10, and the first metal layer and the third metal layer are separated by the second insulating layer 16.
A first insulating layer 12 and an active layer film 13 are formed on the second insulating layer 16, the active layer film 13, the first insulating layer 12 and the second insulating layer 16 in the non-display region 102 are patterned to form a second contact hole 160 penetrating the active layer film 13, the first insulating layer 12 and the second insulating layer 16, the etching rate of the second insulating layer 16 is less than or equal to that of the first insulating layer 12 to form a first contact hole 120 having a smooth sidewall, and the forming principle of the second contact hole 160 can refer to the first contact hole 120. It is understood that after the first contact hole 120 and the second contact hole 160 are formed, the active layer film 13 above the contact holes is removed, and only the silicon island 131 area in the display region 101 is remained, but not limited thereto.
The second lead 143 is filled in the second contact hole 160 to be electrically connected to the third lead 151.
After the pattern of the second metal layer 14 is completed, subsequent processes, such as formation of a common electrode (not shown) and a pixel electrode (not shown), may be continued with reference to the prior art, and are not described herein again.
Example two
The parts of this embodiment are the same as those of the embodiment, and the description of the same parts is omitted here, except that: as shown in fig. 5a to 5l, before the step of forming the first contact hole 120 penetrating the active layer film 13 and the first insulating layer 12, the active layer film 13 is patterned to form a silicon island 131 in the display region 101 and an etching guide 132 in the non-display region 102, the etching guide 132 corresponding to the first contact hole 120.
Specifically, as shown in fig. 5a to 5c, the fourth photoresist layer 24 is coated on the active layer film 13, exposed, developed and etched, and a portion of the active layer film 13 remains at a position where the first contact hole 120 is formed, as a guide or transition of the subsequent etching, i.e., the etching guide 132. As shown in fig. 5d, the fourth photoresist layer 24 is removed.
As shown in fig. 5e, a fifth photoresist layer 25 is coated on the etching guiding portion 132, and after exposure and development, the photoresist layer is removed at the position corresponding to the first contact hole 120 to expose the etching guiding portion 132; as shown in fig. 5f, the etching guide 132 and the first insulating layer 12 under the etching guide 132 are etched to form the first contact hole 120 penetrating the etching guide 132 and the first insulating layer 12, wherein the first contact hole 120 has smooth sidewalls, i.e., good taper angle, and the specific implementation manner can refer to the description of the first embodiment. As shown in fig. 5g, the fifth photoresist layer 25 is removed.
Further, as shown in fig. 5h, a second metal layer 14 covering the etching guide 132 and the silicon island 131 is formed on the substrate 10.
As shown in fig. 5i, a sixth photoresist layer 26 is coated on the second metal layer 14, and is exposed and developed to remain on the upper portion corresponding to the first contact hole 120 and on the silicon island 131.
After the wet etching process, as shown in fig. 5j, the second wire 143 covering the etching guiding portion 132 is formed in the non-display region 102, and the second wire 143 is filled in the first contact hole 120 to be electrically connected to the first wire 113, so that the source electrode 141 and the drain electrode 142 are formed in the display region 101 while being insulated from each other. It will be appreciated that the silicon island 131 may also continue to be etched, as shown in figure 5k, to etch away the doped amorphous silicon layer on the silicon island 131 to form a channel.
As shown in FIG. 5l, the sixth photoresist layer 26 is removed.
In the present embodiment, the second wires 143 cover the etching guide portion 132, and the edge of the second wires 143 is much larger than the edge of the etching guide portion 132, that is, the facing area of the second wires 143 on the substrate 10 is larger than the facing area of the etching guide portion 132 on the substrate 10, so as to prevent the first wires 113 from being lost due to leakage at the edge of the second wires 143 caused by the trench etching during the acid etching.
After the pattern of the second metal layer 14 is completed, the subsequent processes, such as the formation of the common electrode and the pixel electrode, can be continued with reference to the prior art, and are not described herein again.
The invention also provides an array substrate which is manufactured by the manufacturing method of the array substrate.
The invention provides a manufacturing method of an array substrate and the array substrate, a first insulating layer 12 and an active layer film 13 covering a first metal layer are sequentially formed on a substrate 10, wherein the etching rate of the active layer film 13 is greater than that of the first insulating layer 12, the active layer film 13 and the first insulating layer 12 are overlapped up and down, the active layer film 13 is used as a guide layer of the first insulating layer 12 when the active layer film 13 is opened, the active layer film 13 and the first insulating layer 12 are opened at the position corresponding to a first contact hole 120, the first contact hole 120 penetrating through the active layer film 13 and the first insulating layer 12 from top to bottom can be formed, due to the different etching rates of the active layer film 13 and the first insulating layer 12, the active layer film 13 is guided when the active layer film 13 is opened, the undercut problem of the first insulating layer 12 below is avoided, and simultaneously, a good taper angle can be obtained at the position of the first contact hole 120, even if the third metal layer and the second insulating layer 16 are added under the first metal layer, the second contact hole having a good taper angle and penetrating through the active layer thin film 13, the first insulating layer 12 and the second insulating layer 16 can be formed, so that the risk of wire breakage is avoided by subsequently filling the second metal layer 14 into the first contact hole 120 and/or the second contact hole, the yield of products is effectively improved, the existing photomask is used when the contact hole is formed, the existing photomask is not required to be modified or a new photomask is not required, and the cost is saved.
As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, including not only those elements listed, but also other elements not expressly listed.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a display area and a non-display area positioned at the periphery of the display area;
forming a first metal layer on the substrate, and patterning the first metal layer in the non-display area to form a first lead;
forming a first insulating layer covering the first metal layer on the substrate;
forming an active layer thin film covering the first insulating layer on the first insulating layer, forming a first contact hole penetrating the active layer thin film and the first insulating layer, the first contact hole being positioned above the first lead, an etching rate of the active layer thin film being greater than an etching rate of the first insulating layer;
and forming a second metal layer on the first insulating layer, and patterning the second metal layer in the non-display area to form a second lead, wherein the second lead is filled in the first contact hole and is electrically connected with the first lead.
2. The method of fabricating an array substrate according to claim 1, wherein after the step of forming the first contact hole penetrating the active layer thin film and the first insulating layer, the active layer thin film is patterned to form a silicon island in the display region, and a region of the active layer thin film other than the silicon island is removed.
3. The method of claim 1, wherein the active layer film is patterned to form silicon islands in the display region and etch guides in the non-display region, the etch guides corresponding to positions of the first contact holes, before the step of forming the first contact holes penetrating the active layer film and the first insulating layer.
4. The method of manufacturing an array substrate of claim 3, wherein the etching guide and the first insulating layer under the etching guide are patterned to form the first contact hole penetrating the etching guide and the first insulating layer.
5. The method for manufacturing an array substrate according to claim 4, wherein the second leads cover the etching guide portion, and a facing area of the second leads on the substrate is larger than a facing area of the etching guide portion on the substrate.
6. The method of claim 1, wherein the first insulating layer is formed by chemical vapor deposition using a reaction gas comprising silane, ammonia, and nitrogen.
7. The method as claimed in claim 6, wherein the flow of the silane is controlled to 1860-2100sccm and the flow of the ammonia is controlled to 15400-17300sccm in the high-speed film formation state of the first insulating layer; and controlling the flow range of the silane to be 600-700sccm and the flow range of the ammonia gas to be 7600-9000sccm in a low-speed film forming state.
8. The method for fabricating the array substrate according to claim 1, wherein the first contact hole is formed by an etching process, and when the active layer thin film is etched at a position corresponding to the first contact hole, the gas introduced into the etching process includes sulfur hexafluoride gas, helium gas and chlorine gas, the flow rate of the sulfur hexafluoride gas ranges from 310sccm to 500sccm, the flow rate of the helium gas ranges from 100sccm to 300sccm, the flow rate of the chlorine gas ranges from 2100sccm to 2200sccm, the pressure adopted by the etching process ranges from 40 mTorr to 50mTorr, and the power adopted by the etching process ranges from 5000-; when the first insulating layer is etched at the position corresponding to the first contact hole, the introduced gas of the etching process comprises sulfur hexafluoride gas, oxygen and helium, the flow range of the sulfur hexafluoride gas is 510sccm-600sccm, the flow range of the helium is 600 sccm-1000 sccm, and the pressure range adopted by the etching process is 160-170 mTorr.
9. The method for manufacturing an array substrate according to any one of claims 1 to 8, further comprising:
before the step of forming the first metal layer on the substrate, forming a third metal layer on the substrate, and patterning the third metal layer in the non-display area to form a third lead;
forming a second insulating layer covering the third lead on the substrate, the third lead and the second insulating layer being formed between the first metal layer and the substrate;
forming the first insulating layer and the active layer thin film on the second insulating layer, and performing patterning processing on the active layer thin film, the first insulating layer and the second insulating layer in the non-display region to form a second contact hole penetrating through the active layer thin film, the first insulating layer and the second insulating layer, wherein the etching rate of the second insulating layer is less than or equal to that of the first insulating layer;
the second lead is filled in the second contact hole and is electrically connected with the third lead.
10. An array substrate, wherein the array substrate is manufactured by the manufacturing method of the array substrate according to any one of claims 1 to 9.
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