CN111952247A - Semiconductor device and preparation method thereof - Google Patents

Semiconductor device and preparation method thereof Download PDF

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Publication number
CN111952247A
CN111952247A CN201910413136.8A CN201910413136A CN111952247A CN 111952247 A CN111952247 A CN 111952247A CN 201910413136 A CN201910413136 A CN 201910413136A CN 111952247 A CN111952247 A CN 111952247A
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stress
inducing layer
pmos
nmos
layer
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CN111952247B (en
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刘佑铭
贾超超
孟昭生
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

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Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein the method comprises the following steps: providing a substrate, and forming a PMOS device and an NMOS device; depositing a stress inducing layer over the substrate, the stress inducing layer conformally deposited over the PMOS device and the NMOS device; performing plasma treatment on the stress inducing layer above the PMOS device or the NMOS device according to the type of the stress inducing layer; and annealing to make the PMOS device memorize the compressive stress and the NMOS device memorize the tensile stress. The method of the invention makes the NMOS device and the PMOS device memorize the tensile stress and the compressive stress respectively, enhances the electron mobility of the channel layer of the NMOS device and the hole mobility of the channel layer of the PMOS device, thereby improving the overall performance of the semiconductor device. The compressive stress and the tensile stress can be memorized in the PMOS device and the NMOS device respectively only by forming the stress inducing layer once, the implementation process is simple, the preparation cost of the semiconductor device is not increased, and meanwhile, the high-performance semiconductor device can be obtained.

Description

Semiconductor device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor device and the semiconductor device obtained by the method.
Background
To improve the performance of a Metal Oxide Semiconductor (MOS) transistor, the conductivity of the channel region of the MOS transistor may be increased. For example, the lattice structure of the channel region may be altered to increase the mobility of charge carriers and thereby improve the conductivity of the channel region.
Stress Memorization Techniques (SMT) are one of the techniques that can be used to alter the lattice structure of the channel region. In particular, SMT requires forming an amorphous region near a channel region where a channel of a MOS transistor is to be formed and annealing the amorphous region at a time when a stress inducing layer is located on the amorphous region. Therefore, the amorphous region is recrystallized in a state where stress is applied thereto by the stress-inducing layer. As a result, deformed crystals are formed. The deformed crystal maintains its deformed state even after the stress-inducing layer is removed. Thus, it can be considered that the stress is memorized in the deformed crystal.
SMT in the prior art is mostly applied to memorizing tensile stress in an NMOS device, so that the electron mobility of the NMOS device is improved, and the performance of the NMOS device is improved. However, in a CMOS circuit including both NMOS and PMOS devices, the performance of the PMOS device may be affected and degraded. In the prior art, to improve the performance degradation of PMOS devices, common measures include: removing the stress inducing layer above the PMOS before annealing; or a SiGe epitaxial layer may be formed over the PMOS device to improve the performance of the PMOS device.
However, the method cannot significantly prevent the performance of the PMOS device from being reduced or ensure or improve the performance of the PMOS device, but the method is too complicated and increases the device manufacturing cost.
Disclosure of Invention
In view of the above-mentioned deficiencies and drawbacks of the SMT technology in the prior art, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, in which a stress inducing layer is formed above the device, and plasma processing is performed on a PMOS or NMOS device according to the type of stress generated by the stress inducing layer, so that the PMOS and NMOS devices respectively memorize compressive stress and tensile stress, and the overall formation of the device is improved.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, wherein a PMOS device and an NMOS device are formed on the substrate;
depositing a stress inducing layer over the substrate, the stress inducing layer conformally deposited over the PMOS and NMOS devices;
performing plasma treatment on the stress inducing layer above the PMOS device or the NMOS device according to the type of the stress inducing layer;
and annealing to make the PMOS device memorize the compressive stress and the NMOS device memorize the tensile stress.
Optionally, when the stress inducing layer is a tensile stress pressure inducing layer, performing plasma treatment on the stress inducing layer above the PMOS device, wherein the plasma treatment includes the following steps:
covering a first mask layer above the stress inducing layer above the NMOS device, and exposing the stress inducing layer above the PMOS device;
performing the plasma treatment on the stress inducing layer above the PMOS device;
the gas used for the plasma treatment comprises H2 or a mixed gas of H2 and Ar.
Optionally, when the stress inducing layer is a compressive stress inducing layer, performing plasma treatment on the stress inducing layer above the NMOS device, where the plasma treatment includes the following steps:
covering a second mask layer over the stress inducing layer over the PMOS device, exposing the stress inducing layer over the NMOS device;
performing the plasma treatment on the stress inducing layer above the NMOS device;
the gas used for the plasma treatment comprises N2 or a mixed gas of N2 and Ar.
Optionally, the method further comprises the following steps:
removing the first mask layer above the stress inducing layer above the NMOS device;
removing the stress inducing layer.
Optionally, the method further comprises the following steps:
removing the second mask layer over the stress inducing layer over the PMOS device;
removing the stress inducing layer.
Optionally, before forming the stress inducing layer over the substrate, further comprising:
forming a buffer layer over the substrate, the buffer layer conformally formed over the PMOS and NMOS devices.
Optionally, a shallow trench isolation structure is formed between the PMOS device and the NMOS device to isolate the PMOS device and the NMOS device from each other.
Optionally, the stress inducing layer is formed by PECVD, and the stress inducing layer includes a SiN layer.
Optionally, the buffer layer comprises undoped silicate glass.
Optionally, the first plasma treatment and the second plasma treatment use decoupled pulsed radio frequency to generate plasma, and the treatment temperature is less than 150 ℃.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a substrate; and
a PMOS device and an NMOS device formed on the substrate;
the PMOS device memorizes compressive stress, and the NMOS device memorizes tensile stress.
Optionally, the PMOS and NMOS devices include deformed crystal regions, the deformed crystal regions of the PMOS devices remaining in a deformed state such that the PMOS devices memorize the compressive stress and the NMOS devices memorize the tensile stress.
Optionally, a shallow trench isolation structure is formed between the PMOS device and the NMOS device to isolate the PMOS device and the NMOS device from each other.
As described above, the method for manufacturing a semiconductor device and the semiconductor device of the present invention have the following technical effects:
according to the method, the stress inducing layer is formed above the PMOS device and the NMOS device of the CMOS circuit, and plasma processing is carried out on the stress inducing layer above the PMOS device or the NMOS device aiming at the stress inducing layer. For example, if the stress inducing layer is a tensile stress inducing layer, then H is used for the stress inducing layer above the PMOS device2Performing plasma treatment to convert the stress inducing layer above the PMOS device into a compressive stress inducing layer; if the stress inducing layer is a compressive stress inducing layer, N is adopted for the stress inducing layer above the NMOS device2Plasma treatment is performed to convert the compressive stress inducing layer above the plasma into a tensile stress inducing layer. And then annealing the device to enable the NMOS device and the PMOS device to memorize tensile stress and compressive stress respectively, so that the electron mobility of the channel layer of the NMOS device and the hole mobility of the channel layer of the PMOS device are enhanced, and the overall performance of the semiconductor device is improved.
The method can respectively memorize the compressive stress and the tensile stress in the PMOS device and the NMOS device only by forming the stress inducing layer once, has simple implementation process, does not increase the preparation cost of the semiconductor device, and can obtain the high-performance semiconductor device.
According to the semiconductor device, a tensile stress layer and a compressive stress layer do not need to be deposited above the NMOS device and the PMOS device respectively, the stress inducing layers do not need to be retained in the final semiconductor device, and the tensile stress and the compressive stress are memorized in the NMOS device and the PMOS device respectively by forming deformed crystal regions.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:
FIG. 1 is a flow chart illustrating a method for improving stress memory of a semiconductor device according to the present invention.
Fig. 2 is a schematic structural diagram of a substrate with a PMOS device and an NMOS device formed therein according to the method of the first embodiment.
Fig. 3 is a schematic structural view illustrating the formation of a stress-inducing layer over the structure shown in fig. 2.
Fig. 4 is a schematic diagram illustrating plasma processing of the PMOS device shown in fig. 3.
Fig. 5 is a schematic view of a semiconductor structure formed after annealing the structure shown in fig. 4.
Fig. 6 is a schematic structural diagram of a substrate with a PMOS device and an NMOS device formed therein according to the method of the second embodiment.
Fig. 7 is a schematic structural view illustrating the formation of a stress-inducing layer over the structure shown in fig. 5.
Fig. 8 is a schematic diagram illustrating plasma processing of the PMOS device shown in fig. 6.
Fig. 9 is a schematic view of a semiconductor structure formed after annealing the structure shown in fig. 8.
Reference numerals
100 substrate
101 NMOS device
102 PMOS device
103 shallow trench isolation structure
104 grid structure
104-1 gate material layer
104-2 gate dielectric layer
105 side wall
106 source/drain
107 amorphous region
107' deformed crystal region
108 stress inducing layer
109 buffer layer
110 NMOS device mask layer
200 substrate
201 NMOS device
202 PMOS device
203 shallow trench isolation structure
204 gate structure
204-1 layer of gate material
204-2 gate dielectric layer
205 side wall of grid structure
206 source/drain
207 amorphous region
207' deformed crystal region
208 stress inducing layer
209 buffer layer
210 PMOS device mask layer
I channel region
II source/drain region
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, a technical means for simultaneously improving the performance of a PMOS device and an NMOS device has also appeared, for example, a tensile stress inducing layer is formed over the NMOS device and the PMOS device by CVD, and then the tensile stress inducing layer over the PMOS device is removed by etching under the action of a mask; depositing a compressive stress inducing layer above the PMOS and above the tensile stress inducing layer on the NMOS by CVD, removing the compressive stress inducing layer above the tensile stress inducing layer on the NMOS under the action of a mask, and keeping the compressive stress inducing layer above the PMOS; a dielectric layer is then deposited over the tensile stress inducing layer and the compressive stress inducing layer. Compressive stress and tensile stress are generated in the PMOS device and the NMOS device by the compressive stress inducing layer and the tensile stress inducing layer.
However, the above method still has many disadvantages, such as two times of deposition and two-sided etching, complex and tedious preparation process, and accordingly the preparation cost will be increased.
In order to improve the stress memory of the semiconductor device and simultaneously improve the functions of the PMOS and NMOS devices in the semiconductor device, the invention provides a preparation method of the semiconductor device, as shown in figure 1, the method comprises the following steps:
providing a substrate, wherein a PMOS device and an NMOS device are formed on the substrate;
depositing a stress inducing layer over the substrate, the stress inducing layer conformally deposited over the PMOS and NMOS devices;
performing plasma treatment on the stress inducing layer above the PMOS device or the NMOS device according to the type of the stress inducing layer;
and annealing to make the PMOS device memorize the compressive stress and the NMOS device memorize the tensile stress.
The above method will now be described in detail with reference to specific examples. The following examples are only for illustrating the above-mentioned methods and are useful for the understanding of the technical solutions by those skilled in the art, and are not to be construed as limiting the above-mentioned methods.
Example one
The present embodiment provides a method for improving stress memory of a semiconductor device, as shown in fig. 2, a substrate 100 is provided, and an NMOS device 101 and a PMOS device 102 are formed on the substrate 100. The substrate 100 may be formed of at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In a preferred embodiment of the present invention, the substrate 100 is a silicon substrate.
In a preferred embodiment of this embodiment, a shallow trench isolation structure 103 is formed in the substrate, and the shallow trench isolation structure 103 is formed between the NMOS device 101 and the PMOS device 102 to isolate them.
Referring also to fig. 2, the NMOS device 101 and the PMOS device 102 each include a gate structure 104 formed over the channel region I, the gate structure 104 including a gate material layer 104-1 and a gate dielectric layer 104-2. A sidewall 105 is formed on the periphery of the gate structure 104. The gate dielectric layer 104-2 is formed between the channel region I and the gate material layer 104-1, and between the gate material layer 104-1 and the sidewall spacers 105. In this embodiment, the gate dielectric layer 104-2 may be silicon oxide, silicon nitride, SiON, GexOyNz, GexSiyOz, a high-k material layer, or a stacked structure of each of the above materials. Examples of such high-k materials include, but are not limited to HfO2、ZrO2、A12O3、Ta2O5Hafnium silicate, zirconium silicate and a stack of various of the above materials. The gate material layer 104-1 is a single material layer of polysilicon, poly SiGe, polysilicon doped with impurities, metal (such as Ta, Mo, Ru, or Ni), or metal silicide (such as TaSiN or NiSi), or TaN or TiN, or a stack of various of the above materials. The sidewall spacers 105 may be made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.
As shown in fig. 2, source/drain regions II are disposed on both sides of the channel region I, and include doped source/drain regions 106 and amorphous regions 107 adjacent to the source/drain regions 106. Fig. 2 shows that the source/drain region II includes a doped source/drain 106 and an amorphous region 107, and in another preferred embodiment of the present embodiment, the source/drain region II may be formed integrally with the doped amorphous region.
Over the substrate on which the above structure is formed, a stress inducing layer 108 is deposited, as shown in fig. 3. The stress-inducing layer 108 may be conformally formed on the above structure by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, the stress-inducing layer 108 covering the amorphous region 107. In the present embodiment, high stress SiN is taken as an example, SiH is usually adopted4，NH3And N2The method is realized by a PECVD process, and the reaction temperature (400-The H atom content in the high stress SiN is changed by parameters such as the bulk flow rate and the radio frequency power, so that the H atom content in the high stress SiN is low, and a high tensile stress SiN layer, i.e., the stress inducing layer 108, is obtained.
In a preferred embodiment of this embodiment, before forming the stress-inducing layer 108, a buffer layer 109 may be conformally formed over the structure shown in fig. 2. A stress-inducing layer 108 is conformally formed over the buffer layer 109. The buffer layer 109 is formed of a material having high etching selectivity with respect to the material of the stress-inducing layer 108, so that the buffer layer 109 can function as an etching stop layer when the stress-inducing layer 108 is removed. In addition, the buffer layer 109 may prevent the gate material layer 104-1 and the gate dielectric layer 104-2 from being damaged during the removal of the stress-inducing layer 108. The buffer layer 109 may be an oxide layer, for example, undoped silicate glass.
The tensile stress inducing layer 108 generates tensile stress in the channel regions I of both the NMOS device and the PMOS device, which can improve electron mobility for the NMOS device, but can affect the performance of the PMOS device. Thus, in this embodiment, as shown in fig. 4, a first mask layer 110 is formed over the NMOS device, the first mask layer 110 may be a photoresist layer. The first mask layer 110 shields the NMOS device 101 and exposes the PMOS device 102, and the stress inducing layer 108 above the exposed PMOS device is subjected to plasma treatment under the shielding of the first mask layer 110. Specifically, the stress inducing layer 108 above the PMOS device 102 is subjected to H ion bombardment by using a decoupling pulse radio frequency, and H is selected as a reaction gas2Or H2And Ar. Therefore, the concentration of H atoms in the stress inducing layer 108 above the PMOS device is increased, and the H atoms are converted into a compressive stress inducing layer, which generates a compressive stress on the channel region I of the PMOS device. The stress-inducing layer 108 over the semiconductor device thus forms a tensile stress-inducing layer over the NMOS device and a compressive stress-inducing layer over the PMOS device.
The above plasma treatment is performed at a low temperature, for example, at a temperature of less than 150 ℃. The radio frequency power of the decoupling pulse radio frequency is about 500-3000W, and the duty ratio range is about 5% -50%.
The semiconductor device is then annealed, for example, by one or a combination of spike annealing and laser annealing. During the annealing treatment, the amorphous region 107 is recrystallized in a state where stress is applied thereto by the stress-inducing layer 108. As shown in fig. 5, a deformed crystal region 107 'is formed, and the deformed crystal region 107' maintains its deformed state. Thus, the stress is memorized in the deformed crystal, producing compressive and tensile stresses to the channel region of the PMOS device and the channel region of the NMOS device, respectively. That is, the above compressive stress and tensile stress of the stress-inducing layer 108 are memorized in the PMOS device and the NMOS device, respectively.
After the process, the NMOS device and the PMOS device respectively memorize the tensile stress and the compressive stress, so that the electron mobility of the NMOS device is improved, and meanwhile, the hole mobility of the PMOS device can also be improved, and therefore, the performances of the NMOS device and the PMOS device are improved.
In addition, the method described in this embodiment only needs to deposit a stress inducing layer once, and only needs to form a mask layer once according to the type of the stress inducing layer to perform plasma processing on the PMOS device or the NMOS device, so that the PMOS device or the NMOS device memorizes the tensile stress and the compressive stress respectively.
After the annealing process is completed, as shown in fig. 5, the first mask layer 110 is removed, and the stress-inducing layer 108 and the buffer layer 109 are removed. In a preferred embodiment, the stress-inducing layer 108 is removed using a wet etch, such as H3PO4The stress-inducing layer 108 is removed by a wet process. Buffer layer 109 is removed using a dry or wet etch, for example, a wet etch process using HF solution in the preferred embodiment, to remove buffer layer 109.
Example two
The present embodiment also provides a method for improving the stress memory of a semiconductor device, as shown in fig. 6, a substrate 200 is provided first, and an NMOS device 201 and a PMOS device 202 are formed on the substrate 200. The substrate 200 may be formed of at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In a preferred embodiment of the present invention, the substrate 200 is a silicon substrate.
In a preferred embodiment of this embodiment, a shallow trench isolation structure 203 is formed in the substrate, and the shallow trench isolation structure 203 is formed between the NMOS device 201 and the PMOS device 202 to isolate the two devices.
Referring also to fig. 6, the NMOS device 201 and the PMOS device 202 each include a gate structure 204 formed over the channel region I, the gate structure 204 including a layer of gate material 204-1 and a layer of gate dielectric 204-2. A sidewall 205 is also formed around the gate structure 204. The gate dielectric layer 204-2 is formed between the channel region igold material layer 204-1 and between the gate material layer 204-1 and the sidewall spacers 205. In this embodiment, the gate dielectric layer 204-2 may be silicon oxide, silicon nitride, SiON, GexOyNz, GexSiyOz, a high-k material layer, or a stacked structure of each of the above materials. Examples of such high-k materials include, but are not limited to HfO2、ZrO2、A12O3、Ta2O5Hafnium silicate, zirconium silicate and a stack of various of the above materials. The gate material layer 104-1 is a single material layer of polysilicon, poly SiGe, polysilicon doped with impurities, metal (such as Ta, Mo, Ru, or Ni), or metal silicide (such as TaSiN or NiSi), or TaN or TiN, or a stack of various of the above materials. The sidewall spacers 205 may be made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride.
As shown in fig. 6, source/drain regions II are disposed on both sides of the channel region I, and include doped source/drain regions 206 and amorphous regions 207 adjacent to the source/drain regions 106. Fig. 6 shows that the source/drain region II includes doped source/drain electrodes 106 and an amorphous region 107, and in another preferred embodiment of the present embodiment, the source/drain region II may be formed integrally with the doped amorphous region.
Depositing on the substrate to form the above structureThe product stress inducing layer 208 is shown in fig. 7. The stress-inducing layer 208 may be conformally formed on the above structure by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, the stress-inducing layer 208 covering the amorphous region 207. In the present embodiment, high stress SiN is taken as an example, SiH is usually adopted4，NH3And N2The method is realized by a PECVD process, and the H atom content in the high-stress SiN can be changed by changing parameters such as reaction temperature (400-.
In a preferred embodiment of this embodiment, as shown in fig. 7, before forming the stress-inducing layer 208, a buffer layer 209 may be conformally formed over the structure shown in fig. 6. A stress inducing layer 208 is conformally formed over the buffer layer 209. The buffer layer 209 is formed of a material having high etching selectivity with respect to the material of the stress-inducing layer 208, so that the buffer layer 209 can function as an etching stop layer when the stress-inducing layer 208 is removed. In addition, the buffer layer 209 may prevent the gate material layer 204-1 and the gate dielectric layer 204-2 from being damaged during the removal of the stress-inducing layer 208. The buffer layer 209 may be an oxide layer, for example, undoped silicon glass.
The tensile stress inducing layer 208 described above creates a compressive stress on the channel regions I of both the NMOS and PMOS devices that enhances electron mobility for the PMOS devices, but affects the performance of the NMOS devices. Thus, in this embodiment, as shown in fig. 8, a second mask layer 210 is formed over the PMOS device, and the second mask layer 210 may be a photoresist layer. The second mask layer 210 shields the PMOS device 202 and exposes the NMOS device 201, and under the shielding of the second mask layer 210, a plasma treatment is performed on the stress inducing layer 208 above the exposed NMOS device. Specifically, N ion bombardment is performed on the stress inducing layer 108 above the NMOS device 201 by using decoupling pulse radio frequency, and N is selected as the reaction gas2Or N2And Ar. Thereby increasing the concentration of N atoms in the stress inducing layer 108 above the NMOS device, converting it into a tensile stress inducing layer, for NMThe channel region I of the OS device generates tensile stress. The stress-inducing layer 108 over the semiconductor device thus forms a tensile stress-inducing layer over the NMOS device and a compressive stress-inducing layer over the PMOS device.
The above plasma treatment is performed at a low temperature, for example, at a temperature of less than 150 ℃. The radio frequency power of the decoupling pulse radio frequency is about 500-3000W, and the duty ratio range is about 5% -50%.
The semiconductor device is then annealed, for example, by an annealing process that may be one or a combination of a stark anneal and a laser anneal. During the annealing treatment, the amorphous region 207 is recrystallized in a state where stress is applied thereto by the stress-inducing layer 208. As shown in fig. 9, a deformed crystal region 207 'is formed, and the deformed crystal region 207' maintains its deformed state. Thus, the stress is memorized in the deformed crystal, producing compressive and tensile stresses to the channel region of the PMOS device and the channel region of the NMOS device, respectively. That is, the above compressive stress and tensile stress of the stress-inducing layer 208 are memorized in the PMOS device and the NMOS device, respectively.
After the process, the NMOS device and the PMOS device respectively memorize the tensile stress and the compressive stress, so that the electron mobility of the NMOS device is improved, and meanwhile, the hole mobility of the PMOS device can also be improved, and therefore, the performances of the NMOS device and the PMOS device are improved.
Before the annealing process, the second mask layer 210 is first removed. After the annealing process is completed, the stress-inducing layer 208 and the buffer layer 209 are removed as shown in fig. 9. In a preferred embodiment, the stress-inducing layer 208 is removed using a wet etch, such as H3PO4The stress-inducing layer 208 is removed by a wet process. Buffer layer 209 is removed using a dry or wet etch, for example, a wet etch process using an HF solution in the preferred embodiment, to remove buffer layer 209.
In the above embodiments, a stress-inducing layer is deposited and then plasma treatment is performed on the PMOS device or the NMOS device according to the type of the stress-inducing layer. For example, for a stress inducing layer generating tensile stress, plasma treatment is performed on the PMOS device to convert the stress inducing layer above the PMOS device into a compressive stress inducing layer; and for the stress inducing layer generating the compressive stress, carrying out plasma treatment on the NMOS device to convert the stress inducing layer above the NMOS device into a tensile stress inducing layer. In this way, the NMOS device and the PMOS device memorize tensile stress and compressive stress respectively, and meanwhile, the electron mobility of the channel layer of the NMOS device and the hole mobility of the channel layer of the PMOS device are enhanced. The overall performance of the device is improved. In addition, the process only needs to deposit the stress inducing layer once to form the mask layer once, and is relatively simple, easy to realize and favorable for reducing the production cost of the device.
EXAMPLE III
This embodiment provides a semiconductor device manufactured by the method described in embodiment one or embodiment two. Still referring to fig. 5 and 9, the semiconductor device of the present embodiment includes a substrate (100 or 200), an NMOS device (101 or 201) and a PMOS device (102 or 202) formed on the substrate.
Taking the semiconductor device shown in fig. 5 as an example, the NMOS device 101 and the PMOS device 102 each include a gate structure 104 formed above the channel region I, and the gate structure 104 includes a gate material layer 104-1 and a gate dielectric layer 104-2. A sidewall 105 is formed on the periphery of the gate structure 104. The gate dielectric layer 104-2 is formed between the channel region I and the gate material layer 104-1, and between the gate material layer 104-1 and the sidewall spacers 105. In this embodiment, the gate dielectric layer 104-2 may be silicon oxide, silicon nitride, SiON, GexOyNz, GexSiyOz, a high-k material layer, or a stacked structure of each of the above materials. Examples of such high-k materials include, but are not limited to HfO2、ZrO2、A12O3、Ta2O5Hafnium silicate, zirconium silicate and a stack of various of the above materials. The gate material layer 104-1 is a single material layer of polysilicon, poly SiGe, polysilicon doped with impurities, metal (such as Ta, Mo, Ru, or Ni), or metal silicide (such as TaSiN or NiSi), or TaN or TiN, or a stack of various of the above materials. The sidewall spacers 105 may be silicon nitride, silicon oxide or oxynitrideSilicon, and the like.
As shown in fig. 2, source/drain regions II are disposed on two sides of the channel region I, and include doped source/drain regions 106 and amorphous regions 107, in which the amorphous regions 107 are adjacent to the source/drain regions 106. Fig. 2 shows that the source/drain region II includes a doped source/drain 106 and an amorphous region 107, and in another preferred embodiment of the present embodiment, the source/drain region II may be formed integrally with the doped amorphous region. . In the fabrication process of the semiconductor device, the above amorphous region 107 is recrystallized in the annealing process by the stress-inducing layer, and a deformed crystalline region 107' is formed, as shown in fig. 5. The deformed crystalline region 107' maintains its deformed state. Thus, the stress is memorized in the deformed crystal, producing compressive and tensile stresses to the channel region of the PMOS device and the channel region of the NMOS device, respectively. That is, the PMOS device and the NMOS device memorize compressive stress and tensile stress, respectively.
In the semiconductor device of this embodiment, under the action of the tensile stress inducing layer and the compressive stress inducing layer above the NMOS device and the PMOS device, a deformed crystal region is formed through annealing, the crystal region memorizes the stress of the stress inducing layer, and generates tensile stress and compressive stress to the channel region of the PMOS device and the channel region of the NMOS device, respectively, that is, the compressive stress and the tensile stress are memorized in the channel region of the PMOS device and the channel region of the NMOS device, respectively, so that the electron mobility of the channel layer of the NMOS device is enhanced, and at the same time, the hole mobility of the channel layer of the PMOS device is enhanced. Thereby improving the overall performance of the device. Compared with the prior art, the semiconductor device of the embodiment does not need to deposit the tensile stress layer and the compressive stress layer above the NMOS device and the PMOS device respectively, and does not need to retain the stress inducing layers in the final semiconductor device, but memorizes the tensile stress and the compressive stress in the NMOS device and the PMOS device respectively by forming the deformed crystal regions.
In the semiconductor device and the method for manufacturing the same according to the above embodiments, the stress inducing layer is formed above the PMOS and NMOS devices of the CMOS circuit, and plasma processing is performed on the stress inducing layer above the PMOS device or the NMOS device, according to the type of the stress inducing layer. For example, if the stress inducing layer is tensileThe stress inducing layer above the PMOS device is H2Performing plasma treatment to convert the stress inducing layer above the PMOS device into a compressive stress inducing layer; if the stress inducing layer is a compressive stress inducing layer, N is adopted for the stress inducing layer above the NMOS device2Plasma treatment is performed to convert the compressive stress inducing layer above the plasma into a tensile stress inducing layer. And then annealing the device to enable the NMOS device and the PMOS device to memorize tensile stress and compressive stress respectively, so that the electron mobility of the channel layer of the NMOS device and the hole mobility of the channel layer of the PMOS device are enhanced, and the overall performance of the semiconductor device is improved.
The method can respectively memorize the compressive stress and the tensile stress in the PMOS device and the NMOS device only by forming the stress inducing layer once, has simple implementation process, does not increase the preparation cost of the semiconductor device, and can obtain the high-performance semiconductor device.
According to the semiconductor device, a tensile stress layer and a compressive stress layer do not need to be deposited above the NMOS device and the PMOS device respectively, the stress inducing layers do not need to be retained in the final semiconductor device, and the tensile stress and the compressive stress are memorized in the NMOS device and the PMOS device respectively by forming deformed crystal regions.
The foregoing embodiments are merely illustrative of the principles of this invention and its efficacy, rather than limiting it, and various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention, which is defined in the appended claims.

Claims (13)

1. A method for manufacturing a semiconductor device includes the steps of:
providing a substrate, wherein a PMOS device and an NMOS device are formed on the substrate;
depositing a stress inducing layer over the substrate, the stress inducing layer conformally deposited over the PMOS and NMOS devices;
performing plasma treatment on the stress inducing layer above the PMOS device or the NMOS device according to the type of the stress inducing layer;
and annealing to make the PMOS device memorize the compressive stress and the NMOS device memorize the tensile stress.
2. The method according to claim 1, wherein when the stress-inducing layer is a tensile stress pressure-inducing layer, the stress-inducing layer over the PMOS device is subjected to a plasma treatment, the plasma treatment comprising the steps of:
covering a first mask layer above the stress inducing layer above the NMOS device, and exposing the stress inducing layer above the PMOS device;
performing the plasma treatment on the stress inducing layer above the PMOS device;
the gas used for the plasma treatment comprises H2Or H2And Ar.
3. The method according to claim 1, wherein when the stress-inducing layer is a compressive stress-inducing layer, the stress-inducing layer above the NMOS device is subjected to a plasma treatment, the plasma treatment comprising the steps of:
covering a second mask layer over the stress inducing layer over the PMOS device, exposing the stress inducing layer over the NMOS device;
performing the plasma treatment on the stress inducing layer above the NMOS device;
the gas adopted by the plasma treatment comprises N2Or N2And Ar.
4. The method of claim 2, further comprising the steps of:
removing the first mask layer above the stress inducing layer above the NMOS device;
removing the stress inducing layer.
5. The method of claim 3, further comprising the steps of:
removing the second mask layer over the stress inducing layer over the PMOS device;
removing the stress inducing layer.
6. The method for manufacturing according to claim 1, further comprising, before forming a stress-inducing layer over the substrate:
forming a buffer layer over the substrate, the buffer layer conformally formed over the PMOS and NMOS devices.
7. The method of claim 1, wherein a shallow trench isolation structure is formed between the PMOS device and the NMOS device to isolate the PMOS device and the NMOS device from each other.
8. The production method according to claim 1, wherein the stress-inducing layer is formed by PECVD, and the stress-inducing layer includes a SiN layer.
9. The method of claim 6, wherein the buffer layer comprises undoped silicate glass.
10. The method of claim 1, wherein the first plasma treatment and the second plasma treatment use decoupled pulsed radio frequency generated plasmas, and the treatment temperature is less than 150 ℃.
11. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate; and
a PMOS device and an NMOS device formed on the substrate;
the PMOS device memorizes compressive stress, and the NMOS device memorizes tensile stress.
12. The semiconductor device of claim 11, wherein the PMOS and NMOS devices include deformed crystal regions, the deformed crystal regions of the PMOS devices remaining in a deformed state such that the PMOS devices memorize the compressive stress and the NMOS devices memorize the tensile stress.
13. The semiconductor device of claim 11, wherein a shallow trench isolation structure is formed between the PMOS device and the NMOS device to isolate the PMOS device and the NMOS device from each other.
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