CN111950216A - Method for generating multi-fan-out signal for superconducting RSFQ circuit - Google Patents
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Abstract
There is provided a method of generating a multi-fan-out signal for a superconducting RSFQ circuit, where N is the number of fan-out signals, each of the N fan-out signals corresponding to a branch path made up of SPLs passing from a signal source point to a signal end point, the branch path made up of SPLs making up an SPL tree, the method comprising: calculating the minimum number Y of SPLs according to N; selecting different tree structures according to the minimum number Y of SPLs; determining branch paths of the multi-fan-out signal, which are formed by SPLs, according to the tree structure; wherein the minimum number of SPLs Y is calculated according to the following equation:
and, at most one of the SPLs, SPL2, the remainder being SPL 3.
Description
Technical Field
The invention relates to a method for generating a multi-fan-out signal oriented to a superconducting RSFQ circuit.
Background
The superconducting high-speed single-flux quantum circuit technology and the low-power-consumption derivative thereof are expected to become the next-generation electronic circuit technology with ultra-low power consumption and ultra-high-speed calculation. The RSFQ technology-based circuit differs from the conventional semiconductor circuit in that the former uses pulses to transmit the presentation information, and the latter uses high and low levels. The active device of the RSFQ circuit is a Josephson junction, and the passive device is an inductor. Whereas CMOS circuits use transistors as active devices and capacitors as passive devices. Entirely new superconducting devices have been designed based on RSFQ technology, such as AND, XOR, NOT, Confluency Buffer (CB), DFF, AND split (spl), all of which are made up of josephson junctions. Wherein for SPL of 1-2, herein designated SPL 2; for SPLs 1-3, herein designated SPL 3.
Unlike conventional CMOS logic circuits, each RSFQ logic gate can only drive one logic gate. Therefore, in superconducting RSFQ logic, a special device called a Splitter (SPL) is used to solve the multiple fan-out problem. The SPL2 device is adopted in the logic synthesis of the prior superconducting RSFQ logic circuit to realize multi-fan signals. In fact, modern advanced RSFQ processes have been able to produce SPL3 devices with the same cell area as SPL2, but with more fan-out ports. Thus, using the SPL3 device can reduce the number of devices inserted, thereby reducing the circuit area.
Disclosure of Invention
The invention considers SPL3 device in RSFQ logic synthesis, and provides a method for generating multi-fan-out signals facing a superconducting RSFQ circuit, wherein N is the number of fan-out signals, each of the N fan-out signals corresponds to a branch path formed by SPL and passing from a signal source point to a signal end point, and the branch path formed by the SPL forms an SPL tree, the method comprises the following steps:
calculating the minimum number Y of SPLs according to N;
selecting different tree structures according to the minimum number Y of SPLs;
determining branch paths of the multi-fan-out signal, which are formed by SPLs, according to the tree structure;
wherein the minimum number Y of SPLs is calculated according to the following equation:
and, at most one of the SPLs, SPL2, the remainder being SPL 3.
Preferably, wherein the depth of the SPL tree structure is in the range of:
where H is the depth of the SPL tree.
Preferably, wherein the tree structure is a chain tree or a full 3-way tree.
Preferably, for the chain tree structure, the method further comprises the steps of:
and if the number of the current nodes is equal to the minimum number Y of the SPLs and the number N% 2 of the fan-out signals is equal to 0, newly building an SPL2 node, and otherwise, newly building an SPL3 node.
Preferably, for the chain tree structure, the method further comprises the steps of:
if the upper layer of the current building node close to the leaf node is the leaf node, connecting all output ports of the current building node to the leaf node;
otherwise, if there is a non-leaf node at the previous layer of the current building node close to the leaf node, connecting one output port of the current building node to the input port of the non-leaf node, and connecting the rest output ports of the current building node to the leaf node,
wherein there is only one SPL node per layer in the chain tree structure, and the chain tree structure is built in a layer-by-layer progressive order from leaf nodes to root nodes.
Preferably, for the full 3-way tree structure, the method further comprises the steps of:
and if the number of the current nodes is equal to the minimum number Y of the SPLs and the number N% 2 of the fan-out signals is equal to 0, newly building an SPL2 node, and otherwise, newly building an SPL3 node.
Preferably, for the full 3-way tree structure, the method further comprises the steps of:
if the current building node does not have a previous layer node close to the root node, setting the current building node as the root node;
if an empty output port exists in a node on the upper layer of the current building node close to the root node, selecting one empty output port to be connected to an input port of the current building node;
and after the Y-th node is established, connecting the empty output ports of all the nodes to the leaf nodes.
Preferably, the device delay difference between leaf nodes of the multi-fan-out signal based on the chain tree structure is the largest and is T (Y-1), wherein T is the delay of a single SPL.
Preferably, the device delay phase difference between leaf nodes of the multi-fan-out signal based on the full 3-way tree structure is the smallest, which is T, where T is the delay of a single SPL.
Preferably, when the fan-out number is even, the tree structure comprises one SPL2, and the rest is SPL 3; when the fan-out number is odd, no SPL2 is included in the tree structure.
The present invention also provides a computer readable storage medium having embodied thereon a computer program executable by a processor to perform the steps of the above-described method of generating a multi-fan signal for a superconducting RSFQ circuit.
The present invention also provides an electronic device, including:
one or more processors; and
a memory, wherein the memory is to store one or more executable instructions;
the one or more processors are configured to implement the steps of one of the above-described methods of generating a multi-fan-out signal for a superconducting RSFQ circuit via execution of the one or more executable instructions.
The invention solves the problem that the logic device in the superconducting RSFQ logic circuit cannot be fanned out more. SPL3 is considered to realize multi-fan-out signals in the logic synthesis process of the superconducting RSFQ logic circuit, so that the fan-out limitation of the superconducting RSFQ logic device is met, and the superconducting RSFQ logic circuit generated by logic synthesis can work normally. Meanwhile, the method of using the multi-fan-out signal containing the SPL3 facing the superconducting RSFQ circuit reduces the use amount of the SPL, thereby effectively reducing the area of a circuit logic device.
Drawings
FIG. 1A is a schematic diagram of an equivalent circuit of SPL 2;
FIG. 1B is a schematic diagram of a CMOS circuit and RSFQ circuit fan-out comparison;
FIG. 2 is a flow diagram of a method of chain tree based multi-fan signaling in accordance with an embodiment of the present invention;
FIG. 3 is a tree structure diagram of a method of multi-fan out signal based on a chain tree according to an embodiment of the present invention;
FIG. 4 is a flow diagram of a method of multi-fan out signal based on a full ternary tree according to one embodiment of the present invention;
fig. 5 is a tree structure diagram of a method of multi-fan signal based on a full ternary tree according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings.
FIG. 1A is a schematic diagram of an equivalent circuit of SPL2, and as shown in FIG. 1A, when SFQ pulses are input into SPL2, there will be the same two outputs, OUT1 and OUT 2. Similarly, in the SPL3 device, when an SFQ pulse is input into the SPL3, there will be the same three-way output.
Fig. 1B is a diagram illustrating fan-out comparison between a CMOS circuit in which the output of a CMOS logic gate can be directly connected to a fan-out logic gate, and an RSFQ circuit in which the output of a logic gate can drive only one logic gate, as shown in fig. 1B, and therefore in a superconducting circuit, SPL is required to obtain a multi-fan-out signal. In the method of multi-fan-out signal of the superconducting RSFQ logic circuit, it is generally considered that the smaller the number of SPLs used, the smaller the circuit logic device area. On the basis, the invention provides a method for generating a multi-fan-out signal oriented to a superconducting RSFQ circuit with an optimal area.
The terminology of the present invention is explained IN conjunction with the tree structure of fig. 3, as shown IN fig. 3, a root node is a node having no parent node, i.e., a signal source point, IN fig. 3, an input terminal of the root node is connected to an input signal (IN), a leaf node is a terminal node, i.e., a signal end point, IN fig. 3, an output terminal of the leaf node is connected to an output signal (OUT), and a child node is an intermediate node between the root node and the leaf node. In the example of fig. 3, the root node is SPL2, the child nodes are 4 SPLs 3, and the leaf nodes are DFF devices, it should be understood that the arrangement in fig. 3 is merely an example, and the leaf nodes may be other devices or circuits in practical applications according to the requirements of fan-out.
The invention provides a method for generating multi-fan-out signals facing a superconducting RSFQ circuit, wherein N is the number of fan-out signals (fan-out number), each of the N fan-out signals corresponds to a branch path formed by SPL passing from a signal source point to a signal end point, and the branch path formed by the SPL forms an SPL tree. The method of the present invention for multi-fan-out signals for superconducting RSFQ circuits will be described below in conjunction with the SPL tree structure.
Suppose the fan-out number of an RSFQ logic device is N (the invention aims at the problem of multiple fan-out of a superconducting circuit unit, so N>2), the number of non-leaf nodes of the SPL tree built for the device is Y, i.e., the number of inserted SPLs is Y and the depth of the SPL tree is H. The depth of the tree is defined as the number of nodes on the longest path from the root node to the leaf nodes. The number of SPLs used in the present invention is optimized
Constructing a tree structure according to the number Y of SPLs, wherein the depth of the tree is maximum SPL tree structure based on chain tree in all types of tree structures, H is Y, and the depth of the tree is minimum SPL tree structure based on full 3-way tree
The method of generating the multi-fan-out signal for the superconducting RSFQ circuit based on the chain tree-based SPL tree structure and the full 3-way tree-based SPL tree structure will be described in detail hereinafter.
The method for generating the multi-fan-out signal facing the superconducting RSFQ circuit based on the chain tree comprises the following steps:
the method for generating the multi-fan-out signal facing the superconducting RSFQ circuit based on the chain tree is actually to connect non-leaf nodes in series in a chain table mode. And newly building an SPL3 node each time, and only when the total fan-out number N is an even number, newly building the last SPL as an SPL2 node so as to ensure that the number of the used SPLs is minimum. This approach, however, results in maximizing the depth between leaf nodes, i.e., at most phase difference Y-1, thus making the device delays between leaf nodes very different, i.e., T (Y-1), where T is the delay of a single SPL. The method takes fan-out number as input, takes root nodes of the SPL tree as output, and adopts a bottom-up mode to build the SPL tree layer by layer.
The specific implementation steps of the method are shown in fig. 2:
step 1: calculating the number Y of SPLs according to the fan-out number N, initializing an upper Node to be null, and initializing the number i of the current established Node to be 1 (S100);
step 2: judging whether i is less than or equal to the number Y of the SPLs (S101), if so, executing the step 3, otherwise, executing the step 6;
and step 3: judging whether i is equal to Y and N% 2 is equal to 0(S102), if so, newly building an SPL2 node (S104), otherwise, newly building an SPL3 node (S103), and continuing to the step 4;
and 4, step 4: judging whether the Node is empty (S105), if the Node is empty, indicating that the upper layer of the newly-built Node is a leaf Node, connecting all output ports of the newly-built Node to the leaf Node (S106), if the Node is not empty, indicating that the upper layer Node exists, connecting the rightmost output port of the newly-built Node to an input port of the Node, and connecting the other output ports of the newly-built Node to the leaf Node (S107); continuing with step 5
And 5: assigning the newly-built Node to a Node (S108), adding 1 to the value of i (S109), returning to the step 2, and judging the next step;
step 6: the Node is used as the root Node of the SPL tree (S110);
finally, branch paths of the multi-fan signal composed of SPLs are determined from the tree structure.
Inputting: the number of fan-outs N for a device.
1-count the number of SPLs inserted Y
2:for i from 1to Y do
3:if i＝＝Y and N％ 2＝＝0then
4:node←new an SPL2
5:else
6:node←new an SPL3
7:end if
8:if root not empty then
9:node.right_child＝root
10:end if
11:root＝node
12:end for
And (3) outputting: root (R)
Fig. 3 is a tree structure diagram of a method for generating a multi-fan-out signal for a superconducting RSFQ circuit based on a chain tree according to an embodiment of the present invention, where as shown in fig. 3, the fan-out number N is 10, so the number Y of SPLs calculated is 5, and the tree depth H is 5. In fig. 3, only the root node is the SPL2 device, and the remaining are SPL3 devices, which maximize the depth between leaf nodes, i.e., at most 4 phase differences, thus maximizing the device delay difference between leaf nodes, i.e., 4. In the chain tree structure, each layer has only one SPL node, and the chain tree structure is built in a layer-by-layer progressive sequence from the leaf nodes to the root nodes.
Secondly, a method for generating a multi-fan-out signal facing the superconducting RSFQ circuit based on a complete ternary tree comprises the following steps:
the method for generating the multi-fan-out signal facing the superconducting RSFQ circuit based on the complete treble is to actually create a complete treble, so that the number of SPLs is not increased, the depth difference between leaf nodes is 1 at most, and the device delay between the leaf nodes is reduced to T.
The specific implementation steps of the method are shown in fig. 4:
step 1: calculating the number Y of SPLs according to the fan-out number N, initializing a queue Q to be empty, and initializing the number i of the current building nodes to be 1 (S200);
step 2: judging whether i is less than or equal to the number Y of SPLs (S201), if so, executing the step 3, otherwise, executing the step 7;
and step 3: judging whether i is equal to Y and N% 2 is equal to 0(S202), if so, newly building an SPL2 node (S203), otherwise, newly building an SPL3 node (S204), and continuing to the step S4;
and 4, step 4: judging whether the queue Q is empty (S205), if Q is empty, then the new node is a first node, then the new node is set as a root node (S206), if Q is not empty, then the node already exists in the queue, then the empty output port of the queue head node in Q is connected to the input port of the new node (S207), and continuing to the step 5;
and 5: enqueuing the new node into Q (S208), and continuing to step 6;
step 6: if all output ports of the head node in the Q are not empty, the head node is dequeued from the Q (S209), the next node of the head node becomes a new head node, the value of i is added with 1(S210), and the step 2 is returned to for the next judgment;
and 7: connecting the remaining empty output ports of all nodes in Q to the leaf node (S211);
finally, branch paths of the multi-fan signal composed of SPLs are determined from the tree structure.
Inputting: the number of fan-outs N for a device.
1, calculating the number Y of inserted SPLs and initializing the queue Q to be empty
2:for i from 1to Y do
3:if i＝＝Y and N％ 2＝＝0then
4:node←new an SPL2
5:else
6:node←new an SPL3
7:end if
8:if Q not empty then
9:P＝Q.front()
10:an empty output port of P is connected to node
11:else
12:root＝node
13:end if
14:Q.in_queue(node)
15:if P！＝
&&all output ports of P are not empty do
16:Q.out_queue()
17:end if
18:end for
And (3) outputting: root (R)
Fig. 5 is a tree structure diagram of a method for generating a multi-fan-out signal for a superconducting RSFQ circuit based on a full-ternary tree according to an embodiment of the present invention, where as shown in fig. 5, the fan-out number N is 10, so the number Y of SPLs calculated is 5, and the tree depth H is 3. In FIG. 5, only the child nodes closest to the leaf nodes are SPL2 devices, and the remainder are SPL3 devices, which achieve a maximum difference in depth between leaf nodes of 1, thereby reducing the device delay between leaf nodes to T.
Although the above is to the baseThe detailed description is made on the chain tree and the method for generating the multi-fan-out signal for the superconducting RSFQ circuit based on the full ternary tree, but the present invention is not limited thereto. According to one embodiment of the invention, whenever the SPL number is satisfied
Can be used in the area-optimized method for multiple fan-out signals of superconducting RSFQ circuits of the present invention. According to another embodiment of the invention, whenever the SPL number is satisfied
And the depth H of the tree satisfies
Tree structures within the scope of the invention can be used in the area-optimized superconducting RSFQ circuit-oriented multi-fan-out approach of the present invention. Meanwhile, the number of SPLs used in the invention is minimum, so that in the process of constructing the tree, at most one SPL2 exists, and the balance is SPL 3.
The invention solves the problem that the superconducting RSFQ logic unit cannot be fanned out more by using the SPL in the logic synthesis stage of the superconducting RSFQ logic circuit, and solves the problem that the logic device in the superconducting RSFQ logic circuit cannot be fanned out more. The SPL insertion method comprising the SPL3 reduces the use number of the SPLs, thereby effectively reducing the area of a circuit logic device.
The present invention also provides a computer readable storage medium having embodied thereon a computer program executable by a processor to perform the steps of a method of generating a multi-fan-out signal for a superconducting RSFQ circuit as described above.
The present invention also provides an electronic device comprising: one or more processors; and a memory, wherein the memory is to store one or more executable instructions; the one or more processors are configured to implement the steps of a method of generating a multi-fan-out signal for a superconducting RSFQ circuit described above via execution of one or more executable instructions.
Finally, it should be noted that the above embodiments are only used for explaining the technical solution of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A method of generating a multi-fan-out signal for a superconducting RSFQ circuit, where N is a number of fan-out signals, each of the N fan-out signals corresponding to a branch path of SPL passing from a signal source point to a signal end point, the branch path of SPL constituting a SPL tree, the method comprising:
calculating the minimum number Y of SPLs according to N;
selecting different tree structures according to the minimum number Y of SPLs;
determining branch paths of the multi-fan-out signal, which are formed by SPLs, according to the tree structure;
wherein the minimum number Y of SPLs is calculated according to the following equation:
and, at most one of the SPLs, SPL2, the remainder being SPL 3.
2. The method of generating a multi-fan-out signal for a superconducting RSFQ circuit of claim 1, wherein the depth of the SPL tree structure is in the range of:
where H is the depth of the SPL tree.
3. The method of generating a superconducting RSFQ circuit-oriented multi-fan-out signal of claim 1, wherein said tree structure is a chain tree or a full 3-way tree.
4. A method of generating a superconducting RSFQ circuit-oriented multi-fan-out signal in accordance with claim 3, further comprising, for said chain tree structure, the steps of:
and if the number of the current nodes is equal to the minimum number Y of the SPLs and the number N% 2 of the fan-out signals is equal to 0, newly building an SPL2 node, and otherwise, newly building an SPL3 node.
5. A method of generating a superconducting RSFQ circuit-oriented multi-fan-out signal in accordance with claim 3, further comprising, for said chain tree structure, the steps of:
if the upper layer of the current building node close to the leaf node is the leaf node, connecting all output ports of the current building node to the leaf node;
otherwise, if there is a non-leaf node at the previous layer of the current building node close to the leaf node, connecting one output port of the current building node to the input port of the non-leaf node, and connecting the rest output ports of the current building node to the leaf node,
wherein there is only one SPL node per layer in the chain tree structure, and the chain tree structure is built in a layer-by-layer progressive order from leaf nodes to root nodes.
6. A method of generating a superconducting RSFQ circuit-oriented multi-fan-out signal according to claim 3, further comprising, for the full 3-way tree structure, the steps of:
and if the number of the current nodes is equal to the minimum number Y of the SPLs and the number N% 2 of the fan-out signals is equal to 0, newly building an SPL2 node, and otherwise, newly building an SPL3 node.
7. A method of generating a superconducting RSFQ circuit-oriented multi-fan-out signal according to claim 3, further comprising, for the full 3-way tree structure, the steps of:
if the current building node does not have a previous layer node close to the root node, setting the current building node as the root node;
if an empty output port exists in a node on the upper layer of the current building node close to the root node, selecting one empty output port to be connected to an input port of the current building node;
and after the Y-th node is established, connecting the empty output ports of all the nodes to the leaf nodes.
8. The method of claim 3, wherein device delays between leaf nodes of the chain-tree based multi-fan signal differ the most by T (Y-1), where T is the delay of a single SPL.
9. The method of claim 3, wherein device delays between leaf nodes of the multi-fan signal based on the full 3-way tree structure differ a minimum by a value of T, where T is the delay of a single SPL.
10. The method of claim 1, wherein when the number of fan-outs is even, the tree structure comprises an SPL2, and the remainder is SPL 3; when the fan-out number is odd, no SPL2 is included in the tree structure.
11. A computer-readable storage medium, having embodied thereon a computer program, the computer program being executable by a processor for performing the steps of the method of one of claims 1 to 10.
12. An electronic device, comprising:
one or more processors; and
a memory, wherein the memory is to store one or more executable instructions;
the one or more processors are configured to implement the steps of the method of one of claims 1-10 via execution of the one or more executable instructions.
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