CN111949294A

CN111949294A - Firmware refreshing method, device, server and computer readable storage medium

Info

Publication number: CN111949294A
Application number: CN202010785437.6A
Authority: CN
Inventors: 别岩波; 张则民; 黄晨; 谢凌帅
Original assignee: Dawning Information Industry Beijing Co Ltd
Current assignee: Dawning Information Industry Beijing Co Ltd
Priority date: 2020-08-06
Filing date: 2020-08-06
Publication date: 2020-11-17

Abstract

The application relates to a firmware refreshing method and device, a server and a computer readable storage medium, comprising the following steps: when BIOS firmware refreshing is carried out on at least one BIOS chip in the dual-BIOS system, the identification of the BIOS chip to be refreshed is obtained. And accessing the BIOS chip to be refreshed corresponding to the identifier into the system through the CPLD logic circuit. And acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file. The BIOS chip to be refreshed is accessed to the system by adopting a CPLD logic circuit instead of a mode of manually adjusting the jump cap in the traditional method, so that the refreshing process is greatly simplified, and the convenience of firmware refreshing is improved. And because the switching of the BIOS chip access system is not needed to be manually realized, the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

Description

Firmware refreshing method, device, server and computer readable storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a firmware refreshing method and apparatus, a server, and a computer-readable storage medium.

Background

BIOS (Basic Input Output System) firmware is a set of System programs solidified into a memory chip on a motherboard of a computing device, plays an indispensable role in normal initialization, startup, and operating System booting of a computer System, and is a key link for implementing key functions of the computer System, such as security and reliability. With the continuous development of computer technology, dual BIOS systems are increasingly applied to various terminal devices and servers, wherein the dual BIOS systems are systems having two BIOS chips.

Because the dual-BIOS system has two BIOS chips, the conventional method adopts the jump cap as a switch for accessing the two BIOS chips into the system when the BIOS firmware of the dual-BIOS system is refreshed. Therefore, when BIOS firmware refreshing needs to be carried out on a certain BIOS chip, the BIOS chip is accessed to the system by manually adjusting the jump cap, and then the BIOS firmware refreshing is carried out on the BIOS chip. After the BIOS chip is refreshed, another BIOS chip is accessed to the system by manually adjusting the jump cap, so that the BIOS chip is refreshed.

However, when the dual BIOS system is refreshed, the jump cap needs to be manually adjusted back and forth, so that the BIOS firmware refreshing process is inconvenient to operate and too complicated, and the error rate is high.

Disclosure of Invention

The embodiment of the application provides a firmware refreshing method, a firmware refreshing device, a server and a computer readable storage medium, which can simplify the firmware refreshing process, improve the convenience of firmware refreshing and further improve the accuracy of firmware refreshing.

A firmware refresh method, comprising:

when BIOS firmware refreshing is carried out on at least one BIOS chip in the dual-BIOS system, the identification of the BIOS chip to be refreshed is obtained;

accessing the BIOS chip to be refreshed corresponding to the identification into a system through a complex programmable logic device CPLD logic circuit;

and acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file.

In the embodiment of the application, when a server or a terminal refreshes BIOS firmware of at least one BIOS chip in a dual-BIOS system, an identifier of the BIOS chip to be refreshed is obtained. And accessing the BIOS chip to be refreshed corresponding to the identification into the system through a complex programmable logic device CPLD logic circuit. And acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file. Through the CPLD logic circuit, the BIOS chip to be refreshed is automatically accessed into the system, so that the firmware of the BIOS chip to be refreshed can be refreshed directly. The BIOS chip to be refreshed is accessed to the system by adopting a CPLD logic circuit instead of a mode of manually adjusting the jump cap in the traditional method, so that the refreshing process is greatly simplified, and the convenience of firmware refreshing is improved. And because the switching of the BIOS chip access system is not needed to be manually realized, the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

In one embodiment, the accessing the BIOS chip to be refreshed corresponding to the identifier to the system through a complex programmable logic device CPLD logic circuit includes:

reading the GPIO signal through a CPLD logic circuit;

and accessing the BIOS chip to be refreshed into a system according to the GPIO signal.

In the embodiment of the application, the server or the terminal reads the GPIO signal through the CPLD logic circuit and accesses the BIOS chip to be refreshed into the system according to the GPIO signal. The read GPIO signal is used for controlling the CPLD logic circuit to automatically access the BIOS chip to be refreshed into the system. Because the switching of the BIOS chip access system is not needed to be manually realized, the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

In one embodiment, the GPIO signals include a first GPIO signal and a second GPIO signal, the state value of the first GPIO signal is used to distinguish a BIOS chip currently accessed to the system, the state value of the first GPIO signal is updated according to whether switching of the chip in the dual BIOS system is successful, and the state value of the second GPIO signal is updated by the dual BIOS system based on whether chip switching is required.

In the embodiment of the application, the GPIO signals include a first GPIO signal and a second GPIO signal, the state value of the first GPIO signal is used to distinguish the BIOS chip currently accessed to the system, the state value of the first GPIO signal is updated according to whether the switching of the chip in the dual BIOS system is successful, and the state value of the second GPIO signal is updated by the dual BIOS system based on whether the chip switching is required. If the BIOS chip to be refreshed does not access the system, reading the second GPIO signal through the CPLD logic circuit to switch the chip, and then reading the first GPIO signal to judge whether the switching is successful. Therefore, the CPLD logic circuit reads the two GPIO signals, and the BIOS chip to be refreshed is successfully accessed into the system.

In one embodiment, the reading, by the CPLD logic circuit, a GPIO signal and accessing the BIOS chip to be refreshed to the system according to the GPIO signal includes:

reading the current state value of the first GPIO signal through a CPLD logic circuit;

judging whether the BIOS chip of the current access system is the BIOS chip to be refreshed or not according to the current state value of the first GPIO signal;

if not, the CPLD logic circuit is controlled to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal.

In the embodiment of the application, the server or the terminal reads the current state value of the first GPIO signal through the CPLD logic circuit, and judges whether the BIOS chip of the current access system is the BIOS chip to be refreshed or not according to the current state value of the first GPIO signal. If so, the switching is not needed; if not, the CPLD logic circuit is controlled to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal. Therefore, by combining the current state value of the first GPIO signal and the current state value of the second GPIO signal, which chip is currently accessed to the system can be accurately identified, and an instruction whether to switch the chips is accurately sent out. Because the current state value of the GPIO signal changes only when a specific condition is met, the BIOS chip to be refreshed is accurately ensured to be accessed into the system, so that the firmware refreshing of the BIOS chip to be refreshed can be accurately carried out subsequently.

In one embodiment, after the controlling the CPLD logic circuit to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal, the method includes:

judging whether the current state value of the first GPIO signal and the last state value of the first GPIO signal change or not;

if yes, determining that the BIOS chip of the current access system is the BIOS chip to be refreshed, and reporting the successful switching result to the dual-BIOS system.

In the embodiment of the application, after the CPLD logic circuit is controlled to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal, a step of judging whether the switching is successful is added. The chip in the current access system is further ensured to be the BIOS chip to be refreshed, so that the situation that the BIOS chip to be refreshed fails to be refreshed is avoided.

In one embodiment, the dual BIOS system includes a first BIOS chip and a second BIOS chip, and the first BIOS chip and the second BIOS chip are the same two chips;

before the obtaining the identifier of the BIOS chip to be refreshed when the BIOS firmware refresh is performed on at least one BIOS chip in the dual BIOS system, the method further includes:

and if the first BIOS chip of the current access system is damaged, the CPLD logic circuit is controlled to switch the chips of the current access system by updating the current state value of the second GPIO signal.

In the embodiment of the application, if the first BIOS chip currently accessed to the system is damaged, the system updates the current state value of the second GPIO signal to a high level. And reading the current state value of the updated second GPIO signal through the CPLD logic circuit, and switching the chip currently accessed into the system. Therefore, the chip with the fault is switched to another normal chip to ensure the normal starting work of the server or the terminal.

In one embodiment, if the identifier is an identifier of a first BIOS chip, the accessing, by a CPLD logic circuit, the BIOS chip to be refreshed corresponding to the identifier to a system includes:

reading the current state value of the first GPIO signal through a CPLD logic circuit, and determining whether a BIOS chip of a current access system is the first BIOS chip;

if not, the CPLD logic circuit is controlled to switch the second BIOS chip currently accessed into the system into the first BIOS chip by updating the current state value of the second GPIO signal.

In the embodiment of the application, if the first BIOS chip of the current access system is damaged, the current state value of the updated second GPIO signal is read by the CPLD logic circuit, and the chip in the current access system is switched. Therefore, the chip with the fault is switched to another normal chip to ensure the normal starting work of the server or the terminal. And then, the CPLD logic circuit is controlled to switch a second BIOS chip currently accessed into the system into the first BIOS chip by updating the current state value of the second GPIO signal, so that firmware refreshing of the BIOS chip with a fault is ensured subsequently.

In one embodiment, if the identifiers are identifiers of two BIOS chips, the accessing the BIOS chip to be refreshed corresponding to the identifiers to the system through the CPLD logic circuit includes:

acquiring a BIOS chip of a current access system according to the current state value of the first GPIO signal, and taking the BIOS chip of the current access system as a target BIOS chip to be refreshed;

the firmware refreshing of the BIOS chip to be refreshed through the BIOS firmware refreshing file comprises the following steps:

and refreshing the firmware of the target BIOS chip to be refreshed through the BIOS firmware refreshing file.

In the embodiment of the application, when BIOS firmware refreshing needs to be performed on two BIOS chips in a dual-BIOS system, firmware refreshing is performed on a chip currently accessed into the system. Therefore, chip switching is not required to be performed frequently, and the firmware refreshing efficiency is improved.

In one embodiment, after the firmware refresh is performed on the target BIOS chip to be refreshed by using the BIOS firmware refresh file, the method includes:

the CPLD logic circuit is controlled to switch the chips in the current access system by updating the current state value of the second GPIO signal, and the BIOS chip in the switched access system is used as a new target BIOS chip to be refreshed;

and updating the firmware of the new target BIOS chip to be updated through the BIOS firmware updating file.

In the embodiment of the application, when BIOS firmware refreshing needs to be carried out on two BIOS chips in a dual-BIOS system, firmware refreshing is carried out in a mode of sequentially carrying out firmware refreshing. And firstly, firmware refreshing is carried out on the chip in the current access system, then another BIOS chip is switched to the access system, and firmware refreshing is carried out on the BIOS chip. Therefore, the refreshing sequence is clear, and chip switching is not required frequently, so that the firmware refreshing efficiency is improved. And through the CPLD logic circuit, the BIOS chip to be refreshed is automatically accessed into the system, and because the BIOS chip access system does not need to be manually switched, the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

A firmware refresh apparatus, comprising:

the acquisition module is used for acquiring the identification of the BIOS chip to be refreshed when BIOS firmware refreshing is carried out on at least one BIOS chip in the dual-BIOS system;

the access module is used for accessing the BIOS chip to be refreshed corresponding to the identifier into a system through a Complex Programmable Logic Device (CPLD) logic circuit;

and the firmware refreshing module is used for acquiring a BIOS firmware refreshing file according to the identification and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file.

A server comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to carry out the steps of the above method.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method as above.

According to the firmware refreshing method, the firmware refreshing device, the server and the computer readable storage medium, when BIOS firmware refreshing is carried out on at least one BIOS chip in a dual-BIOS system, the identification of the BIOS chip to be refreshed is obtained. And accessing the BIOS chip to be refreshed corresponding to the identification into the system through a complex programmable logic device CPLD logic circuit. And acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file. The BIOS chip to be refreshed can be automatically accessed into the system by switching the chips through the CPLD logic circuit, so that the firmware of the BIOS chip to be refreshed can be directly refreshed. The BIOS chip to be refreshed is accessed to the system by adopting a CPLD logic circuit instead of a mode of manually adjusting the jump cap in the traditional method, so that the refreshing process is greatly simplified, and the convenience of firmware refreshing is improved. And because the switching of the BIOS chip access system is not needed to be manually realized, the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram of an application environment of a firmware refresh method in one embodiment;

FIG. 2 is a flow diagram of a firmware refresh method in one embodiment;

FIG. 3 is a flowchart of a method for accessing the BIOS chip to be refreshed to the system according to the GPIO signals by reading the GPIO signals through the CPLD logic circuit in FIG. 2;

FIG. 4 is a flowchart of a firmware refresh method in another embodiment;

FIG. 5 is a flowchart of a firmware refresh method in yet another embodiment;

FIG. 6 is a flow chart of a firmware refresh method in yet another embodiment;

FIG. 7 is a flow diagram of a firmware refresh method in one embodiment;

FIG. 8 is a block diagram showing the structure of a firmware refresh apparatus according to an embodiment;

FIG. 9 is a block diagram showing the structure of a firmware refreshing apparatus according to another embodiment;

fig. 10 is a schematic diagram of an internal configuration of a server in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

As shown in fig. 1, fig. 1 is a diagram illustrating an application scenario of firmware refresh in an embodiment. As shown in fig. 1, the application environment includes an external device 120 and a server 140. When the server 140 performs BIOS firmware refresh on at least one BIOS chip in the dual BIOS system, acquiring an identifier of the BIOS chip to be refreshed; accessing the BIOS chip to be refreshed corresponding to the identifier into the system through a complex programmable logic device CPLD logic circuit; and acquiring the BIOS firmware refreshing file from the external device 120 according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file. Of course, the server may be replaced by a terminal, and the present application is not limited thereto.

Fig. 2 is a flowchart of a firmware refresh method in an embodiment, and as shown in fig. 2, a firmware refresh method is provided, which is applied to a server or a terminal and includes steps 220 to 260.

Step 220, when the BIOS firmware of at least one BIOS chip in the dual BIOS system is refreshed, the identification of the BIOS chip to be refreshed is obtained.

Because the dual BIOS system has two BIOS chips including a first BIOS chip and a second BIOS chip. The first BIOS chip is a main BIOS chip, the second BIOS chip is a slave BIOS chip, generally, the system runs on the main BIOS chip, and the slave BIOS chip is mainly used for temporarily switching to the slave BIOS chip to support normal startup of a server or a terminal when the main BIOS chip breaks down. The identifier may be 1 for a first BIOS chip configuration in a dual BIOS system and 0 for a second BIOS chip configuration in the dual BIOS system. For example, if the obtained identifier of the BIOS chip to be refreshed is 1, it indicates that the firmware of the first BIOS chip is refreshed; if the obtained identification of the BIOS chip to be refreshed is 0, the firmware refreshing of the second BIOS chip is performed.

When a server or a terminal refreshes BIOS firmware of at least one BIOS chip in the dual-BIOS system, the identification of the BIOS chip to be refreshed is obtained. Specifically, the BIOS firmware refresh may be performed on at least one BIOS chip in the dual BIOS system, or may be performed on both BIOS chips in the dual BIOS system. When the BIOS firmware of one BIOS chip in the dual-BIOS system needs to be refreshed, the specific BIOS chip needs to be determined, and then the BIOS chip is used as the BIOS chip to be refreshed to obtain the identification of the BIOS chip to be refreshed.

When a server or a terminal needs to refresh BIOS firmware of two BIOS chips in a dual BIOS system, the two BIOS chips are both needed to be used as the BIOS chips to be refreshed, and the identification of the BIOS chips to be refreshed is obtained.

And step 240, accessing the BIOS chip to be refreshed corresponding to the identifier to the system through the complex programmable logic device CPLD logic circuit.

Among them, a Complex Programmable Logic Device (CPLD) Logic circuit is a short name of a Complex PLD, which is a Complex Logic element compared with the PLD. The CPLD is a digital integrated circuit in which a user constructs logic functions according to his or her own needs. The basic design method is to generate corresponding target files by means of an integrated development software platform and methods such as schematic diagrams, hardware description languages and the like, and to transmit codes to a target chip through system programming to realize a designed digital system.

Because only one BIOS chip can be accessed at the same time in the dual BIOS system, when a server or a terminal needs to perform firmware refresh on a certain BIOS chip to be refreshed, the BIOS chip to be refreshed needs to be accessed to the system. Specifically, the system accesses the BIOS chip to be refreshed corresponding to the identifier to the system through the CPLD logic circuit, where the system may refer to an operating system or an operating system on a server or a terminal.

And step 260, acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file.

After the system accesses the BIOS chip to be refreshed corresponding to the identifier to the system through the CPLD logic circuit, the BIOS firmware refreshing file corresponding to the BIOS chip of the identifier is obtained from the external equipment according to the identifier. The external device stores a BIOS firmware refreshing file in advance. Typically, two BIOS chips in a dual BIOS system use the same BIOS firmware to refresh files. Of course, the two BIOS chips in the dual BIOS system may also use different BIOS firmware to refresh the file, which is not limited in this application.

After the server or the terminal acquires the BIOS firmware refreshing file corresponding to the identified BIOS chip from the external device according to the identification, firmware refreshing is carried out on the BIOS chip to be refreshed through the BIOS firmware refreshing file. The BIOS chip can be repaired or upgraded by firmware refreshing.

In one embodiment, the step 240 of accessing the identification corresponding to the BIOS chip to be refreshed to the system through the complex programmable logic device CPLD logic circuit includes:

reading the GPIO signal through a CPLD logic circuit;

and accessing the BIOS chip to be refreshed into the system according to the GPIO signal.

The GPIO (General Purpose input/output Ports) means General Purpose input/output Ports, which are commonly referred to as pins. The GPIO signal may be understood as an input state (high level or low level) of the GPIO port or an output state (high level or low level) of the GPIO port. The system can control the hardware operation by data interaction between the GPIO signal and the hardware.

Specifically, the server or the terminal reads the GPIO signal through the CPLD logic circuit and accesses the BIOS chip to be refreshed into the system according to the GPIO signal. The CPLD logic circuit reads the GPIO signal, so that the system can determine the identification of the BIOS chip of the current access system, and further determine which BIOS chip of the current access system is.

And the server or the terminal reads the GPIO signal through the CPLD logic circuit, so that the BIOS chip to be refreshed can be accessed into the system according to the GPIO signal. Specifically, if the current access system is the BIOS chip to be refreshed, the chip of the access system does not need to be switched. And if the current access system is not the BIOS chip to be refreshed, switching the chip of the access system.

In one embodiment, the GPIO signals include a first GPIO signal and a second GPIO signal, the state value of the first GPIO signal is used to distinguish a BIOS chip currently accessed in the system, the state value of the first GPIO signal is updated according to whether switching of the chip in the dual BIOS system is successful, and the state value of the second GPIO signal is updated by the dual BIOS system based on whether chip switching is required.

Specifically, the state value of the first GPIO signal is used to distinguish a BIOS chip currently accessed to the system. Assume that the first BIOS chip is currently accessed in the dual BIOS system, and the state value of the first GPIO signal (GPIO-1) is high. Because the state value of the first GPIO signal is updated according to whether the switching of the chip in the dual BIOS system is successful or not, if the chip in the dual BIOS system is switched and the switching is successful at this time, the state value of the first GPIO signal is changed to a low level at this time.

The state value of the second GPIO signal (GPIO-0) is set by the dual BIOS system. Specifically, when the system does not need to switch chips, the state value of the second GPIO signal is set to be a low level by default; correspondingly, when the system needs to switch the chip, the state value of the second GPIO signal is updated to a high level, and the state value is restored to a default setting (low level) after switching.

In one embodiment, as shown in fig. 3, reading the GPIO signal through the CPLD logic circuit, and accessing the BIOS chip to be refreshed to the system according to the GPIO signal includes:

and step 320, reading the current state value of the first GPIO signal through the CPLD logic circuit.

Similarly, assume that the first BIOS chip is currently accessed in the dual BIOS system, and the state value of the first GPIO signal (GPIO-1) is at a high level at this time. Because the state value of the first GPIO signal is updated according to whether the switching of the chip in the dual BIOS system is successful or not, if the chip in the dual BIOS system is switched and the switching is successful at this time, the state value of the first GPIO signal is changed to a low level at this time. Then the state value of the first GPIO signal (GPIO-1) remains high, i.e., when the chip in the access system is the first BIOS chip. And when the chip in the access system is the second BIOS chip, the state value of the first GPIO signal (GPIO-1) is kept at low level.

And the server or the terminal reads the current state value of the first GPIO signal through the CPLD logic circuit and judges whether the current state value of the first GPIO signal is high level or low level.

And step 340, judging whether the BIOS chip of the current access system is the BIOS chip to be refreshed or not according to the current state value of the first GPIO signal.

If the current state value of the first GPIO signal is high level, the chip in the access system is the first BIOS chip, and the BIOS chip of the current access system is judged not to be the BIOS chip to be refreshed, and at the moment, switching is needed. If the current state value of the first GPIO signal is low level, the chip in the access system is a second BIOS chip, the BIOS chip of the current access system is judged to be the BIOS chip to be refreshed (the second BIOS chip), and at this moment, switching is not needed.

And step 360, if not, controlling the CPLD logic circuit to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal.

When the current state value of the first GPIO signal is at a high level, the chip in the access system is the first BIOS chip, and it is determined that the BIOS chip of the current access system is not the BIOS chip to be refreshed (the second BIOS chip), the chip in the current access system needs to be switched. When the system needs to switch the chip, the state value of the second GPIO signal is updated to be high level. And then, reading the updated state value of the second GPIO signal by the CPLD logic circuit, and switching the chip currently accessed into the system based on the high level. Therefore, the second BIOS chip which needs firmware refreshing is accessed into the system.

In one embodiment, after the CPLD logic circuit is controlled to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal, the method includes:

Specifically, after the CPLD logic circuit is controlled to switch the chip currently accessed to the system by updating the current state value of the second GPIO signal, it is also necessary to determine whether the switching is successful to refresh the firmware, thereby avoiding an error.

Firstly, a server or a terminal reads the current state value of a first GPIO signal through a CPLD logic circuit; secondly, judging whether the current state value of the first GPIO signal and the last state value of the first GPIO signal change or not; if yes, determining that the BIOS chip of the current access system is the BIOS chip to be refreshed, reporting the successful switching result to the dual-BIOS system, refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file, and restarting the dual-BIOS system after refreshing. If not, the switching failure is indicated, the switching failure result is reported to the double BIOS system, and the refreshing failure is prompted.

In one embodiment, obtaining the identification of the BIOS chip to be refreshed includes:

acquiring a refreshing requirement of a user, wherein the refreshing requirement carries an identifier of one or two chips to be refreshed;

and acquiring the identification of the BIOS chip to be refreshed from the refreshing requirement of the user.

Specifically, the user can select to enter the BIOS firmware refresh interface after the server is powered on and enters the setup interface, and three options are provided on the BIOS firmware refresh interface for the user to select. The first option is to select firmware refreshing on the first BIOS chip, the second option is to select firmware refreshing on the second BIOS chip, and the third option is to select firmware refreshing on both the first BIOS chip and the second BIOS chip. The system obtains different refreshing requirements of the user according to the selection operation of different options of the user on the BIOS firmware refreshing interface.

For example, a user may select to perform BIOS firmware refresh on a certain BIOS chip in the dual BIOS system, and at this time, the system acquires that the refresh requirement of the user carries an identifier of a chip to be refreshed. Or the BIOS firmware can be refreshed for two BIOS chips in the dual BIOS system, and the system obtains the refresh requirement of the user and carries the identification of the two chips to be refreshed.

In the embodiment of the application, the user's refreshing requirement can carry the identifier of one or two chips to be refreshed, and after the system obtains the user's refreshing requirement, the system obtains the identifier of the BIOS chip to be refreshed from the user's refreshing requirement. Therefore, the BIOS chip to be refreshed corresponding to the identification is accessed into the system through the CPLD logic circuit based on the identification of the BIOS chip to be refreshed, the BIOS firmware refreshing file is obtained according to the identification, and firmware refreshing is carried out on the BIOS chip to be refreshed through the BIOS firmware refreshing file. Therefore, the situation that the wrong BIOS chip is accessed into the system and the BIOS chip which does not need to be refreshed by firmware is refreshed is reduced. The accuracy of the BIOS chip accessing to the system is improved, and the accuracy of firmware refreshing is further improved.

In one embodiment, the dual BIOS system includes a first BIOS chip and a second BIOS chip, the first BIOS chip and the second BIOS chip are two same chips;

before obtaining the identifier of the BIOS chip to be refreshed when the BIOS firmware of at least one BIOS chip in the dual BIOS system is refreshed, the method further includes:

and if the first BIOS chip of the current access system is damaged, accessing the second BIOS chip into the system through the CPLD logic circuit.

Specifically, the server or the terminal supports a dual BIOS system, and the dual BIOS system includes a first BIOS chip and a second BIOS chip, and the first BIOS chip and the second BIOS chip are the same two chips. Therefore, when the BIOS chip of any one access system fails, the BIOS chip can be switched to another BIOS chip access system. Because the first BIOS chip and the second BIOS chip are two same chips, normal startup use of the server or the terminal can still be guaranteed. Then, the BIOS chip with the fault can be repaired in the boot state.

Therefore, a firmware refreshing method is provided, if a first BIOS chip of the current access system is damaged, a server or a terminal accesses a second BIOS chip into the system through a CPLD logic circuit. Then, when BIOS firmware refreshing is carried out on at least one BIOS chip in the dual-BIOS system, the identification of the BIOS chip to be refreshed is obtained. And the server or the terminal accesses the BIOS chip to be refreshed corresponding to the identification into the system through a complex programmable logic device CPLD logic circuit. And acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file.

In the embodiment of the application, because the first BIOS chip and the second BIOS chip in the dual BIOS system are the same two chips, if the first BIOS chip of the current access system is damaged, the second BIOS chip is accessed to the system through the CPLD logic circuit, so that the server or the terminal is ensured to be normally started, and the normal use requirement is met. And the BIOS chip with the fault can be repaired in the boot-up state. Therefore, the problem that the server or the terminal cannot be normally started due to the damage of a certain BIOS chip of the access system, the normal use requirement cannot be met, and the firmware refreshing of the BIOS chip with the fault cannot be carried out is solved.

In the previous embodiment, if the first BIOS chip of the currently accessed system is damaged, the accessing the second BIOS chip to the system through the CPLD logic circuit includes:

Specifically, the state value of the second GPIO signal (GPIO-0) is set by the dual BIOS system. Specifically, when the system does not need to switch chips, the state value of the second GPIO signal is set to be a low level by default; correspondingly, when the system needs to switch chips, the state value of the second GPIO signal is updated to be high level. Therefore, if the first BIOS chip of the current access system is damaged, chip switching is required to ensure normal startup of the server or the terminal. Therefore, the system in the server or the terminal updates the current state value of the second GPIO signal to be a high level, and then reads the updated current state value of the second GPIO signal through the CPLD logic circuit to switch the chip currently accessed to the system. I.e. the BIOS chip currently accessing the system is switched from the first BIOS chip to the second BIOS chip.

In one embodiment, if the identifier of the to-be-refreshed chip is the identifier of the first BIOS chip, accessing the to-be-refreshed BIOS chip corresponding to the identifier to the system through the CPLD logic circuit, including:

reading the current state value of the first GPIO signal through a CPLD logic circuit, and determining whether a BIOS chip of a current access system is a first BIOS chip;

Specifically, when a first BIOS chip of the current access system is damaged, the access system is switched to a second BIOS chip first, and the system can be started normally. And then, when the first BIOS chip needs to be repaired, interrupting the normal working state of the system and switching to the damaged first BIOS chip to access the system. At this time, although the system cannot work normally, the first BIOS chip can be repaired after the system is already in the power-on state. As shown in fig. 4, there is provided a firmware refresh method including:

step 410, if the first BIOS chip of the current access system is damaged, accessing the second BIOS chip into the system through the CPLD logic circuit;

step 430, acquiring an identifier of the BIOS chip to be refreshed;

step 450, if the identification of the BIOS chip to be refreshed is the identification of the first BIOS chip, reading the current state value of the first GPIO signal through the CPLD logic circuit, and determining whether the BIOS chip of the current access system is the first BIOS chip;

step 470, if not, controlling the CPLD logic circuit to switch the second BIOS chip currently accessed to the system to the first BIOS chip by updating the current state value of the second GPIO signal;

step 490, the BIOS firmware refresh file is obtained according to the identification, and firmware refresh is performed on the BIOS chip to be refreshed through the BIOS firmware refresh file.

Specifically, when a BIOS chip (e.g., a first BIOS chip) accessing a system in a dual BIOS system is damaged, chip switching is required to ensure normal booting of a server or a terminal. Therefore, the system in the server or the terminal updates the current state value of the second GPIO signal to the high level. And reading the current state value of the updated second GPIO signal through the CPLD logic circuit, and switching the chip currently accessed into the system. I.e. the BIOS chip currently accessing the system is switched from the first BIOS chip to the second BIOS chip.

And secondly, acquiring an identifier of the BIOS chip to be refreshed, reading the current state value of the first GPIO signal through the CPLD logic circuit if the identifier of the BIOS chip to be refreshed is the identifier of the first BIOS chip, and determining whether the BIOS chip currently accessed to the system is the first BIOS chip.

Obviously, the BIOS chip currently accessing the system is the second BIOS chip, and then a chip switch is required. At this time, the system updates the current state value of the second GPIO signal to the high level again. And reading the updated current state value of the second GPIO signal through the CPLD logic circuit, and switching the chip currently accessed into the system. That is, the BIOS chip currently accessed to the system is switched back from the second BIOS chip to the damaged first BIOS chip, and the current state value of the second GPIO signal is restored to the default setting (low level) after switching.

And finally, acquiring a BIOS firmware refreshing file according to the identification, and refreshing the firmware of the BIOS chip (the first BIOS chip) to be refreshed through the BIOS firmware refreshing file.

In the embodiment of the application, if the first BIOS chip of the current access system is damaged, the current state value of the updated second GPIO signal is read by the CPLD logic circuit, and the chip in the current access system is switched. Therefore, the chip with the fault is switched to another normal chip, so that normal open work of the server or the terminal is guaranteed. And then, the CPLD logic circuit is controlled to switch a second BIOS chip currently accessed into the system into the first BIOS chip by updating the current state value of the second GPIO signal, so that firmware refreshing of the BIOS chip with a fault is ensured subsequently.

At this time, if the failed chip needs to be recovered, the CPLD logic circuit reads the current state value of the second GPIO signal after being updated again, and switches the chip currently accessed to the system again (i.e., switches to the original failed chip). And acquiring a BIOS firmware refreshing file corresponding to the fault chip, and refreshing the firmware of the fault chip through the BIOS firmware refreshing file. Therefore, when the chip fails, the chip can be rapidly switched through the CPLD logic circuit, and normal startup use of the server or the terminal is guaranteed. Meanwhile, the fault chip can be repaired in a targeted manner, and the maintenance difficulty is reduced.

In one embodiment, as shown in fig. 5, if the identifier of the to-be-refreshed chip is an identifier of two BIOS chips, the accessing the to-be-refreshed BIOS chip corresponding to the identifier to the system through the CPLD logic circuit includes:

step 242, reading the current state value of the first GPIO signal through the CPLD logic circuit;

step 244, acquiring a BIOS chip of the currently accessed system according to the current state value of the first GPIO signal, and taking the BIOS chip of the currently accessed system as a target BIOS chip to be refreshed;

the firmware refreshing of the BIOS chip to be refreshed is carried out through the BIOS firmware refreshing file, and the method comprises the following steps: step 246, firmware refreshing is performed on the target to-be-refreshed BIOS chip through the BIOS firmware refresh file.

Specifically, when the BIOS firmware of two BIOS chips in the dual BIOS system needs to be refreshed, the server or the terminal reads the current state value of the first GPIO signal through the CPLD logic circuit. Because the chip in the access system is the first BIOS chip, the state value of the first GPIO signal (GPIO-1) is kept at a high level. And when the chip in the access system is the second BIOS chip, the state value of the first GPIO signal (GPIO-1) is kept at low level. Therefore, the chip in the access system can be determined according to the current state value of the first GPIO signal at the moment.

Then, the BIOS chip of the current access system is used as the target BIOS chip to be refreshed, and the firmware of the chip in the access system can be refreshed directly. Specifically, the server or the terminal obtains a BIOS firmware refresh file corresponding to the target BIOS chip to be refreshed from the external device, and performs firmware refresh on the target BIOS chip to be refreshed through the BIOS firmware refresh file. The target BIOS chip to be refreshed is the BIOS chip which needs firmware refreshing currently when the two BIOS chips are refreshed.

In another embodiment, after performing firmware refresh on a target BIOS chip to be refreshed by a BIOS firmware refresh file, the method includes:

and refreshing the firmware of the new target BIOS chip to be refreshed through the BIOS firmware refreshing file.

As shown in fig. 6, a firmware refresh method is provided, which is applied to the case where both BIOS chips in a dual BIOS system need to be refreshed. The method comprises the following steps:

step 610, when BIOS firmware refreshing is carried out on two BIOS chips in the dual BIOS system, acquiring the identification of the BIOS chip to be refreshed;

step 620, reading the current state value of the first GPIO signal through the CPLD logic circuit;

step 630, acquiring a BIOS chip of the currently accessed system according to the current state value of the first GPIO signal, and taking the BIOS chip of the currently accessed system as a target BIOS chip to be refreshed;

step 640, performing firmware refreshing on the target BIOS chip to be refreshed through the BIOS firmware refreshing file;

step 650, controlling the CPLD logic circuit to switch the chips in the current access system by updating the current state value of the second GPIO signal, and taking the BIOS chip in the switched access system as a new target BIOS chip to be refreshed;

and 660, performing firmware refreshing on the new target BIOS chip to be refreshed through the BIOS firmware refreshing file.

Specifically, when BIOS firmware refreshing needs to be performed on two BIOS chips in a dual BIOS system, a server or a terminal first performs firmware refreshing on a chip currently accessed to the system. After firmware refreshing is carried out on the BIOS chip in the current access system, another BIOS chip is switched to the access system. Thus, the firmware of the chip accessed into the system at this time is refreshed. Therefore, BIOS firmware refreshing of two BIOS chips in the dual BIOS system is completed in sequence.

In the embodiment of the application, when BIOS firmware refreshing needs to be carried out on two BIOS chips in a dual-BIOS system, firmware refreshing is carried out in a mode of sequentially carrying out firmware refreshing. And firstly, firmware refreshing is carried out on the chip in the current access system, then another BIOS chip is switched to the access system, and firmware refreshing is carried out on the BIOS chip. Therefore, the refreshing sequence is clear, and chip switching is not required frequently, so that the firmware refreshing efficiency is improved.

And through the CPLD logic circuit, the BIOS chip to be refreshed is automatically accessed into the system, and because the BIOS chip access system does not need to be manually switched, the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

In a specific embodiment, as shown in fig. 7, there is provided a firmware refresh method, including:

step 702, after a server or a terminal is started and enters a setup interface, selecting to enter a BIOS firmware refreshing interface; step 704 is entered;

step 704, selecting to refresh the master BIOS chip and the slave BIOS chip or refresh the master BIOS chip and the slave BIOS chip simultaneously on the BIOS firmware refreshing interface; in one case, either the master BIOS chip or the slave BIOS chip is refreshed, then step 706 is entered; in another case, the master BIOS chip and the slave BIOS chip are refreshed at the same time, then step 730 is performed;

step 706, selecting a BIOS firmware refresh file from the peripheral storage device; step 708 is entered;

step 708, reading the current state value of the GPIO-1 through the CPLD logic circuit, and judging whether the chips accessed into the system need to be switched; if the switching is not needed, go to step 710; if the handover is required, go to step 712;

step 710, directly refreshing the firmware of the BIOS chip in the access system through the BIOS firmware refreshing file; entering step 720;

step 712, the system sets the state value of the GPIO-0 to be high level, reads the state value of the GPIO-0 through the CPLD logic circuit, and switches the chip currently accessed into the system; step 714 is entered;

step 714, reading the current state value of the GPIO-1 through the CPLD logic circuit, and judging whether the switching is successful; if the switch is successful, go to step 716; if the handover fails, go to step 718;

step 716, the firmware of the BIOS chip in the access system is refreshed through the BIOS firmware refresh file, and the state value of GPIO-0 is set to high level again after the refresh is completed, and the BIOS chip is switched back to the original BIOS chip access system; entering step 720;

step 718, prompting failure of updating;

and step 720, restarting the server or the terminal.

In another case, the flow of refreshing the master BIOS chip and the slave BIOS chip at the same time is as follows:

step 730, selecting a BIOS firmware refresh file from the peripheral storage device; proceed to step 732;

step 732, directly refreshing the firmware of the BIOS chip in the access system through the BIOS firmware refreshing file; step 734 is entered;

step 734, after the refreshing is completed, reading and storing the current state value of the GPIO-1 through the CPLD logic circuit, setting the state value of the GPIO-0 as a high level by the system, reading the state value of the GPIO-0 through the CPLD logic circuit, and switching the chips currently accessed into the system; step 736 is entered;

step 736, reading the current state value of the GPIO-1 through the CPLD logic circuit, and judging whether the switching is successful; if the handover is successful, go to step 738; if the handover fails, go to step 740;

step 738, firmware refreshing is carried out on the BIOS chip in the access system through the BIOS firmware refreshing file, the state value of GPIO-0 is set to be high level again after the refreshing is finished, and the BIOS chip is switched back to the original BIOS chip access system (because the system generally runs on the original main BIOS chip); entering step 720;

step 740, prompting which chip fails to update; step 720 is entered.

In the embodiment of the application, when firmware refreshing is performed on two BIOS chips in a dual BIOS system, two situations are included. In one case, either the master BIOS chip or the slave BIOS chip is refreshed; in another case, the master BIOS chip and the slave BIOS chip are refreshed simultaneously.

When any one of the master BIOS chip or the slave BIOS chip is refreshed, the chips are switched through the CPLD logic circuit, so that the BIOS chip to be refreshed is automatically accessed into the system, and the firmware of the BIOS chip to be refreshed can be directly refreshed. When the master BIOS chip and the slave BIOS chip are refreshed at the same time, the refreshing is carried out by adopting a mode of sequentially refreshing the firmware. And firstly, firmware refreshing is carried out on the chip in the current access system, then another BIOS chip is switched to the access system, and firmware refreshing is carried out on the BIOS chip. Therefore, the refreshing sequence is clear, and chip switching is not required frequently, so that the firmware refreshing efficiency is improved.

And the BIOS chip access system does not need to be switched manually, so that the accuracy of the BIOS chip access system is improved, and the accuracy of firmware refreshing is improved.

In one embodiment, as shown in FIG. 8, there is provided a firmware refresh apparatus 800, comprising:

an obtaining module 820, configured to obtain an identifier of a BIOS chip to be refreshed when performing BIOS firmware refresh on at least one BIOS chip in a dual BIOS system;

the access module 840 is used for accessing the BIOS chip to be refreshed corresponding to the identifier into the system through the complex programmable logic device CPLD logic circuit;

and the firmware refreshing module 860 is used for acquiring the BIOS firmware refreshing file according to the identifier and refreshing the firmware of the BIOS chip to be refreshed through the BIOS firmware refreshing file.

In one embodiment, the access module 840 is further configured to read the GPIO signal through the CPLD logic circuit; and accessing the BIOS chip to be refreshed into the system according to the GPIO signal.

In one embodiment, the access module 840 includes:

the first GPIO signal reading unit is used for reading the current state value of the first GPIO signal through the CPLD logic circuit;

the judging unit is used for judging whether the BIOS chip of the current access system is a BIOS chip to be refreshed or not according to the current state value of the first GPIO signal;

and the chip switching unit is used for controlling the CPLD logic circuit to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal if the current state value of the second GPIO signal is not updated.

In one embodiment, the access module 840 further includes:

the switching success confirming unit is used for reading the current state value of the first GPIO signal through the CPLD logic circuit; judging whether the current state value of the first GPIO signal and the last state value of the first GPIO signal change or not; if yes, determining that the BIOS chip of the current access system is the BIOS chip to be refreshed, and reporting the successful switching result to the dual-BIOS system.

In one embodiment, as shown in fig. 9, the dual BIOS system includes a first BIOS chip and a second BIOS chip, where the first BIOS chip and the second BIOS chip are the same two chips; there is provided a firmware refresh apparatus 800, further comprising:

and a chip damage and switching module 880, configured to control the CPLD logic circuit to switch the chip currently accessed to the system by updating the current state value of the second GPIO signal if the first BIOS chip currently accessed to the system is damaged.

In one embodiment, if the identifier of the chip to be refreshed is the identifier of the first BIOS chip, the access module 840 is further configured to read the current state value of the first GPIO signal through the CPLD logic circuit, and determine whether the BIOS chip currently accessed to the system is the first BIOS chip; if not, the CPLD logic circuit is controlled to switch the second BIOS chip currently accessed into the system into the first BIOS chip by updating the current state value of the second GPIO signal.

In one embodiment, if the identifiers of the chips to be refreshed are identifiers of two BIOS chips, the access module 840 is further configured to read the current state value of the first GPIO signal through the CPLD logic circuit; acquiring a BIOS chip of the current access system according to the current state value of the first GPIO signal, and taking the BIOS chip of the current access system as a target BIOS chip to be refreshed;

the firmware refreshing module 860 is further configured to perform firmware refreshing on the target BIOS chip to be refreshed through the BIOS firmware refreshing file.

In the previous embodiment, the access module 840 is further configured to control the CPLD logic circuit to switch the chip currently accessed to the system by updating the current state value of the second GPIO signal, and use the BIOS chip accessed to the system after switching as a new target BIOS chip to be refreshed;

the firmware refreshing module 860 is further configured to perform firmware refreshing on the new target BIOS chip to be refreshed through the BIOS firmware refreshing file.

The division of each module in the firmware refreshing apparatus is only for illustration, and in other embodiments, the firmware refreshing apparatus may be divided into different modules as needed to complete all or part of the functions of the firmware refreshing apparatus.

Fig. 10 is a schematic diagram of an internal configuration of a server in one embodiment. As shown in fig. 10, the server includes a processor and a memory connected by a system bus. Wherein, the processor is used for providing calculation and control capability and supporting the operation of the whole server. The memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The computer program is executable by a processor for implementing a firmware refresh method provided in the following embodiments. The internal memory provides a cached execution environment for the operating system computer programs in the non-volatile storage medium. The server may be a mobile phone, a tablet computer, or a personal digital assistant or a wearable device, etc.

The implementation of the various modules in the firmware refresh device provided in the embodiments of the present application may be in the form of a computer program. The computer program may be run on a terminal or a server. The program modules constituted by the computer program may be stored on the memory of the terminal or the server. Which when executed by a processor, performs the steps of the method described in the embodiments of the present application.

The embodiment of the application also provides a computer readable storage medium. One or more non-transitory computer-readable storage media containing computer-executable instructions that, when executed by one or more processors, cause the processors to perform the steps of the firmware refresh method.

A computer program product comprising instructions which, when run on a computer, cause the computer to perform a firmware refresh method.

Any reference to memory, storage, database, or other medium used by embodiments of the present application may include non-volatile and/or volatile memory. Suitable non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A firmware refresh method, comprising:

2. The method according to claim 1, wherein said accessing the BIOS chip to be refreshed corresponding to the identifier to the system through a complex programmable logic device CPLD logic circuit comprises:

reading the GPIO signal through a CPLD logic circuit;

3. The method of claim 2, wherein the GPIO signals comprise a first GPIO signal and a second GPIO signal, wherein a state value of the first GPIO signal is used for distinguishing a BIOS chip in a current access system, wherein the state value of the first GPIO signal is updated according to whether switching of the chip in the dual BIOS system is successful or not, and wherein the state value of the second GPIO signal is updated by the dual BIOS system based on whether the chip switching is required or not.

4. The method according to claim 3, wherein said reading GPIO signals by CPLD logic circuit, accessing said BIOS chip to be refreshed to system according to said GPIO signals, comprises:

5. The method of claim 4, wherein after the controlling the CPLD logic circuit to switch the chip currently accessed into the system by updating the current state value of the second GPIO signal, the method comprises:

6. The method of claim 1, wherein the dual BIOS system comprises a first BIOS chip and a second BIOS chip, and the first BIOS chip and the second BIOS chip are two same chips;

7. The method according to claim 6, wherein if the identifier of the to-be-refreshed chip is the identifier of the first BIOS chip, the accessing the to-be-refreshed BIOS chip corresponding to the identifier to the system through the CPLD logic circuit includes:

8. The method according to claim 1, wherein if the identifications of the to-be-refreshed chips are identifications of two BIOS chips, the accessing the to-be-refreshed BIOS chip corresponding to the identifications to a system through a CPLD logic circuit includes:

9. The method of claim 8, wherein after the firmware refresh of the target BIOS chip to be refreshed by the BIOS firmware refresh file, the method comprises:

10. A firmware refresh apparatus, comprising:

11. A server comprising a memory and a processor, the memory having stored therein a computer program, wherein the computer program, when executed by the processor, causes the processor to perform the steps of the firmware refresh method of any one of claims 1 to 9.

12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the firmware refresh method according to any one of claims 1 to 9.