CN111936965A - 随机舍入逻辑 - Google Patents

随机舍入逻辑 Download PDF

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Publication number
CN111936965A
CN111936965A CN201980021078.2A CN201980021078A CN111936965A CN 111936965 A CN111936965 A CN 111936965A CN 201980021078 A CN201980021078 A CN 201980021078A CN 111936965 A CN111936965 A CN 111936965A
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China
Prior art keywords
csa
input
logic
carry
output
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CN201980021078.2A
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Chinese (zh)
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加布里埃尔·H·洛
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of CN111936965A publication Critical patent/CN111936965A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
CN201980021078.2A 2018-03-22 2019-03-18 随机舍入逻辑 Pending CN111936965A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/933,229 US10628124B2 (en) 2018-03-22 2018-03-22 Stochastic rounding logic
US15/933,229 2018-03-22
PCT/US2019/022685 WO2019182943A1 (en) 2018-03-22 2019-03-18 Stochastic rounding logic

Publications (1)

Publication Number Publication Date
CN111936965A true CN111936965A (zh) 2020-11-13

Family

ID=65952226

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980021078.2A Pending CN111936965A (zh) 2018-03-22 2019-03-18 随机舍入逻辑

Country Status (6)

Country Link
US (1) US10628124B2 (ko)
EP (1) EP3769208B1 (ko)
JP (1) JP7292297B2 (ko)
KR (1) KR20200134281A (ko)
CN (1) CN111936965A (ko)
WO (1) WO2019182943A1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113791756A (zh) * 2021-09-18 2021-12-14 中科寒武纪科技股份有限公司 转数方法、存储介质、装置及板卡
CN113835677A (zh) * 2021-09-23 2021-12-24 龙芯中科技术股份有限公司 操作数处理系统、方法及处理器

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108256644B (zh) * 2018-01-05 2021-06-22 上海兆芯集成电路有限公司 微处理器电路以及执行神经网络运算的方法
US11615782B2 (en) * 2020-11-12 2023-03-28 Sony Interactive Entertainment Inc. Semi-sorted batching with variable length input for efficient training

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040078401A1 (en) * 2002-10-22 2004-04-22 Hilton Howard E. Bias-free rounding in digital signal processing
CN1609813A (zh) * 2003-10-24 2005-04-27 英特尔公司 减少硬件的软错误检测
CN101042583A (zh) * 2006-02-09 2007-09-26 阿尔特拉公司 用于可编程逻辑器件的专门处理块
US20090287757A1 (en) * 2008-05-15 2009-11-19 Rarick Leonard D Leading Zero Estimation Modification for Unfused Rounding Catastrophic Cancellation
US8533250B1 (en) * 2009-06-17 2013-09-10 Altera Corporation Multiplier with built-in accumulator
CN107025091A (zh) * 2016-02-01 2017-08-08 国际商业机器公司 二进制融合乘加浮点计算

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974435A (en) * 1997-08-28 1999-10-26 Malleable Technologies, Inc. Reconfigurable arithmetic datapath
US8019805B1 (en) 2003-12-09 2011-09-13 Globalfoundries Inc. Apparatus and method for multiple pass extended precision floating point multiplication
JP4544870B2 (ja) * 2004-01-26 2010-09-15 富士通セミコンダクター株式会社 演算回路装置
US9710228B2 (en) * 2014-12-29 2017-07-18 Imagination Technologies Limited Unified multiply unit
US10108397B2 (en) * 2015-08-25 2018-10-23 Samsung Electronics Co., Ltd. Fast close path solution for a three-path fused multiply-add design
US9940102B2 (en) * 2016-01-04 2018-04-10 International Business Machines Corporation Partial stochastic rounding that includes sticky and guard bits
US10489152B2 (en) 2016-01-28 2019-11-26 International Business Machines Corporation Stochastic rounding floating-point add instruction using entropy from a register

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040078401A1 (en) * 2002-10-22 2004-04-22 Hilton Howard E. Bias-free rounding in digital signal processing
CN1609813A (zh) * 2003-10-24 2005-04-27 英特尔公司 减少硬件的软错误检测
CN101042583A (zh) * 2006-02-09 2007-09-26 阿尔特拉公司 用于可编程逻辑器件的专门处理块
US20090287757A1 (en) * 2008-05-15 2009-11-19 Rarick Leonard D Leading Zero Estimation Modification for Unfused Rounding Catastrophic Cancellation
US8533250B1 (en) * 2009-06-17 2013-09-10 Altera Corporation Multiplier with built-in accumulator
CN107025091A (zh) * 2016-02-01 2017-08-08 国际商业机器公司 二进制融合乘加浮点计算

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
何军等: "分离通路浮点乘加器设计与实现", 计算机科学, no. 08, 15 August 2013 (2013-08-15) *
刘鸿瑾等: "基于快速舍入的双精度浮点乘法器的设计", 微电子学与计算机, no. 06, 20 July 2006 (2006-07-20) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113791756A (zh) * 2021-09-18 2021-12-14 中科寒武纪科技股份有限公司 转数方法、存储介质、装置及板卡
CN113791756B (zh) * 2021-09-18 2022-12-23 中科寒武纪科技股份有限公司 转数方法、存储介质、装置及板卡
CN113835677A (zh) * 2021-09-23 2021-12-24 龙芯中科技术股份有限公司 操作数处理系统、方法及处理器

Also Published As

Publication number Publication date
JP2021517301A (ja) 2021-07-15
US20190294412A1 (en) 2019-09-26
US10628124B2 (en) 2020-04-21
EP3769208A1 (en) 2021-01-27
EP3769208B1 (en) 2022-10-26
JP7292297B2 (ja) 2023-06-16
KR20200134281A (ko) 2020-12-01
WO2019182943A1 (en) 2019-09-26

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