CN111935020A - Message generation method and circuit and storage medium - Google Patents
Message generation method and circuit and storage medium Download PDFInfo
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- CN111935020A CN111935020A CN202011004819.7A CN202011004819A CN111935020A CN 111935020 A CN111935020 A CN 111935020A CN 202011004819 A CN202011004819 A CN 202011004819A CN 111935020 A CN111935020 A CN 111935020A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
- H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
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Abstract
The application relates to a message generating method, a circuit and a storage medium, wherein after a message is received, a front-end address of a current storage address is divided into reserved addresses, the message is sequentially written into next-bit addresses of the reserved addresses, after the message is written, key information in the middle of the message or key information which can be obtained after the message is received can be obtained from the message, a section of storage address is reserved at the front end of the current storage address, the key information of the message is written back to the reserved addresses at the moment, the message received by a receiver is the message with the key information in front, the message data in the back is convenient for the receiver to read the message, and the efficiency of the receiver in writing the message is not influenced.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method and a circuit for generating a packet, and a storage medium.
Background
In the prior art, when a message is received, the message generally needs to be cached, some key information in the message is extracted at the same time, and the key information is forwarded after being processed without errors. When a message is received, an entry logic First determines the Start and End Of the message, generally, the Start and End are indicated by using auxiliary SOP (Start Of Packet) and EOP (End Of Packet) signals, a message memory usually writes In a FIFO (First In First Out) format, although the FIFO has a characteristic Of First In First Out to ensure that the sequence Of the content Of the message is excellent, some key information Of the message can be obtained only In the middle Of the message or after the message is received, and because Of the structural problem Of the FIFO, the key information can only be written In the rearmost Of the message. However, the message generated in this way can only be obtained by the receiver at the end when being forwarded. That is, the prior art also adopts a dual FIFO mode, that is, these key information are stored in other places, one FIFO stores message data, and the other FIFO stores key information, so that when a message is forwarded, the message is sent first, and then the message is sent. The receiver may first retrieve the critical information from the information FIFO and then retrieve the message from the data FIFO. However, by doing so, the synchronicity of the FIFOs needs to be optimized, while the depth of the FIFO storing critical information is not easily controlled (too large to be wasted and too small to overflow). When the message is written in, the message FIFO needs to be written in first, then the information FIFO needs to be written in, when the message is read, the information FIFO needs to be read first, then the message FIFO needs to be read, and reading and writing are controlled, so that the operation is complicated.
Disclosure of Invention
To overcome at least some of the problems in the related art, the present application provides a message generation method, a circuit and a storage medium.
The scheme of the application is as follows:
according to a first aspect of the embodiments of the present application, a method for generating a packet is provided, including:
receiving a message;
dividing the front end address of the current storage address into a reserved address, and sequentially writing the messages into the secondary addresses of the reserved address;
and after the message is written, extracting key information from the message, and writing the key information of the message back to the reserved address.
Preferably, in an implementation manner of the present application, the method further includes:
grouping the messages, and when determining the circulation, sequentially writing the messages of each group according to the circulation.
Preferably, in an implementation manner of the present application, the key information of the message at least includes: the HASH value, the password, the index, the length, the destination address, the source and the mapping table of the message.
Preferably, in an implementation manner of the present application, the extracting key information from the message specifically includes:
and extracting required key information from the message according to the application scene of the message.
Preferably, in an implementation manner of the present application, the extracting, according to the application scenario of the packet, required key information from the packet specifically includes:
if the application scene of the message is simple forwarding, extracting destination address information from the message;
if the application scene of the message is simple decryption, extracting password information or HASH value and index information from the message;
and if the application scene of the message is source seeking, extracting source information from the message.
Preferably, in an implementation manner of the present application, the dividing the front-end address of the current storage address into the reserved address specifically includes:
and according to the application scene of the message, dividing a reserved address with a corresponding size in the front-end address of the current storage address.
Preferably, in an implementation manner of the present application, the method further includes: and writing the message according to an FIFO format.
Preferably, in an implementation manner of the present application, the method further includes:
and after the message is completely written, forwarding the message according to the written format.
According to a second aspect of the embodiments of the present application, there is provided a packet generation circuit, including:
a processor and a memory;
the processor and the memory are connected through a communication bus:
the processor is used for calling and executing the program stored in the memory;
the memory is configured to store a program, and the program is at least configured to execute any one of the message generation methods described above.
According to a third aspect of embodiments of the present application, there is provided a storage medium storing a computer program which, when executed by a processor, implements a message generation method as described in any one of the above.
The technical scheme provided by the application can comprise the following beneficial effects: according to the method and the device, after the message is received, the front-end address of the current storage address is divided into the reserved addresses, the message is sequentially written into the secondary addresses of the reserved addresses, after the message is written, key information in the middle of the message or key information which can be obtained after the message is received can be obtained from the message, a section of storage address is reserved at the front end of the current storage address, the key information of the message is written back to the reserved addresses, the message received by a receiver is the message with the key information in front, the message data in the back is the message, the receiver can read the message conveniently, and the efficiency of the local message writing is not affected.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flowchart of a message generation method according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a message written into a storage address in a message generation method according to an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a message being written into a storage address in a message generation method according to another embodiment of the present application;
fig. 4 is a schematic flowchart of a message generation method according to another embodiment of the present application;
fig. 5 is a schematic structural diagram of a message generation circuit according to an embodiment of the present application.
Reference numerals: a processor-21; a memory-22.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Fig. 1 is a schematic flow diagram of a message generation method according to an embodiment of the present application, and referring to fig. 1, a message generation method includes:
s11: receiving a message;
s12: dividing the front end address of the current storage address into a reserved address, and sequentially writing the message into a secondary address of the reserved address;
and according to the application scene of the message, dividing a reserved address with a corresponding size in the front-end address of the current storage address.
The application scenario of the packet may be: simple forwarding, simple decryption, source seeking and the like.
The key information corresponding to different application scenes is different, the length of the corresponding key information can be estimated according to the application scenes of the message, and the length of the reserved address can be divided according to the length of the key information.
Preferably, the length of the reserved address is the minimum address where the key information can be loaded.
S13: referring to fig. 2, after the message is written, key information is extracted from the message, and the key information of the message is written back to the reserved address.
The key information of the message at least comprises: HASH value, cipher, index, length, destination address, source and mapping table of the message.
The HASH value and length of the message can be obtained only after the last beat of data of the message is received, and key information such as a sending destination and the like is generally hidden in the middle section of the message.
Extracting key information from the message based on the key information of the message, which specifically comprises the following steps:
and extracting required key information from the message according to the application scene of the message.
For example, the following steps are carried out:
1) if the application scene of the message is simple forwarding, extracting destination address information from the message;
2) if the application scene of the message is simple decryption, extracting the password information or HASH value and index information from the message;
3) if the application scene of the message is source solving, extracting source information from the message;
4) and if the application scene of the message is the destination, extracting destination address information from the message.
Referring to fig. 3, a method for generating a packet in some embodiments further includes:
grouping the messages, and writing each group of messages in sequence according to the cycle when the cycle is determined.
Generally, a received message is a plurality of groups of data, in this embodiment, the messages are grouped, and after a group of messages is written, the steps S12-S13 are repeatedly executed until all the groups of messages in the message are written.
In the message generation method in some embodiments, preferably, the message is written in a FIFO format.
The FIFO format structure is used to ensure that the order of the message contents is superior.
Referring to fig. 4, a method for generating a packet in some embodiments further includes:
s14: and after the message is completely written, forwarding the message according to the written format.
After one message is completely written, the messages with the FIFO structure are forwarded, and in the forwarded messages, each group of messages is in front of key information and behind message data, so that a receiver can conveniently read the messages.
The message generating method in the implementation divides the front end address of the current storage address into the reserved address after receiving the message, sequentially writes the message into the next-order address of the reserved address, and after the message is written, the key information of the middle section of the message or the key information which can not be obtained after the message is received can be obtained from the message. The message received by the receiver is the message with the key information in front and the message data in back, so that the receiver can read the message conveniently, and the efficiency of writing the message locally is not influenced.
Meanwhile, because the length information of the message is written back at the front end of the message, a receiver can easily know how long the message is when receiving the message, so that the EOP status of the message is calculated, the EOP information of the message does not need to be stored specially, and one mark can be saved.
The application of the method in the embodiment in NFC is illustrated as follows:
in the 14443 protocol, the first byte of the packet, that is, the length indication of the required packet, may be implemented by applying the packet generation method in this application.
When the method is applied, when a message sent by an upper layer protocol is received, the NFC forwarding logic does not need to tell the long message of the NFC forwarding logic message, skips the reserved address to start receiving the message, starts to calculate the length, and writes the counted length back to the skipped reserved address after the message is received. Thus, when forwarding, the first data read by the receiver is the length information of the message.
Fig. 5 is a schematic structural diagram of a message generation circuit according to an embodiment of the present application, and referring to fig. 5, the message generation circuit includes:
a processor 21 and a memory 22;
the processor 21 is connected to the memory 22 by a communication bus:
the processor 21 is configured to call and execute a program stored in the memory 22;
a memory 22 for storing a program for executing at least the message generation method in any of the above embodiments.
A storage medium storing a computer program which, when executed by a processor, implements a message generation method as in any one of the above embodiments.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A message generation method is characterized by comprising the following steps:
receiving a message;
dividing the front end address of the current storage address into a reserved address, and sequentially writing the messages into the secondary addresses of the reserved address;
and after the message is written, extracting key information from the message, and writing the key information of the message back to the reserved address.
2. The method of claim 1, further comprising:
grouping the messages, and when determining the circulation, sequentially writing the messages of each group according to the circulation.
3. The method according to claim 1, wherein the key information of the packet at least comprises: the HASH value, the password, the index, the length, the destination address, the source and the mapping table of the message.
4. The method according to claim 1, wherein the extracting key information from the message specifically includes:
and extracting required key information from the message according to the application scene of the message.
5. The method according to claim 4, wherein the extracting required key information from the message according to the application scenario of the message specifically includes:
if the application scene of the message is simple forwarding, extracting destination address information from the message;
if the application scene of the message is simple decryption, extracting password information or HASH value and index information from the message;
and if the application scene of the message is source seeking, extracting source information from the message.
6. The method according to claim 4, wherein the dividing the front-end address of the current storage address into the reserved address specifically comprises:
and according to the application scene of the message, dividing a reserved address with a corresponding size in the front-end address of the current storage address.
7. The method of claim 1, further comprising: and writing the message according to an FIFO format.
8. The method of claim 2, further comprising:
and after the message is completely written, forwarding the message according to the written format.
9. A message generation circuit, comprising:
a processor and a memory;
the processor and the memory are connected through a communication bus:
the processor is used for calling and executing the program stored in the memory;
the memory for storing a program for performing at least the message generation method of any of claims 1-8.
10. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the message generation method according to any one of claims 1 to 8.
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| CN202011004819.7A CN111935020A (en) | 2020-09-22 | 2020-09-22 | Message generation method and circuit and storage medium |
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Cited By (1)
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| CN113709061A (en) * | 2021-07-23 | 2021-11-26 | 合肥忆芯电子科技有限公司 | Message forwarding method and circuit |
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