CN109101439A - A kind of method and device of Message processing - Google Patents
A kind of method and device of Message processing Download PDFInfo
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- CN109101439A CN109101439A CN201710475363.4A CN201710475363A CN109101439A CN 109101439 A CN109101439 A CN 109101439A CN 201710475363 A CN201710475363 A CN 201710475363A CN 109101439 A CN109101439 A CN 109101439A
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- 238000003672 processing method Methods 0.000 description 9
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
A kind of method and device of Message processing is disclosed herein, comprising: accelerator sends consistency write request to consistency system interconnection unit；The consistency system interconnection unit confirm the consistency write request corresponding data whether the CPU caching, the corresponding data of the consistency write request executes consistency treatment in the caching of the CPU；After completing the consistency treatment, the CPU reads corresponding data from memory.The application can save the expense of CPU maintenance cache consistency, effectively improve the speed of Message processing.
Description
Technical field
The present invention relates to field of computer technology, and in particular to a kind of method and device of Message processing.
Background technique
Currently, usual peripheral hardware or accelerator have oneself dimension in a system on chip (SOC, System On Chip)
The spatial cache of shield does not need to interact operation with CPU, this segment space only needs software distribution in memory management,
And accelerator is supplied information to, it is voluntarily managed by accelerator.Another part then needs real with CPU in a manner of shared drive
It now interacts, i.e., memory is written in descriptor and message by peripheral hardware or accelerator, and then interrupt notification CPU is handled.Alternatively, CPU is initial
Change descriptor and message, memory is written, peripheral hardware or accelerator is notified to read.And in a high performance SOC, CPU can be enabled
It caches (cache), when this allows for each CPU processing message, requires to consider memory consistency problem.In addition, CPU is from memory
Before the message for reading accelerator write-in, first invalid corresponding cacheline (cacheline) is needed, then could be obtained in memory
The newest data in face；Equally, after cache is written in the message of initialization by CPU, corresponding cacheline need to be removed
(cacheline clean) arrives memory, this performance for allowing for CPU processing message is restricted.
For in the related technology, CPU needs to safeguard the expense of cache consistency, Message processing slow skill when handling message
Art problem, currently no effective solution has been proposed.
Summary of the invention
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of pair of message accelerate processing realization device and
Method, can solve that CPU processing message expense is big, slow-footed asks while not influencing original accelerator and manage oneself caching
Topic.
The embodiment of the invention provides:
A kind of method of Message processing, comprising:
Accelerator sends consistency write request to consistency system interconnection unit；
Whether the consistency system interconnection unit confirms the corresponding data of the consistency write request in the CPU
Caching, the corresponding data of the consistency write request executes consistency treatment in the caching of the CPU；
After completing the consistency treatment, the CPU reads corresponding data from memory.
Wherein, the accelerator sends consistency write request to consistency system interconnection unit, comprising: according to corresponding
The memory attribute of data judges whether to need to be implemented consistency treatment；When needing to be implemented consistency treatment, to consistency system
Interconnection unit sends consistency write request.
Wherein, the corresponding data of the consistency write request executes consistency treatment in the caching of the CPU, comprising:
The corresponding data of the consistency write request is confirmed in the caching of the CPU, and consistency system interconnection unit is to described
CPU sends consistency write request, and the CPU is returned the corresponding data in the caching by consistency system interconnection unit
Memory is written, memory is written in the corresponding data that the consistency system interconnection unit sends the accelerator later.
Wherein, the accelerator to consistency system interconnection unit send consistency write request after, the CPU from
Memory is read before corresponding data, further includes: confirms the corresponding data of the consistency write request not in the caching of the CPU
When, memory is written in the corresponding data that the consistency interconnection directly sends accelerator.
Wherein, the corresponding data of the consistency write request is message and descriptor.
A kind of method of Message processing, comprising:
Accelerator sends consistency read request to consistency system interconnection unit；
Whether the consistency system interconnection unit confirms the corresponding data of the consistency read request in the CPU
Caching, the corresponding data of the consistency read request executes consistency treatment in the caching of the CPU；
After completing the consistency treatment, accelerator obtains corresponding data.
Wherein, the accelerator sends consistency read request to consistency system interconnection unit, comprising: according to corresponding
The memory attribute of data judges whether to need to be implemented consistency treatment；When needing to be implemented consistency treatment, to consistency system
Interconnection unit sends consistency read request.
Wherein, the corresponding data of the consistency read request executes consistency treatment in the caching of the CPU, comprising:
The corresponding data of the consistency read request is confirmed in the caching of the CPU, and consistency system interconnection unit is to described
CPU sends consistency read request, and the corresponding data in the caching is passed through the consistency system interconnection list by the CPU
Member returns to accelerator.
Wherein, the accelerator to consistency system interconnection unit send consistency read request after, the acceleration
Device obtain corresponding data before, further includes: confirm the corresponding data of the consistency read request not in the caching of the CPU,
The consistency read request that the accelerator is sent is sent to memory by the consistency interconnection, and accelerator is from the memory
Middle acquisition corresponding data.
Wherein, the consistency read request is the consistency read request of descriptor, the respective counts of the consistency read request
According to for descriptor；And/or the consistency read request be message consistency read request, the consistency read request it is corresponding
Data are message.
Wherein, when the corresponding data that the accelerator obtains is descriptor, the accelerator is further according to the descriptor
The insertion message address of interior offer continues the consistency read request for sending corresponding message and obtains corresponding message.
A kind of device of Message processing, comprising: accelerator, consistency system interconnection unit, CPU；
The accelerator, including consistency request control unit and write-read DCU data control unit, the consistency request control
Unit processed is used to send consistency write request to consistency system interconnection unit；Alternatively, for being interconnected to consistency system
Bus unit sends consistency read request；The write-read DCU data control unit, for obtaining the corresponding of the consistency read request
Data；
The consistency system interconnection unit, for confirming the corresponding data of the consistency write request whether in institute
The caching for stating CPU executes one with the CPU when the corresponding data of the consistency write request is in the caching of the CPU jointly
The processing of cause property；Alternatively, for confirming the corresponding data of the consistency read request whether in the caching of the CPU, described
The corresponding data of consistency read request executes consistency treatment with the CPU in the caching of the CPU jointly；
The CPU, for reading the respective counts of the consistency write request from memory after completing the consistency treatment
According to.
Wherein, the accelerator, further includes: queue number memory attribute mapping register table, the queue number memory attribute
Mapping register table preserves the memory attribute of the data；The consistency requests control unit, is specifically used for according to
The memory attribute of data described in queue number memory attribute mapping register table, judges whether to need to be implemented consistency treatment；?
When needing to be implemented consistency treatment, consistency write request or consistency read request are sent to consistency system interconnection unit.
Wherein, the consistency system interconnection unit, specifically for confirming the respective counts of the consistency write request
When according to the caching for being present in the CPU, consistency write request is sent to the CPU, by the corresponding data from the cpu cache
It is written back into memory, memory is written in the corresponding data for later again sending the accelerator；
The CPU is also used to when receiving the consistency write request that the consistency system interconnection unit is sent, will
The corresponding data of consistency write request described in caching is sent to the consistency system interconnection unit, in being written back into
It deposits；
The write-read DCU data control unit is also used to for the corresponding data of the consistency write request being sent to described consistent
Property system interconnection unit, so that memory is written.
Wherein, the consistency system interconnection unit is also used in the respective counts for confirming the consistency write request
Memory is written according to the corresponding data not in the caching of the CPU, directly sent accelerator.
Wherein, the consistency system interconnection unit, specifically for confirming the respective counts of the consistency read request
According in the caching of the CPU, consistency read request is sent to the CPU, receives the corresponding data that the CPU is sent and return
To accelerator；
The CPU is also used to when receiving the consistency read request that the consistency system interconnection unit is sent, will
The corresponding data of consistency read request described in caching is sent to the consistency system interconnection unit, so as to described consistent
Property system interconnection unit returns to accelerator；
The write-read DCU data control unit of the accelerator is specifically used for receiving the consistency system interconnection unit hair
The corresponding data sent.
Wherein, the consistency system interconnection unit, specifically for confirming the respective counts of the consistency read request
According to not in the caching of the CPU, the consistency read request that the accelerator is sent directly is sent to memory, and will come from
The corresponding data of the memory, the described consistency read request returns to accelerator；The write-read DCU data control unit, it is specific to use
In the corresponding data for receiving the consistency system interconnection unit transmission.
Wherein, the consistency read request is the consistency read request of descriptor, the respective counts of the consistency read request
According to for descriptor；And/or the consistency read request be message consistency read request, the consistency read request it is corresponding
Data are message.
In the embodiment of the present invention, phase can be completed jointly by accelerator, CPU and consistency system interconnection unit
The consistency treatment answered can achieve the effect of transparent processing message compared to processing message process in the related technology, save
The expense of CPU maintenance cache consistency, effectively improves the speed of Message processing.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is the flow diagram of message processing method in the embodiment of the present invention one；
Fig. 2 is the flow diagram of message processing method in the embodiment of the present invention two；
Fig. 3 is the structural schematic diagram of message process device in the embodiment of the present invention three；
Fig. 4 is the exemplary block diagram of message process device in example 1；
Fig. 5 is the schematic diagram of example packet's process flow in example 3；
Fig. 6 is the schematic diagram of example packet's process flow in example 4.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
Embodiment one
The present embodiment provides a kind of methods of Message processing, as shown in Figure 1, comprising:
Step 101, accelerator sends consistency write request to consistency system interconnection unit；
Step 102, the consistency system interconnection unit confirm the consistency write request corresponding data whether
Consistency treatment is executed in the caching of the CPU in the corresponding data of the caching of the CPU, the consistency write request；
Step 103, after completing the consistency treatment, the CPU reads corresponding data from memory.
In the present embodiment, pass through accelerator, CPU and consistency system interconnection when CPU is from memory read data
Unit completes corresponding consistency treatment jointly, compared to processing message process in the related technology, can achieve transparent place
The effect for managing message saves the expense of CPU maintenance cache consistency, effectively improves the speed of Message processing.
In the present embodiment, (MMU, the Memory Management of memory management unit in CPU can be preset
Unit memory attribute), the memory attribute can be set as: accelerator and CPU have the shared drive buffer area of data interaction (to compare
Such as, the region in cache or memory) it is set as that (shareable) (indicating that CPU and accelerator may have access to the region) can be shared
Or (cacheable) (indicating that CPU can be by cache buffer memory data) can be buffered.Meanwhile setting descriptor team in accelerator
It is set inside column, the memory attribute of message and the MMU consistent.So, it can be ensured that at least partly region in cache and DDR
It is that accelerator and CPU can be accessed.
In the present embodiment, it can judge whether to need to be implemented consistency treatment according to the memory attribute of corresponding data；It is needing
When executing consistency treatment, consistency write request is sent to consistency system interconnection unit.
Further, it is also possible to its message matching rule is set in accelerator according to information such as the type of message, length, so as to
It can determine whether corresponding message supports that shared (e.g., CPU passes through accelerator with CPU according to the message matching rule in accelerator
Data or CPU are extracted to accelerator insertion data etc.).That is, accelerator can be sentenced previously according to the descriptor of message
Whether the message that breaks meets above-mentioned message matching rule, meet above-mentioned message matching it is regular in the case where the present embodiment again it is upper
State message processing method.
In a kind of implementation, the corresponding data of the consistency write request executes consistency in the caching of the CPU
Processing may include: to confirm the corresponding data of the consistency write request in the caching of the CPU, and consistency system interconnects
Bus unit sends consistency write request to the CPU, and the CPU passes through consistency system interconnection unit for the caching
In corresponding data be written back into memory, the consistency system interconnection unit sends the accelerator corresponding later
Memory is written in data.In this way, by consistency system interconnection unit, CPU and can add when needing to be implemented consistency treatment
Fast device etc. completes consistency treatment jointly, to effectively reduce the expense of CPU maintenance cache consistency, is substantially improved at message
The speed of reason.
In a kind of implementation, the accelerator to consistency system interconnection unit send consistency write request it
Afterwards, before the CPU reads corresponding data from memory, the corresponding data of the consistency write request can also confirmed not in institute
When stating the caching of CPU, memory is written in the corresponding data that the consistency interconnection directly sends accelerator.
In the present embodiment, the corresponding data of above-mentioned consistency write request is message.
In the present embodiment, consistency system interconnection unit confirm the consistency write request corresponding data whether
The mode of the cache of the CPU can there are many kinds of.For example, consistency system interconnection unit can pass through therein
Snoop filter inquiry corresponding data whether in the cache of CPU.Wherein, Snoop filter is for recording CPU
Data mode in cache, can by inquiry CPU cache in data mode confirm corresponding data whether CPU cache
In.Certainly, in other implementations, whether consistency system interconnection unit can confirm corresponding data by other means
In the cache of the CPU, specific confirmation process and validation testing can be adjusted according to the difference of actual scene.
In practical application, the above-mentioned message processing method of the present embodiment can be realized by calculating equipment.The calculating equipment can
To be any kind of equipment for executing the present embodiment above method step, which includes at least above-mentioned CPU, interior
It deposits, accelerator, the system bus for supporting consistency treatment.It is integrated for example, the calculating equipment can be embodied as (but being not limited to)
Circuit catv terminal, for example, ONU, interchanger, WIFI router etc. can be presented as.
Embodiment two
A kind of method of Message processing, as shown in Fig. 2, may include:
Step 201, accelerator sends consistency read request to consistency system interconnection unit；
Step 202, the consistency system interconnection unit confirm the consistency read request corresponding data whether
Consistency treatment is executed in the caching of the CPU in the corresponding data of the caching of the CPU, the consistency read request；
Step 203, after completing the consistency treatment, accelerator obtains corresponding data.
In the present embodiment, accelerator need by local data transfer to external equipment (namely CPU need to accelerator insert
When entering data), corresponding consistency treatment can be completed jointly by CPU and consistency system interconnection unit, compared to
Processing message process in the related technology, can achieve the effect of transparent processing message, save CPU maintenance cache consistency
Expense, effectively improve the speed of Message processing.
In the present embodiment, (MMU, the Memory Management of memory management unit in CPU can be preset
Unit memory attribute), the memory attribute can be set as: accelerator and CPU have the shared drive buffer area of data interaction (to compare
Such as, the region in cache or memory) it is set as that (shareable) (indicating that CPU and accelerator may have access to the region) can be shared
Or (cacheable) (indicating that CPU can be by cache buffer memory data) can be buffered.Meanwhile setting descriptor team in accelerator
It is set inside column, the memory attribute of message and the MMU consistent.So, it can be ensured that at least partly region in cache and DDR
It is that accelerator and CPU can be accessed.
In the present embodiment, it can judge whether to need to be implemented consistency treatment according to the memory attribute of corresponding data；It is needing
When executing consistency treatment, accelerator sends consistency read request to consistency system interconnection unit.
In a kind of implementation, the corresponding data of the consistency read request executes consistency in the caching of the CPU
Processing may include: to confirm the corresponding data of the consistency read request in the caching of the CPU, and consistency system interconnects
Bus unit sends consistency read request to the CPU, and the corresponding data in the caching is passed through the consistency by the CPU
System interconnection unit returns to accelerator.In this way, can be interconnected by consistency system total when needing to be implemented consistency treatment
Line unit, CPU and accelerator etc. complete consistency treatment jointly, to effectively reduce opening for CPU maintenance cache consistency
Pin, is substantially improved the speed of Message processing.
In another implementation, the accelerator to consistency system interconnection unit send consistency read request it
Afterwards, before the accelerator obtains corresponding data, confirm the corresponding data of the consistency read request not in the caching of the CPU
When, the consistency read request that the accelerator is sent can be sent to memory by the consistency interconnection, accelerator from
Corresponding data is obtained in the memory.
In the present embodiment, the consistency read request can be the consistency read request of descriptor, and the consistency reading is asked
The corresponding data asked is descriptor；And/or the consistency read request can be the consistency read request of message, it is described consistent
Property read request corresponding data be message.Here, when the corresponding data that the accelerator obtains is descriptor, the accelerator
Further according to the insertion message address provided in the descriptor, continues the consistency read request for sending corresponding message and obtain corresponding
Message.
In practical application, queue number, descriptor offset etc. actively can be supplied to accelerator by CPU, accelerator according to
The two information can get descriptor, then according to descriptor acquiring to message.Accelerator obtains descriptor and message
Process be the present embodiment above method realization process.
In practical application, the above-mentioned message processing method of the present embodiment can be realized by calculating equipment.The calculating equipment can
To be any kind of equipment for executing the present embodiment above method step, which includes at least above-mentioned CPU, interior
It deposits, accelerator, the system bus for supporting consistency treatment.The calculating includes at least above-mentioned CPU, memory, accelerator, supports one
The system bus of cause property processing.For example, the calculating equipment can be embodied as (but being not limited to) integrated circuit catv terminal, example
Such as, ONU, interchanger, WIFI router etc. can be presented as.Embodiment three
A kind of device of Message processing, as shown in Figure 3, comprising: accelerator 31, consistency system interconnection unit 32,
CPU33；Wherein,
The accelerator 31, including consistency request control unit 311 and write-read DCU data control unit 312, it is described consistent
Property request control unit 311 be used for consistency system interconnection unit 32 send consistency write request；Alternatively, being used for one
Cause property system interconnection unit 32 sends consistency read request；The write-read DCU data control unit 312, for obtaining described one
The corresponding data of cause property read request；
The consistency system interconnection unit 32, for confirm the consistency write request corresponding data whether
The caching of the CPU 33, it is total with the CPU 33 when the corresponding data of the consistency write request is in the caching of the CPU
With execution consistency treatment；Alternatively, for confirming the corresponding data of the consistency read request whether in the slow of the CPU 33
When depositing, executed jointly unanimously when the corresponding data of the consistency read request is in the caching of the CPU 33 with the CPU 33
Property processing；
The CPU 33, for reading the phase of the consistency write request from memory after completing the consistency treatment
Answer data.
In a kind of implementation, accelerator 31 can also include: queue number memory attribute mapping register table, the team
Row number memory attribute mapping register table preserves the memory attribute of the data；The consistency requests control unit 311, tool
Body can be used for the memory attribute of the data according to the queue number memory attribute mapping register table, judge whether to need to hold
Row consistency treatment；When needing to be implemented consistency treatment, writes and ask to the transmission of consistency system interconnection unit 32 consistency
It asks or consistency read request.
In a kind of implementation, the consistency system interconnection unit 32 is particularly used in the confirmation consistency
When the corresponding data of write request is present in the caching of the CPU 33, consistency write request is sent to the CPU 33, will be come from
The corresponding data that the CPU 33 is cached is written back into memory, in the corresponding data write-in for later again sending the accelerator
It deposits；The CPU 33, it may also be used for when receiving the consistency write request that the consistency system interconnection unit 32 is sent,
The corresponding data of consistency write request described in caching is sent to the consistency system interconnection unit 32, so as to write-back
Enter memory；The write-read DCU data control unit 312, it may also be used for be sent to the corresponding data of the consistency write request described
Consistency system interconnection unit 32, so that memory is written.
Here, the consistency system interconnection unit 32, it may also be used in the phase for confirming the consistency write request
Answer data not in the caching of the CPU 33, memory is written in the corresponding data for directly sending accelerator 31.
In another implementation, it is described consistent to be particularly used in confirmation for the consistency system interconnection unit 32
Property read request corresponding data in the caching of the CPU 33, consistency read request is sent to the CPU 33, described in reception
The corresponding data of the transmission of CPU 33 simultaneously returns to accelerator 31；The CPU 33, it may also be used for receiving the consistency system
When the consistency read request that interconnection unit 32 is sent, the corresponding data of consistency read request described in caching is sent to institute
Consistency system interconnection unit 32 is stated, so that the consistency system interconnection unit 32 returns to accelerator 31；Institute
The write-read DCU data control unit 312 for stating accelerator 31 is particularly used in and receives the hair of consistency system interconnection unit 32
The corresponding data sent.
Here, the consistency system interconnection unit 32 is particularly used in the phase for confirming the consistency read request
It answers data not in the caching of the CPU, the consistency read request that the accelerator 31 is sent directly is sent to memory, and
Corresponding data from the memory, the described consistency read request is returned into accelerator 31；The write-read data control is single
Member 312 is particularly used in and receives the corresponding data that the consistency system interconnection unit 32 is sent.
In the present embodiment, the consistency read request is the consistency read request of descriptor, the consistency read request
Corresponding data is descriptor；And/or the consistency read request is the consistency read request of message, the consistency read request
Corresponding data be message.The corresponding data of the consistency write request can be message and descriptor.
The above-mentioned message process device of the present embodiment can realize all details of two the method for embodiment one and embodiment.
The above-mentioned message process device of the present embodiment can be by accelerator, CPU and consistency system interconnection unit come common
Corresponding consistency treatment is completed, can achieve the effect of transparent processing message, saves opening for CPU maintenance cache consistency
Pin, effectively improves the speed of Message processing.
In practical application, the above-mentioned message process device of the present embodiment be can be set in calculating equipment, or can be with body
It is now the calculating equipment, which can be any kind of equipment for executing the above-mentioned function of the present embodiment.Than
Such as, which can be embodied as (but being not limited to) integrated circuit catv terminal, for example, ONU, exchange can be presented as
Machine, WIFI router etc..
The illustrative examples of technology disclosed herein are provided below.It should be noted that the realization side of example described below
Formula can any combination, can also be individually performed.
Example 1
This example is a kind of exemplary structure of message process device described above, which is foregoing embodiments
A kind of example implementations of message process device in three.It, can according to actual needs or concrete application scene in practical application
Different adjustment message process devices a kind of hardware configuration or software configuration.For example, can be in structure shown in this example
CPU, accelerator, consistency system interconnection unit, increase other functional units in DDR, it can also be shown in this example
Increase other hardware in structure, for example, coprocessor, memory etc. can be increased, the configurable storage processing of the memory
The readable computer program of device, the coprocessor are connect with the processor, memory, and coprocessor can coprocessor execution
Some processing.
As shown in figure 4, message process device includes: CPU, DDR, accelerator and the interconnection of consistency system in this example
Bus unit, wherein CPU, DDR and accelerator are connected by the consistency system interconnection unit, include in CPU
cache。
In this example, accelerator can be any kind of acceleration for being able to carry out function described in hereinbefore embodiment
Device.The effect of the accelerator includes but is not limited to by data (such as message) write-in memory, the CPU from local from external equipment
Data (such as message and descriptor) is read in cache or DDR and is transferred to external equipment.In practical application, which can lead to
Cross diversified forms realization.For example, accelerator can be presented as the message process unit of ONU equipment, WIFI processing unit etc..
As shown in figure 4, accelerator may include: register (not shown), system bus interface control module, queue pipe
Manage unit, message First Input First Output (FIFO), descriptor FIFO etc..Wherein, queue number memory attribute is preserved in register
Mapping register table.System bus interface control module includes: consistency request control unit and write-read DCU data control unit.One
Cause property request control unit is responsible for realizing the relevant function of consistency treatment, and write-read DCU data control unit is responsible for realizing writing for data
It reads, for example, the message for needing to be transferred to external equipment is inserted into message FIFO or needs to be written the message of DDR from message
It is read in FIFO.Wherein, message FIFO includes two-way, is the message for needing to be transferred to external equipment all the way, and another way is desirable
The message of DDR is written.Queue management unit is calculated for message descriptor, other requests or insertion message request based on input
Descriptor queue number, group bias internal amount etc., and descriptor to be processed is put into descriptor FIFO.
In this example, consistency system interconnection unit can be able to carry out hereinbefore function any kind of
Bus, that is to say, that be the system bus for supporting consistency treatment.For example, can be support consistency in a kind of implementation
The ACE bus of processing.Certainly, other kinds of bus also can be used in other implementations.Here, consistency treatment function
It is to refer to complete the function in hereinbefore embodiment with consistency treatment correlation step.
In this example, consistency system interconnection unit may include: snoop filter (Snoop filter).
Snoop filter is used to record the data mode in CPU cache, and can be used for inquiring one or more messages or descriptor
Whether in the cache of CPU.For example, Snoop filter can record the state of each cacheline by tag line,
In tag line label have whether idle and its message information (memory address of such as message).
In this example, processor can be any kind of processing for being able to carry out function described in hereinbefore embodiment
Device.For example, processor can be single or multi-core processor, digital signal processor, microprocessor or other processors or place
Reason/control circuit.In some implementations, message process device may include one or more processor.
In this example, pass through different queue storing data (message and its descriptor) in memory (DDR).As shown in figure 3, interior
Deposit in (DDR) comprising queue 0, queue 1 ..., queue N, Desc_0, Desc_1 ..., Desc_n-1, Desc_n for description
Accord with field, Databuf_0, Databuf_1 ..., Databuf_n-1, Databuf_n indicate message content.It is wrapped in descriptor
Essential information containing Databuf, such as address, the information such as length.
In this example, memory (DDR) can be random access memory (RAM), dynamic random access memory (DRAM)
Etc. forms.
Example 2
This example is a kind of exemplary realization process of Message processing processing method described in foregoing embodiments one.This example is logical
The message process device crossed in example 1 is realized.
In this example, in message process device shown in Fig. 4, it can be preset in CPU and be stored by way of software
The memory attribute of device administrative unit (MMU, Memory Management Unit), the memory attribute can be set as: accelerator
There is the shared drive buffer area (for example, region in memory) of data interaction to be set as that (shareable) (table can be shared with CPU
Show CPU and accelerator all and may have access to the region) or can buffer (cacheable) (indicate CPU can be by cache buffer memory number
According to).In addition, can also similarly set the queue number memory attribute mapping register of register in accelerator by way of software
It is set inside table, i.e. setting descriptor queue, the memory attribute of message and the MMU consistent.According to the type of message, length
Equal information settings message matching rule, extracts legal message.So, it can be ensured that at least partly region is to add in DDR
What fast device and CPU can be accessed.
In practical application, can also by way of software according to information such as the type of message, length in the queue number
Its message matching rule is set in memory attribute mapping register table, so that accelerator can be identified according to the message matching rule
Whether message needs CPU to handle, and corresponding queue is added it to when CPU being needed to handle and (is added by distribution queue number
Queue).
For needing to submit to the message of CPU processing, message descriptor passes through the queue management unit of accelerator, accelerator
Queue management unit distribution descriptor queue number, descriptor team's bias internal amount and the information such as message buffering regional address and add
Enter descriptor.In the system bus interface control module of accelerator, asked according to queue number memory attribute mapping table control consistency
Control unit is sought, the memory address of descriptor is calculated by queue number and team's bias internal amount, the message provided according to descriptor is slow
It rushes regional address and obtains the memory address of message, system bus interface control module is to system bus (that is, the interconnection of consistency system is total
Line unit) issue consistency write request.As shown in figure 1 shown in a of path, the prison of consistency system interconnection unit first internally
It listens filter (Snoop filter) (for recording data mode in CPU cache) to initiate inquiry, confirms that the consistency is write
Request the data of corresponding address whether in CPU cache.If the data of address corresponding to the consistency write request are
In CPU cache, as shown in figure 1 shown in the b of path, consistency system interconnection unit, which continues to write to CPU initiation consistency, is asked
It asks, execute process shown in path c and path d as shown in figure 1: CPU is (e.g., for safeguarding the functional unit of consistency (in Fig. 3 in CPU
It is not shown)) corresponding data (e.g., message) in cache is written back to by DDR by consistency system interconnection unit, then,
As shown in figure 1 shown in the e of path, consistency system interconnection unit is by accelerator (e.g., the write-read DCU data control unit of accelerator)
The data of writing sent are write in DDR；If the data of address corresponding to the consistency write request are not in CPU cache
In, the data of writing that consistency interconnection sends accelerator are written directly in memory (DDR).During this, complete
Memory consistency treatment.Accelerator interrupt notification CPU handles message, at this point, the software of CPU can directly pass through consistency system
Interconnection unit reads the descriptor and message and is handled from DDR.
Example 3
This example is a kind of exemplary realization process of Message processing processing method described in foregoing embodiments two.This example is logical
The message process device crossed in example 1 is realized.
In this example, in message process device shown in Fig. 4, it can be preset in CPU and be stored by way of software
The memory attribute of device administrative unit (MMU, Memory Management Unit), the memory attribute can be set as: accelerator
There is the shared drive buffer area (for example, region in cache or memory) of data interaction to be set as to share with CPU
(shareable) it (indicate CPU and accelerator all may have access to the region) or (cacheable) can be buffered (indicates that CPU can pass through
Cache buffer memory data).In addition, can also similarly set the queue number memory of register in accelerator by way of software
It is set inside attribute mapping register table, i.e. setting descriptor queue, the memory attribute of message and the MMU consistent.
When CPU needs to be inserted into data to accelerator, the descriptor and message that the software of CPU will be inserted into are write in cache,
By the descriptor queue number of insertion, team's bias internal amount notifies accelerator to read.Accelerator is mapped according to queue number memory attribute
Consistency in register table control system bus interface control module requests control unit, passes through queue number and team's bias internal amount
The memory address of descriptor is calculated, system bus interface control module is to system bus (that is, consistency system interconnection list
Member) issue consistency reading descriptor request.The Snoop filter of consistency system interconnection unit first internally is initiated
Inquiry confirms that the consistency reads descriptor and requests requested descriptor whether in the cache of CPU.
If the descriptor is in the cache of CPU, consistency system interconnection unit continues to initiate to CPU
Consistency reads descriptor request (type of the request can be snoop request), and CPU is (for example, for safeguarding consistency in CPU
Functional unit) descriptor in cache returned into consistency system interconnection unit, by consistency system interconnection
Descriptor is returned to accelerator again by unit.
Request requested descriptor not in the cache of CPU if the consistency reads descriptor, consistency system
The consistency descriptor message request that accelerator is sent is transmitted directly to DDR by interconnection unit, from DDR described in acquisition
Descriptor.
After accelerator obtains descriptor, according to the insertion message address provided in the descriptor, continue to system bus
(that is, consistency system interconnection unit) issue consistency read message request, consistency system interconnection unit first to
Internal Snoop filter initiates inquiry, confirms that whether the consistency reads the requested message of message request CPU's
In cache, if the message is in the cache of CPU, consistency system interconnection unit continues to initiate one to CPU
Cause property reads message request (type of the request can be snoop request), and CPU is (for example, for safeguarding the function of consistency in CPU
Can unit) the corresponding message in cache returned into consistency system interconnection unit, by consistency system interconnection list
The message is returned to accelerator (for example, write-read DCU data control unit of accelerator) again by member.That is, accelerator from
Message is obtained in CPU cache.
If the consistency reads the requested message of message request not in the cache of CPU, the interconnection of consistency system
The consistency that accelerator is sent is read message request and is transmitted directly to DDR by bus unit, and DDR returns to corresponding message unanimously
Property system interconnection unit, by consistency system interconnection unit again by the message return to accelerator (for example, accelerate
The write-read DCU data control unit of device), that is to say, that accelerator obtains message from DDR.
In the above process, memory consistency treatment is completed.After memory consistency treatment is completed, the system of accelerator is total
Line interface control module gives built-in message the message obtained from bus (e.g., consistency system interconnection unit)
FIFO completes message insertion operation.
Example 4
This example includes Message processing process when CPU needs to extract data, which is message in foregoing embodiments one
A kind of example implementations of processing method.In practical application, other embodiments can also be used.For example, can be at this
Increase other steps in example process, or according to actual needs or the difference of concrete application scene adjusts certain steps in this process
Rapid executes sequence.
As shown in figure 5, Message processing process when CPU needs to extract data in this example, may include:
Step 401, CPU provides the descriptor that need to extract message, and the descriptor of the message is inputted itself by accelerator；
Step 402, the queue management unit of accelerator be the descriptor distribution queue ID of the message, team's bias internal amount,
Message buffering regional address etc.；
Step 403, descriptor is pressed into descriptor FIFO by queue management module；
Step 404, the system bus interface control module of accelerator obtains memory attribute according to queue ID, according to inclined in team
The memory address of shifting amount acquisition descriptor；
Step 405, memory is written in descriptor by accelerator；
Specifically, the write-read DCU data control unit of system bus interface control module is mutual by consistency system in accelerator
Join bus unit and memory is written into the descriptor.
Step 406, according to the message buffering regional address inside descriptor, accelerator is to consistency system interconnection unit
Memory is written in message in message FIFO by request；
Specifically, the consistency of system bus interface control module requests control unit to the consistency system in accelerator
System interconnection unit sends the consistency write request of the message.
Step 407, consistency system bus judges whether to need consistency treatment according to the consistency write request of accelerator,
And consistency treatment is executed when needed；
Specifically, whether consistency system interconnection unit confirms the message in the cache of CPU；If described
For message in the cache of CPU, consistency system interconnection unit sends the consistency write request of the descriptor to CPU,
Message in cache is written back into memory by consistency system interconnection unit by CPU, subsequently into step 408, consistency
Memory is written in the message that system interconnection unit again provides accelerator, in this way, in memory will be in CPU cache
The message that message is newly provided with accelerator covers, so that the message in memory is latest value, while message described in CPU cache
Corresponding cacheline be deactivated, become idle state, to complete consistency treatment.If the descriptor is not CPU's
In cache, does not then need to execute consistency treatment, be directly entered step 408, consistency system interconnection unit can be direct
Memory is written in the message that accelerator is provided.
In practical application, for not needing the message of CPU processing, when being buffered to DDR, respective request is if it is nonuniformity
, then the nonconforming request does not need snoopfilter inquiry.That is, being directed to nonconforming request
This step can not be executed, in this way, can avoid the performance for reducing system bus because frequently inquiring, and then avoids reducing CPU
Performance.
Step 408, memory is written into the message in accelerator message FIFO；
Step 409, accelerator interrupt notification CPU handles message；
Step 410, the software of CPU is handled in the interrupt service program, is completed message and is extracted.
In practical application, accelerator is handled by interrupt notification CPU, after CPU receives interrupt notification, executes corresponding interruption
Service routine completes the processing of corresponding event in interrupt service routine.
Example 5
This example includes Message processing process when CPU needs to extract data, which is message in foregoing embodiments one
A kind of example implementations of processing method.In practical application, other embodiments can also be used.For example, can be at this
Increase other steps in example process, or according to actual needs or the difference of concrete application scene adjusts certain steps in this process
Rapid executes sequence.
As shown in fig. 6, Message processing process may include: in this example
Step 501, cache is written in descriptor and message by the software of CPU；
Step 502, the software notification accelerator of CPU is inserted into message request, in queue ID, team including message to be inserted into partially
Shifting amount；
Step 503, the descriptor is inserted into FIFO by the queue management unit of accelerator；
Step 504, descriptor is pressed into descriptor FIFO by queue management module；
Step 505, memory attribute is obtained according to queue ID in the system bus interface control module of accelerator, according in team
The memory address of offset acquisition descriptor；
Step 506, the consistency of accelerator requests control unit to be retouched to the reading of consistency system interconnection unit requests
State symbol；
Specifically, the consistency of accelerator requests control unit to send descriptor to consistency system interconnection unit
Consistency read request；Whether consistency system interconnection unit confirms the descriptor in the cache of CPU；If described
For descriptor in the cache of CPU, consistency system interconnection unit sends the consistency read request of the descriptor to CPU,
The descriptor in cache is sent to accelerator by consistency system interconnection unit by CPU；If the descriptor is not
In the cache of CPU, consistency system interconnection unit sends the consistency read request of the descriptor to memory, by interior
It deposits and the descriptor is sent to accelerator by consistency system interconnection unit.
From step 507, according to the message buffering address inside the descriptor to read back, continue to consistency system interconnection
Unit requests read message；
Specifically, the consistency request control unit of system bus interface control module is according to the description read back in accelerator
The consistency read request that message is sent to consistency system interconnection unit is continued in the message buffering address for according with the inside.
Step 508, consistency system interconnection unit judges whether needs one according to the consistency read request of accelerator
The processing of cause property, and consistency treatment is executed when needed；
Step 509, after the completion of consistency treatment, the write-read DCU data control unit of accelerator is read from cache or memory
To message；
In step 508 and step 509, consistency system interconnection unit confirm the message whether CPU cache
In, if the message, in the cache of CPU, consistency system interconnection unit sends the consistency of the message to CPU
The message in cache is sent to accelerator by consistency system interconnection unit by CPU by read request.If institute
Message is stated not in the cache of CPU, consistency system interconnection unit is asked to the consistency reading that memory sends the message
It asks, the message is sent to accelerator by consistency system interconnection unit by memory.
Step 510, message is returned to the message FIFO of accelerator by the write-read DCU data control unit of accelerator；
Step 511, accelerator completes message insertion.
Example 6
The application can be applied to optical network unit (ONU, Optical Network Unit) or other similar equipment.
In practical application, device described above can be set in ONU, can accelerate to complete by multiple accelerators
ONU area protocol message is (for example, the bridge tube of Ethernet manages address protocol (GMVP)；Address resolution protocol (ARP)；Internet
Internet Control Message Protocol (ICMP) etc.) processing and WIFI message (for example, 802.11a/b/g/n/11ac protocol massages) with
The too efficiency of network packet (for example, 802.3 protocol massages) conversion.
In a kind of implementation, above each embodiment and each example can be applied to the processing of ONU protocol massages.Pass through acceleration
Device can make CPU handle the process of message under such scene faster, while also less occupancy cpu resource.For example, the report of ONU
Literary processing unit gives the protocol massages that hardware can not be handled to CPU by accelerator unit, is inserted into message after CPU processing
Processing unit.
In a kind of implementation, above each embodiment and each example can be applied to ONU WIFI forwarding service.Accelerator
CPU can be made to handle the process of message under such scene faster, while also less occupancy cpu resource.For example, the ether of ONU
Memory is written by the message that accelerator will be forwarded to WIFI processing unit in network packet processing unit, and CPU is to protocol conversion process
Afterwards, WIFI processing unit reads message by accelerator unit；Alternatively, WIFI processing unit by accelerator unit be issued to
Too memory is written in the message of network packet processing unit, and after CPU is to protocol conversion process, Ethernet message process unit passes through acceleration
Device unit reads message.
It should be noted that core buffer self-administered for accelerator can be by soft in above-mentioned each example
Part mode sets the memory attribute of corresponding MMU as that can not share (unshareable), can not cache (uncacheable)；Software
The memory attribute for setting accelerator internal description symbol queue and message is consistent with the setting of the inside MMU.Accelerator oneself is managed
The queue read-write requests of reason, the system bus interface control module of accelerator are total to system according to the memory attribute for reading and writing queue
Line (e.g., consistency system interconnection unit) issues common read-write requests, and consistency system interconnection unit will receive
To read-write requests be directly passed to DDR, complete read-write operation.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware (such as processor) is completed, and described program can store in computer readable storage medium, as read-only memory,
Disk or CD etc..Optionally, one or more integrated circuits also can be used in all or part of the steps of above-described embodiment
It realizes.Correspondingly, each module/unit in above-described embodiment can take the form of hardware realization, such as pass through integrated circuit
It realizes its corresponding function, can also be realized in the form of software function module, such as be stored in and deposited by processor execution
Program/instruction in reservoir realizes its corresponding function.The application is not limited to the knot of the hardware and software of any particular form
It closes.
The advantages of basic principles and main features and the application of the application have been shown and described above.The application is not by upper
The limitation for stating embodiment, the above embodiments and description only describe the principles of the application, are not departing from the application
Under the premise of spirit and scope, the application be will also have various changes and improvements, these changes and improvements both fall within claimed
Within the scope of the application.
Claims (18)
1. a kind of method of Message processing, comprising:
Accelerator sends consistency write request to consistency system interconnection unit；
Whether the consistency system interconnection unit confirms the corresponding data of the consistency write request in the slow of the CPU
It deposits, the corresponding data of the consistency write request executes consistency treatment in the caching of the CPU；
After completing the consistency treatment, the CPU reads corresponding data from memory.
2. the method according to claim 1, wherein
The accelerator sends consistency write request to consistency system interconnection unit, comprising: according in corresponding data
Attribute is deposited, judges whether to need to be implemented consistency treatment；When needing to be implemented consistency treatment, to consistency system interconnection
Unit sends consistency write request.
3. the method according to claim 1, wherein the corresponding data of the consistency write request is in the CPU
Caching when execute consistency treatment, comprising:
Confirm the corresponding data of the consistency write request in the caching of the CPU, consistency system interconnection unit to
The CPU sends consistency write request, and the CPU passes through consistency system interconnection unit for the respective counts in the caching
According to memory is written back into, in the corresponding data write-in that the consistency system interconnection unit sends the accelerator later
It deposits.
4. the method according to claim 1, wherein the accelerator is sent out to consistency system interconnection unit
After sending consistency write request, before the CPU reads corresponding data from memory, further includes:
The corresponding data of the consistency write request is confirmed not in the caching of the CPU, and the consistency interconnection is direct
Memory is written in the corresponding data that accelerator is sent.
5. method according to any one of claims 1 to 4, which is characterized in that
The corresponding data of the consistency write request is message and descriptor.
6. a kind of method of Message processing, comprising:
Accelerator sends consistency read request to consistency system interconnection unit；
Whether the consistency system interconnection unit confirms the corresponding data of the consistency read request in the slow of the CPU
It deposits, the corresponding data of the consistency read request executes consistency treatment in the caching of the CPU；
After completing the consistency treatment, accelerator obtains corresponding data.
7. according to the method described in claim 6, it is characterized in that,
The accelerator sends consistency read request to consistency system interconnection unit, comprising: according in corresponding data
Attribute is deposited, judges whether to need to be implemented consistency treatment；When needing to be implemented consistency treatment, to consistency system interconnection
Unit sends consistency read request.
8. according to the method described in claim 6, it is characterized in that, the corresponding data of the consistency read request is in the CPU
Caching when execute consistency treatment, comprising:
Confirm the corresponding data of the consistency read request in the caching of the CPU, consistency system interconnection unit to
The CPU sends consistency read request, and the CPU interconnects the corresponding data in the caching by the consistency system total
Line unit returns to accelerator.
9. according to the method described in claim 6, it is characterized in that, the accelerator is sent out to consistency system interconnection unit
After sending consistency read request, before the accelerator obtains corresponding data, further includes:
The corresponding data of the consistency read request is confirmed not in the caching of the CPU, and the consistency interconnection is by institute
It states the consistency read request that accelerator is sent and is sent to memory, accelerator obtains corresponding data from the memory.
10. according to the described in any item methods of claim 6 to 9, which is characterized in that
The consistency read request is the consistency read request of descriptor, and the corresponding data of the consistency read request is description
Symbol；And/or
The consistency read request is the consistency read request of message, and the corresponding data of the consistency read request is message.
11. according to the method described in claim 10, it is characterized in that,
When the corresponding data that the accelerator obtains is descriptor, the accelerator is inserted further according to what is provided in the descriptor
Enter message address, continue the consistency read request for sending corresponding message and obtains corresponding message.
12. a kind of device of Message processing characterized by comprising accelerator, consistency system interconnection unit, CPU；
The accelerator, including consistency request control unit and write-read DCU data control unit, the consistency request control are single
Member is for sending consistency write request to consistency system interconnection unit；Alternatively, being used for consistency system interconnection
Unit sends consistency read request；The write-read DCU data control unit, for obtaining the corresponding data of the consistency read request；
The consistency system interconnection unit, for confirming the corresponding data of the consistency write request whether described
The caching of CPU executes unanimously when the corresponding data of the consistency write request is in the caching of the CPU with the CPU jointly
Property processing；Alternatively, for confirming the corresponding data of the consistency read request whether in the caching of the CPU, described one
The corresponding data of cause property read request executes consistency treatment with the CPU in the caching of the CPU jointly；
The CPU, for reading the corresponding data of the consistency write request from memory after completing the consistency treatment.
13. device according to claim 12, which is characterized in that
The accelerator, further includes: queue number memory attribute mapping register table, the queue number memory attribute mapping register
Table preserves the memory attribute of the data；
The consistency requests control unit, is specifically used for the number according to the queue number memory attribute mapping register table
According to memory attribute, judge whether to need to be implemented consistency treatment；It is mutual to consistency system when needing to be implemented consistency treatment
Join bus unit and sends consistency write request or consistency read request.
14. device according to claim 12, which is characterized in that
The consistency system interconnection unit, specifically for confirming that the corresponding data of the consistency write request is present in institute
When stating the caching of CPU, consistency write request is sent to the CPU, the corresponding data from the cpu cache is written back into interior
It deposits, memory is written in the corresponding data for later again sending the accelerator；
The CPU is also used to cache when receiving the consistency write request that the consistency system interconnection unit is sent
Described in the corresponding data of consistency write request be sent to the consistency system interconnection unit, to be written back into memory；
The write-read DCU data control unit is also used to the corresponding data of the consistency write request being sent to the consistency system
System interconnection unit, so that memory is written.
15. device described in 2 or 14 according to claim 1, which is characterized in that
The consistency system interconnection unit is also used to confirming the corresponding data of the consistency write request not described
When the caching of CPU, memory is written in the corresponding data for directly sending accelerator.
16. device according to claim 12, which is characterized in that
The consistency system interconnection unit, specifically for confirming the corresponding data of the consistency read request described
When the caching of CPU, consistency read request is sent to the CPU, the corresponding data that the CPU is sent is received and returns to acceleration
Device；
The CPU is also used to cache when receiving the consistency read request that the consistency system interconnection unit is sent
Described in the corresponding data of consistency read request be sent to the consistency system interconnection unit, so as to the consistency system
System interconnection unit returns to accelerator；
The write-read DCU data control unit of the accelerator, specifically for receiving the consistency system interconnection unit transmission
The corresponding data.
17. device according to claim 12, which is characterized in that
The consistency system interconnection unit, specifically for confirming the corresponding data of the consistency read request not described
When the caching of CPU, the consistency read request that the accelerator is sent directly is sent to memory, and the memory will be come from
, the corresponding data of the consistency read request return to accelerator；
The write-read DCU data control unit, specifically for receiving the described corresponding of the consistency system interconnection unit transmission
Data.
18. device described in 2,16 or 17 according to claim 1, which is characterized in that
The consistency read request is the consistency read request of descriptor, and the corresponding data of the consistency read request is description
Symbol；And/or
The consistency read request is the consistency read request of message, and the corresponding data of the consistency read request is message.
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