CN109558344A - A kind of DMA transfer method and dma controller suitable for network transmission - Google Patents
A kind of DMA transfer method and dma controller suitable for network transmission Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
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Abstract
The invention discloses a kind of DMA transfer methods and dma controller suitable for network transmission.For Write DMA, the address for the memory space that host side is reserved is sequentially written in the FIFO memory that board end is furnished with by the application in advance, descriptor can be autonomously generated according to the transmission data of the address and board end that store in FIFO memory by making the dma controller at board end, descriptor is safeguarded again without host side, to reduce the interaction times between host side and board end, Write DMA data transfer efficiency is improved, and reduces the work load of host side.For Read DMA, host side actively generates descriptor, rather than wait it is to be interrupted after regenerate descriptor again, so board end regenerates descriptor without waiting for host side, to reduce the interaction time between host side and board end, Read DMA data transfer efficiency is improved.
Description
Technical field
The present invention relates to DMA transfer fields, more particularly to a kind of DMA transfer method and DMA suitable for network transmission
Controller.
Background technique
In the prior art, the DMA under network transmission (Direct Memory Access, direct memory access) is transmitted
Including Write DMA and Read DMA.Fig. 1 is please referred to, Fig. 1 is a kind of realization principle figure of DMA transfer in the prior art.
Write DMA refers to that FPGA (Field-Programmable Gate Array, field programmable gate array) is held to host
End transmission data, Read DMA refer to that host side transmits data to the end FPGA.The end FPGA (i.e. board end) is configured with PCIE
(peripheral component interconnect express, external components high speed interconnection standards) controller, DMA control
Device and Smart NIC (Network Interface Card, network interface card) processed.
For Write DMA, (obtained by Smart NIC from exterior terminal after the data that board end is transmitted needed for being ready to
Access evidence, and data are stored to board end memory), need to inform data the depositing in board end memory that host side will be transmitted
Store up the size (interaction path: dma controller-PCIE controller-host side) of address and data.Then host side is according to this letter
Breath generates descriptor, configures board end register then to inform the storage of the dma controller descriptor in host side at board end
Descriptor is then moved into board end memory reserved descriptor memory space by dma controller by address.Dma controller
The content being successively read in descriptor memory space after having moved descriptor executes Write DMA transfer.Equal descriptors storage
After all descriptors have been carried out in space, dma controller sends interrupt signal to host side.If the number transmitted needed for board end
There is also the data that do not transmit in, needs to regenerate descriptor again and execute Write DMA transfer again, until data are complete
Portion is transmitted.
For Read DMA, host side according to the data of required transmission self EMS memory storage address and data it is big
Small and board end memory space generates descriptor, and next Read DMA transfer process is similar with Write DMA.As it can be seen that
In DMA transfer, the number interacted between host side and board end is more, and board end needs to wait for host side and regenerate to retouch every time
Symbol is stated, the time for causing the two interaction to occupy is longer, to reduce DMA transfer efficiency.
Therefore, how to provide a kind of scheme of solution above-mentioned technical problem is that those skilled in the art needs to solve at present
The problem of.
Summary of the invention
The object of the present invention is to provide a kind of DMA transfer method and dma controller suitable for network transmission, for
Write DMA, the application safeguard descriptor without host side again, to reduce the interaction time between host side and board end
Number, improves Write DMA data transfer efficiency, and reduce the work load of host side.For Read DMA, board end without
It needs to wait for host side and regenerates descriptor, to reduce the interaction time between host side and board end, improve Read
DMA data transfer efficiency.
In order to solve the above technical problems, being applied to the present invention provides a kind of DMA transfer method suitable for network transmission
The direct memory access dma controller of board end configuration, comprising:
Before Write DMA transfer, the address for the memory space that host side is reserved is sequentially written in the board in advance
Hold the fifo fifo memory being furnished with, wherein the reserved memory space of the host side is to store the board end
Transmit the reserved space of data；
When preparing Write DMA transfer, according to the biography of the address and the board end that are stored in the FIFO memory
The storage address and size of data of transmission of data are autonomously generated descriptor, and the descriptor stored and is reserved to the board end
Descriptor memory space, to execute Write DMA transfer；
When preparing Read DMA transfer, according to the board end register information that the host side configures, the master is obtained
The storage address for the descriptor that generator terminal is actively generated according to board end memory space；
According to the storage address for the descriptor that the host side actively generates, from the host side by descriptor move to
The reserved descriptor memory space in the board end, to execute Read DMA transfer.
Preferably, the storage of the transmission data according to the address stored in the FIFO memory and the board end
Address and size of data are autonomously generated descriptor, and the descriptor is stored to the descriptor reserved to the board end and stores sky
Between, to execute Write DMA transfer, comprising:
Transmission address is configured in order for the network message in the transmission data at the board end, wherein the transmission address
For the address successively selected from the address that the FIFO memory stores；
For be not configured network message configuration transmission address while, according to configured network message in the board
Storage address, size of data and its corresponding transmission address at end are autonomously generated descriptor, and the descriptor is successively stored
The descriptor memory space reserved to the board end；
While the descriptor that storage has just generated, Write DMA transfer is executed according to stored descriptor.
Preferably, the DMA transfer method further include:
The multiple groups queue-type that the descriptor memory space that the board end is reserved is divided into different priorities is stored in advance empty
Between；Wherein, it is deposited in the descriptor stored in the high queue-type memory space of priority the queue-type memory space lower than priority
The descriptor of storage is preferentially read；
Then the network message in the transmission data for the board end configures in order transmission address, comprising:
According to the priority of the network message in the transmission data at the board end, it is followed successively by the network message configuration and passes
Defeated address；Wherein, the high network message of the priority network message lower than priority preferentially configures, and board end network message
Priority class is identical as the priority class of the queue-type memory space；
It is described that the descriptor is successively stored to the descriptor memory space reserved to the board end, comprising:
The descriptor is stored according to priority class belonging to its corresponding network message to the queue of the same category
Formula memory space.
Preferably, the storage address of the descriptor actively generated according to the host side, will from the host side
Descriptor moves the descriptor memory space reserved to the board end, to execute Read DMA transfer, comprising:
While the host side configures board end register information, the description that has been actively generated according to the host side
Descriptor is successively moved the descriptor memory space reserved to the board end by the storage address of symbol from the host side；
While moving newly-generated descriptor from the host side, Read is executed according to stored descriptor
DMA transfer.
Preferably, any descriptor that the host side actively generates includes: one in the transmission data of the host side
The institute that network message will be transmitted in the storage address of the host side, the size of data of the network message and the network message
State the memory address at board end.
Preferably, the DMA transfer method further include:
The multiple groups queue-type that the descriptor memory space that the board end is reserved is divided into different priorities is stored in advance empty
Between, wherein the priority class of the queue-type memory space is identical as the priority class of host side network message, and preferential
The descriptor stored in the descriptor stored in the high queue-type memory space of grade the queue-type memory space lower than priority is excellent
First read；
It is described that descriptor is successively moved to the descriptor memory space reserved to the board end, packet from the host side
It includes:
By descriptor according to priority class belonging to its corresponding network message from the host side, successively move to
The queue-type memory space of the same category.
In order to solve the above technical problems, the present invention also provides a kind of dma controllers suitable for network transmission, comprising:
Pre-write module, for before Write DMA transfer, the address of the memory space in advance reserving host side according to
The fifo fifo memory that the secondary write-in board end is furnished with, wherein the reserved memory space of the host side is to deposit
Store up the reserved space of the transmission data at the board end；
WDMA module is used for when preparing Write DMA transfer, according to the address and institute stored in the FIFO memory
The storage address and size of data for stating the transmission data at board end are autonomously generated descriptor, and the descriptor is stored to described
The reserved descriptor memory space in board end, to execute Write DMA transfer；
Address acquisition module, for being deposited according to the board end of host side configuration when preparing Read DMA transfer
Device information obtains the storage address for the descriptor that the host side is actively generated according to board end memory space；
RDMA module, the storage address of the descriptor for being actively generated according to the host side, from the host side
Descriptor is moved to the descriptor memory space reserved to the board end, to execute Read DMA transfer.
Preferably, the WDMA module includes:
Address configuration unit, for when preparing Write DMA transfer, being the network in the transmission data at the board end
Message configures in order transmission address, wherein the transmission address is successively to select from the address that the FIFO memory stores
Address；
First descriptor generation unit, for for be not configured network message configuration transmission address while, according to
The network message of configuration is autonomously generated description in the storage address at the board end, size of data and its corresponding transmission address
Symbol, and the descriptor is successively stored to the descriptor memory space reserved to the board end；
First execution unit, for being executed according to stored descriptor while storing the descriptor just generated
Write DMA transfer.
Preferably, the dma controller further include:
Priority presetting module, for the descriptor memory space that the board end is reserved to be divided into different priorities in advance
Multiple groups queue-type memory space；Wherein, the descriptor stored in the high queue-type memory space of priority is lower than priority
The descriptor stored in queue-type memory space is preferentially read；
Then the network message in the transmission data for the board end configures in order transmission address, comprising:
According to the priority of the network message in the transmission data at the board end, it is followed successively by the network message configuration and passes
Defeated address；Wherein, the high network message of the priority network message lower than priority preferentially configures, and board end network message
Priority class is identical as the priority class of the queue-type memory space；
It is described that the descriptor is successively stored to the descriptor memory space reserved to the board end, comprising:
The descriptor is stored according to priority class belonging to its corresponding network message to the queue of the same category
Formula memory space.
Preferably, the RDMA module includes:
Second descriptor generation unit is used for while the host side configures board end register information, according to institute
The storage address for stating the descriptor that host side has actively generated successively moves descriptor to the board from the host side
The reserved descriptor memory space in end；
Second execution unit, for while moving newly-generated descriptor from the host side, according to having stored
Descriptor execute Read DMA transfer.
The present invention provides a kind of DMA transfer methods suitable for network transmission, the DMA control applied to the configuration of board end
Device, comprising: before Write DMA transfer, the address for the memory space that host side is reserved is sequentially written in board end in advance and is matched
Some FIFO memories, wherein the reserved memory space of host side is to store the reserved space of the transmission data at board end；When
When preparing Write DMA transfer, according to the storage address of the transmission data of the address and board end that are stored in FIFO memory and
Size of data is autonomously generated descriptor, and descriptor is stored to the descriptor memory space reserved to board end, to execute Write
DMA transfer；When preparing Read DMA transfer, according to host side configure board end register information, obtain host side according to
The storage address for the descriptor that board end memory space actively generates；The storage of the descriptor actively generated according to host side
Descriptor is moved the descriptor memory space reserved to board end, from host side to execute Read DMA transfer by location.
As it can be seen that the address for the memory space that host side is reserved is sequentially written in board in advance by the application for Write DMA
It holds in the FIFO memory being furnished with, makes the dma controller at board end can be according to the address and board end stored in FIFO memory
Transmission data be autonomously generated descriptor, descriptor is safeguarded again without host side, to reduce between host side and board end
Interaction times, improve Write DMA data transfer efficiency, and reduce the work load of host side.For Read DMA,
Host side actively generates descriptor, rather than wait it is to be interrupted after regenerate descriptor again, so board end is without waiting for host
End regenerates descriptor, to reduce the interaction time between host side and board end, improves Read DMA data biography
Defeated efficiency.
The present invention also provides a kind of dma controllers suitable for network transmission, with above-mentioned beneficial effect having the same.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of realization principle figure of DMA transfer in the prior art；
Fig. 2 is a kind of flow chart of the DMA transfer method suitable for network transmission provided by the invention；
Fig. 3 is a kind of realization principle figure of DMA transfer provided by the invention；
Fig. 4 is a kind of structural schematic diagram of the dma controller suitable for network transmission provided by the invention.
Specific embodiment
Core of the invention is to provide a kind of DMA transfer method and dma controller suitable for network transmission, for
Write DMA, the application safeguard descriptor without host side again, to reduce the interaction time between host side and board end
Number, improves Write DMA data transfer efficiency, and reduce the work load of host side.For Read DMA, board end without
It needs to wait for host side and regenerates descriptor, to reduce the interaction time between host side and board end, improve Read
DMA data transfer efficiency.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to figure 2., Fig. 2 is a kind of flow chart of the DMA transfer method suitable for network transmission provided by the invention.
This is suitable for the DMA transfer method of network transmission, the dma controller applied to the configuration of board end, comprising:
Step S11: before Write DMA transfer, the address for the memory space that host side is reserved is sequentially written in advance
The FIFO memory that board end is furnished with, wherein the reserved memory space of host side is reserved to store the transmission data at board end
Space.
Specifically, Write DMA refers to that data are transmitted to host side in board end, so host side should reserve a part of storage
Space, for store board end transmission data (transmission data here refer to that board end will be transmitted to the data of host side,
It is stored in the memory at board end).Based on this, before Write DMA transfer, the application is first deposited what host side was reserved in advance
The address in storage space is sequentially written in FIFO (First Input First Output, the first in first out) storage being furnished at board end
Device.That is, the dma controller of board end configuration can obtain the reserved memory space of host side by reading FIFO memory
Address.
It is known in DMA transfer, the corresponding network message of descriptor is (comprising several in the transmission data at board end
A network message, and new network message can be obtained at any time from Smart NIC according to transmission demand).A description of Write DMA
The main composition of symbol: target network message (i.e. board end prepares the network message transmitted) exists in the transmission data at board end
The storage address at board end, the size of data of the target network message and host side are that the target that the target network message provides is deposited
Storing up address, (after goal storage address refers to that the target network message is transmitted to host side from board end, host side is stored
The specific location of the target network message).Therefore, the address that dma controller can store FIFO memory is successively as composition
The target storage address of the descriptor of Write DMA.
Step S12: when preparing Write DMA transfer, according to the biography of the address and board end that are stored in FIFO memory
The storage address and size of data of transmission of data are autonomously generated descriptor, and descriptor is stored to the descriptor that board end is reserved and is deposited
Space is stored up, to execute Write DMA transfer.
Specifically, when preparing Write DMA transfer, dma controller successively determines mesh from the transmission data at board end
Mark network message.For each target network message in board end, dma controller is all in accordance with the target network message in board
The size of data of the storage address at end and the target network message chooses the target network from the address stored in FIFO memory
The target storage address of network message.
After the target storage address for choosing the good target network message, dma controller is according to the target network message
It is autonomous in the target storage address of the storage address at board end, the size of data of the target network message and the target network message
Generate the corresponding descriptor of target network message (can indicate in a tabular form).Also, it is the target network message is corresponding
Descriptor store to board end reserve descriptor memory space.When the Write DMA transfer for executing the target network message
When, dma controller only need to read the corresponding descriptor of target network message being autonomously generated from descriptor memory space, thus
It realizes the target network message transmissions to host side are (specific: the target network packet storage to its target storage address institute table
In the host side memory space shown).
As it can be seen that the address for the memory space that host side is reserved is sequentially written in board in advance by the application for Write DMA
It holds in the FIFO memory being furnished with, makes the dma controller at board end can be according to the address and board end stored in FIFO memory
Transmission data be autonomously generated descriptor, descriptor is safeguarded again without host side, to reduce between host side and board end
Interaction times, improve Write DMA data transfer efficiency, and reduce the work load of host side.
Step S21: when preparing Read DMA transfer, according to the board end register information that host side configures, master is obtained
The storage address for the descriptor that generator terminal is actively generated according to board end memory space.
Specifically, Read DMA refers to that host side transmits data to board end, it is known that the transmission data of host side are (here
Transmission data refer to that host side will be transmitted to the data at board end, are stored in the memory of host side) in comprising several nets
Network message, and the corresponding network message of a descriptor, so the main composition of a descriptor of Read DMA: host side
Transmit target network message in data (i.e. host side prepare transmission a network message) storage address in host side, the mesh
The size of data and board end for marking network message are target storage address (the goal storage that the target network message provides
After address refers to that the target network message is transmitted to board end from host side, board end stores the specific position of the target network message
It sets).
Before preparing Read DMA transfer, host side need to be interacted with board end to obtain board end memory space.Here
Board end memory space refer to board end be used to store host side transmission data memory headroom, thus for determination host side
The target storage address of target network message lay the foundation.
When preparing Read DMA transfer, host-side controller successively determines target network from the transmission data of host side
Message.For each target network message in host side, host-side controller is all in accordance with the target network message in host side
Storage address and the target network message size of data, the mesh of the target network message is chosen from board end memory space
Mark storage address.
After the target storage address for choosing the good target network message, host-side controller is according to the target network report
Target storage address master of the text in the storage address of host side, the size of data of the target network message and the target network message
It is dynamic generate the corresponding descriptor of target network message (actively generating here indicate host side when preparing to transmit data,
Controller is also ready for descriptor in the case where no interruption；That is, host-side controller can be at any time according to transmission demand
Prepare descriptor).
Host-side controller just configures posting for board end after actively generating the corresponding descriptor of target network message
Data are written to the register at board end in storage information, to inform that the dma controller at the board end target network message is corresponding
Descriptor host side storage address.Based on this, the register information that dma controller is configured according to host side can be obtained
Take the storage address of the corresponding descriptor of target network message.
Step S22: according to the storage address for the descriptor that host side actively generates, from host side by descriptor move to
The reserved descriptor memory space in board end, to execute Read DMA transfer.
Specifically, according to the storage address of the corresponding descriptor of target network message, dma controller can be from host side
The descriptor is moved to the descriptor memory space reserved to board end.When the Read DMA transfer for executing the target network message
When, dma controller need to only read the corresponding descriptor of target network message from descriptor memory space, to realize the mesh
Mark network message is transmitted to board end memory (specifically: the target network packet storage to its target storage address institute from host side
In the board end memory space of expression).
As it can be seen that host side actively generates descriptor for Read DMA, rather than wait it is to be interrupted after regenerate description again
Symbol, so board end regenerates descriptor without waiting for host side, to reduce the interaction between host side and board end
Time (gives the time more as far as possible to data transmission), improves Read DMA data transfer efficiency.
The present invention provides a kind of DMA transfer methods suitable for network transmission, the DMA control applied to the configuration of board end
Device, comprising: before Write DMA transfer, the address for the memory space that host side is reserved is sequentially written in board end in advance and is matched
Some FIFO memories, wherein the reserved memory space of host side is to store the reserved space of the transmission data at board end；When
When preparing Write DMA transfer, according to the storage address of the transmission data of the address and board end that are stored in FIFO memory and
Size of data is autonomously generated descriptor, and descriptor is stored to the descriptor memory space reserved to board end, to execute Write
DMA transfer；When preparing Read DMA transfer, according to host side configure board end register information, obtain host side according to
The storage address for the descriptor that board end memory space actively generates；The storage of the descriptor actively generated according to host side
Descriptor is moved the descriptor memory space reserved to board end, from host side to execute Read DMA transfer by location.
As it can be seen that the address for the memory space that host side is reserved is sequentially written in board in advance by the application for Write DMA
It holds in the FIFO memory being furnished with, makes the dma controller at board end can be according to the address and board end stored in FIFO memory
Transmission data be autonomously generated descriptor, descriptor is safeguarded again without host side, to reduce between host side and board end
Interaction times, improve Write DMA data transfer efficiency, and reduce the work load of host side.For Read DMA,
Host side actively generates descriptor, rather than wait it is to be interrupted after regenerate descriptor again, so board end is without waiting for host
End regenerates descriptor, to reduce the interaction time between host side and board end, improves Read DMA data biography
Defeated efficiency.
On the basis of the above embodiments:
As a kind of preferred embodiment, according to depositing for the transmission data of the address and board end that are stored in FIFO memory
Storage address and size of data are autonomously generated descriptor, and descriptor is stored to the descriptor memory space reserved to board end, with
Execute Write DMA transfer, comprising:
Transmission address is configured in order for the network message in the transmission data at board end, wherein transmission address is from FIFO
The address successively selected in the address of memory storage；
For be not configured network message configuration transmission address while, according to configured network message at board end
Storage address, size of data and its corresponding transmission address are autonomously generated descriptor, and descriptor is successively stored to board end
Reserved descriptor memory space；
While the descriptor that storage has just generated, Write DMA transfer is executed according to stored descriptor.
Specifically, for Write DMA, network message of the dma controller in the transmission data for board end is successively matched
While setting transmission address (network message is transmitted to the address for being stored in host side after host side), according to configured transmission address
Network message be autonomously generated descriptor in the storage address at board end, size of data and its corresponding transmission address, and incite somebody to action from
The descriptor of main generation successively stores the descriptor memory space reserved to board end.Dma controller is retouched what will be autonomously generated
While stating the descriptor memory space for according with and successively storing and reserving to board end, stored descriptor is successively read to execute
Write DMA transfer.As it can be seen that the application can parallel processing to provide efficiency of transmission.
As a kind of preferred embodiment, the DMA transfer method further include:
The descriptor memory space that board end is reserved is divided into the multiple groups queue-type memory space of different priorities in advance；Its
In, what is stored in the descriptor stored in the high queue-type memory space of priority the queue-type memory space lower than priority retouches
State the preferential reading of symbol；
Then transmission address is configured in order for the network message in the transmission data at board end, comprising:
According to the priority of the network message in the transmission data at board end, it is followed successively by network message configuration transmission address；
Wherein, the high network message of the priority network message lower than priority preferentially configures, and the priority of board end network message
Classification is identical as the priority class of queue-type memory space；
Descriptor is successively stored to the descriptor memory space reserved to board end, comprising:
Descriptor is stored according to priority class belonging to its corresponding network message to the queue-type of the same category and is deposited
Store up space.
Further, due in DMA transfer descriptor (descriptor corresponding one can only be successively executed by storage order
A network message), so the corresponding network message of descriptor can only successively be transmitted by the storage order of descriptor, cause the later period from
The prior network message of network transmission can not prioritised transmission to host side.So for Write DMA, dma controller is mentioned
The preceding descriptor memory space for reserving board end is divided into the multiple groups queue-type memory space of different priorities.Wherein, same group
The priority of queue-type memory space is identical, i.e., in Write DMA transfer, descriptor is successively executed by storage order；Different groups
The priority of queue-type memory space is different, and the descriptor stored in the high queue-type memory space of priority compares priority
The descriptor stored in low queue-type memory space is preferentially read.
It is understood that in the transmission data at board end network message (abbreviation board end network message) priority class
It is not identical as the priority class of queue-type memory space.The application can be according to the importance of board end network message, by board
Network message is held to carry out priority division, the priority of more important network message (network message that should transmit as early as possible) is got over
It is high.
For example, the descriptor memory space that board end is reserved is divided into tri- groups of queue-type storage skies of A, B, C by dma controller
Between, the priority > C group queue-type memory space of the priority > B group queue-type memory space of A group queue-type memory space
Priority.Then the priority class of board end network message is equally divided into A, B, C three grades, the network message of A grade it is excellent
The priority of the network message of the priority > C grade of the network message of first grade > B grade.
To realize the more important more early transmission of network message, dma controller according to board end network message priority according to
It is secondary to transmit address (the high network message of the priority network message lower than priority preferentially configures) for network message configuration, and according to
It is secondary to be autonomously generated the corresponding descriptor of network message.Then, dma controller is by the descriptor being autonomously generated according to its corresponding net
Priority class belonging to network message is stored to the queue-type memory space of equal priority classification.
For example, storing the corresponding descriptor of the network message of A grade to A group queue-type memory space, by the net of B grade
The corresponding descriptor of network message is stored to B group queue-type memory space, by the corresponding descriptor of the network message of C grade store to
C group queue-type memory space, to enable prior network message prioritised transmission.
For example, early period is B grade from network transmission to priority class belonging to the network message at board end, correspond to
Descriptor store to B group queue-type memory space.Dma controller read B group queue-type memory space in descriptor when, if
At this time from the network message of network transmission A grade to board end, and the corresponding descriptor of the network message of A grade is stored to A
Group queue-type memory space, then after the dma controller descriptor that this reads in having executed B group queue-type memory space,
Just turn the descriptor of execution A group queue-type memory space.After the descriptor of A group queue-type memory space has been carried out, then
Turn to go to continue to execute remaining descriptor in B group queue-type memory space.
As a kind of preferred embodiment, according to the storage address for the descriptor that host side actively generates, from host side
Descriptor is moved to the descriptor memory space reserved to board end, to execute Read DMA transfer, comprising:
While host side configures board end register information, according to the storage for the descriptor that host side has actively generated
Descriptor is successively moved the descriptor memory space reserved to board end by address from host side；
While moving newly-generated descriptor from host side, Read DMA is executed according to stored descriptor and is passed
It is defeated.
Specifically, for Read DMA, dma controller while host side configures board end register information, according to
Descriptor is successively moved to what board end was reserved from host side and is retouched by the storage address for the descriptor that host side has actively generated
State symbol memory space.Descriptor is successively being moved the descriptor storage sky reserved to board end by dma controller from host side
Between while, be successively read stored descriptor to execute Read DMA transfer.As it can be seen that the application can parallel processing to provide
Efficiency of transmission.
As a kind of preferred embodiment, any descriptor that host side actively generates includes: the transmission data of host side
In a network message will transmit in the storage address of host side, the size of data of the network message and the network message
The memory address at board end.
Specifically, the present embodiment has been described in the above-described embodiments, and details are not described herein by the application.
As a kind of preferred embodiment, the DMA transfer method further include:
The descriptor memory space that board end is reserved is divided into the multiple groups queue-type memory space of different priorities in advance,
In, the priority class of queue-type memory space is identical as the priority class of host side network message, and the team that priority is high
The descriptor stored in the descriptor stored in column memory space the queue-type memory space lower than priority is preferentially read；
Descriptor is successively moved to the descriptor memory space reserved to board end from host side, comprising:
Descriptor is successively moved according to priority class belonging to its corresponding network message to identical from host side
The queue-type memory space of classification.
Similarly, for Read DMA, the descriptor memory space that board end is reserved is divided into different excellent by dma controller in advance
The multiple groups queue-type memory space of first grade.Wherein, the priority of same group of queue-type memory space is identical, i.e., passes in Read DMA
Descriptor is successively executed by storage order when defeated；The priority of difference group queue-type memory space is different, and priority is high
The descriptor stored in the descriptor stored in queue-type memory space the queue-type memory space lower than priority is preferentially read.
It is understood that in the transmission data of host side network message (abbreviation host side network message) priority class
It is not identical as the priority class of queue-type memory space.The application can be according to the importance of host side network message, by host
Network message is held to carry out priority division, the priority of more important network message (network message that should transmit as early as possible) is got over
It is high.
To realize the more important more early transmission of network message, host-side controller according to host side network message priority
Sequentially generating the descriptor of network message, (the high network message of the priority network message lower than priority is preferentially produced description
Symbol), and board end register information is configured, to inform the storage address of the descriptor of dma controller host side generation.DMA control
The storage address for the descriptor that device processed is just actively generated according to host side, by the descriptor of generation according to its corresponding network message
Affiliated priority class is stored to the queue-type memory space of equal priority classification, so that prior network message be made to obtain
With prioritised transmission.
Compared to Fig. 1, referring to figure 3., Fig. 3 is a kind of realization principle figure of DMA transfer provided by the invention.It is main in Fig. 3
Generator terminal issues the transmission request that a size is 6 pages, since operating system all uses virtual memory management mechanism, so main
6 pages of generator terminal user program distribution are very in maximum probability and discontinuous in physical memory space, may as shown in Figure 33
A continuous space (Data0, Data1, Data2) is constituted, wherein Data0, and the size of Data1, Data2 are respectively 1 page, and 3
A page and 2 pages.Narration, the application exist in detail in the above-described embodiments for host side and the specific transmission flow in board end
This is repeated no more.In the case where using PCIE-G3x8, a length of 2KByte of transmitting data frame in actual test, host side and plate
Transmission rate between card end is up to 55Gbit/s.In addition, the dma controller implementation method of Fig. 3 is based on FPGA, but this hair
Bright specific implementation is not limited to FPGA, other platforms can also realize that the DMA of efficient suitable network transmission is controlled according to this mechanism
Device processed, the application are not particularly limited herein.
Referring to figure 4., Fig. 4 is a kind of structural schematic diagram of the dma controller suitable for network transmission provided by the invention.
This is suitable for the dma controller of network transmission, comprising:
Pre-write module 1 is used for before Write DMA transfer, the address for the memory space in advance reserving host side
It is sequentially written in the fifo fifo memory being furnished at board end, wherein the reserved memory space of host side is to store board
The reserved space of the transmission data at end；
WDMA module 2 is used for when preparing Write DMA transfer, according to the address and board stored in FIFO memory
The storage address and size of data of the transmission data at end are autonomously generated descriptor, and descriptor is stored to what board end was reserved and is retouched
Symbol memory space is stated, to execute Write DMA transfer；
Address acquisition module 3, for being believed according to the board end register of host side configuration when preparing Read DMA transfer
Breath obtains the storage address for the descriptor that host side is actively generated according to board end memory space；
RDMA module 4, the storage address of the descriptor for being actively generated according to host side, by descriptor from host side
The descriptor memory space reserved to board end is moved, to execute Read DMA transfer.
As a kind of preferred embodiment, WDMA module 2 includes:
Address configuration unit, for when preparing Write DMA transfer, being the network message in the transmission data at board end
Configure in order transmission address, wherein transmission address is the address successively selected from the address that FIFO memory stores；
First descriptor generation unit, for for be not configured network message configuration transmission address while, according to
The network message of configuration is autonomously generated descriptor in the storage address at board end, size of data and its corresponding transmission address, and
Descriptor is successively stored to the descriptor memory space reserved to board end；
First execution unit, for being executed according to stored descriptor while storing the descriptor just generated
Write DMA transfer.
As a kind of preferred embodiment, the dma controller further include:
Priority presetting module, for the descriptor memory space that board end is reserved to be divided into the more of different priorities in advance
Group queue-type memory space；Wherein, the descriptor stored in the high queue-type memory space of priority the queue lower than priority
The descriptor stored in formula memory space is preferentially read；
Then transmission address is configured in order for the network message in the transmission data at board end, comprising:
According to the priority of the network message in the transmission data at board end, it is followed successively by network message configuration transmission address；
Wherein, the high network message of the priority network message lower than priority preferentially configures, and the priority of board end network message
Classification is identical as the priority class of queue-type memory space；
Descriptor is successively stored to the descriptor memory space reserved to board end, comprising:
Descriptor is stored according to priority class belonging to its corresponding network message to the queue-type of the same category and is deposited
Store up space.
As a kind of preferred embodiment, RDMA module 4 includes:
Second descriptor generation unit is used for while host side configures board end register information, according to host side
Descriptor is successively moved to the descriptor that board end is reserved from host side and is deposited by the storage address of the descriptor actively generated
Store up space；
Second execution unit, for being retouched according to stored while moving newly-generated descriptor from host side
It states symbol and executes Read DMA transfer.
The introduction of dma controller provided by the present application please refers to the embodiment of above-mentioned DMA transfer method, and the application is herein not
It repeats again.
It should also be noted that, in the present specification, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of DMA transfer method suitable for network transmission, which is characterized in that the direct memory applied to the configuration of board end
Access dma controller, comprising:
Before Write DMA transfer, the address for the memory space that host side is reserved is sequentially written in the board end in advance and is matched
Some fifo fifo memories, wherein the reserved memory space of the host side is the transmission to store the board end
The reserved space of data；
When preparing Write DMA transfer, according to the transmission number of the address and the board end that are stored in the FIFO memory
According to storage address and size of data be autonomously generated descriptor, and the descriptor is stored to the description reserved to the board end
Memory space is accorded with, to execute Write DMA transfer；
When preparing Read DMA transfer, according to the board end register information that the host side configures, the host side is obtained
According to the storage address for the descriptor that board end memory space actively generates；
According to the storage address for the descriptor that the host side actively generates, descriptor is moved to described from the host side
The reserved descriptor memory space in board end, to execute Read DMA transfer.
2. being suitable for the DMA transfer method of network transmission as described in claim 1, which is characterized in that described according to
The storage address and size of data of the transmission data of the address and the board end that store in FIFO memory are autonomously generated description
Symbol, and the descriptor is stored to the descriptor memory space reserved to the board end, to execute Write DMA transfer, packet
It includes:
For the network message in the transmission data at the board end configure in order transmission address, wherein the transmission address for from
The address successively selected in the address of the FIFO memory storage；
For be not configured network message configuration transmission address while, according to configured network message at the board end
Storage address, size of data and its corresponding transmission address are autonomously generated descriptor, and the descriptor is successively stored to institute
State the reserved descriptor memory space in board end；
While the descriptor that storage has just generated, Write DMA transfer is executed according to stored descriptor.
3. being suitable for the DMA transfer method of network transmission as claimed in claim 2, which is characterized in that the DMA transfer method is also
Include:
The descriptor memory space that the board end is reserved is divided into the multiple groups queue-type memory space of different priorities in advance；Its
In, what is stored in the descriptor stored in the high queue-type memory space of priority the queue-type memory space lower than priority retouches
State the preferential reading of symbol；
Then the network message in the transmission data for the board end configures in order transmission address, comprising:
According to the priority of the network message in the transmission data at the board end, it is followed successively by the network message configuration transmission ground
Location；Wherein, the high network message of the priority network message lower than priority preferentially configures, and board end network message is preferential
Grade classification is identical as the priority class of the queue-type memory space；
It is described that the descriptor is successively stored to the descriptor memory space reserved to the board end, comprising:
The descriptor is stored according to priority class belonging to its corresponding network message to the queue-type of the same category and is deposited
Store up space.
4. being suitable for the DMA transfer method of network transmission as described in claim 1, which is characterized in that described according to the master
Descriptor is moved to what the board end was reserved from the host side and is retouched by the storage address for the descriptor that generator terminal actively generates
Symbol memory space is stated, to execute Read DMA transfer, comprising:
While the host side configures board end register information, the descriptor that has actively generated according to the host side
Descriptor is successively moved the descriptor memory space reserved to the board end by storage address from the host side；
While moving newly-generated descriptor from the host side, Read DMA is executed according to stored descriptor and is passed
It is defeated.
5. being suitable for the DMA transfer method of network transmission as claimed in claim 4, which is characterized in that the host side is actively
Any descriptor generated include: in the transmission data of the host side network message in the storage of the host side
The memory address at the board end that location, the size of data of the network message and the network message will transmit.
6. being suitable for the DMA transfer method of network transmission as claimed in claim 5, which is characterized in that the DMA transfer method is also
Include:
The descriptor memory space that the board end is reserved is divided into the multiple groups queue-type memory space of different priorities in advance,
In, the priority class of the queue-type memory space is identical as the priority class of host side network message, and priority is high
Queue-type memory space in the descriptor that stores in the descriptor that the stores queue-type memory space lower than priority preferentially read
It takes；
It is described that descriptor is successively moved to the descriptor memory space reserved to the board end from the host side, comprising:
Descriptor is successively moved according to priority class belonging to its corresponding network message to identical from the host side
The queue-type memory space of classification.
7. a kind of dma controller suitable for network transmission characterized by comprising
Pre-write module, in advance successively writing the address for the memory space that host side is reserved before Write DMA transfer
Enter the fifo fifo memory that the board end is furnished with, wherein the reserved memory space of the host side is to store institute
State the reserved space of the transmission data at board end；
WDMA module is used for when preparing Write DMA transfer, according to the address and the plate stored in the FIFO memory
The storage address and size of data of the transmission data at card end are autonomously generated descriptor, and the descriptor is stored to the board
The reserved descriptor memory space in end, to execute Write DMA transfer；
Address acquisition module, for being believed according to the board end register of host side configuration when preparing Read DMA transfer
Breath, obtains the storage address for the descriptor that the host side is actively generated according to board end memory space；
RDMA module, the storage address of the descriptor for actively generating according to the host side will be retouched from the host side
It states symbol and moves the descriptor memory space reserved to the board end, to execute Read DMA transfer.
8. being suitable for the dma controller of network transmission as claimed in claim 7, which is characterized in that the WDMA module includes:
Address configuration unit, for when preparing Write DMA transfer, being the network message in the transmission data at the board end
Configure in order transmission address, wherein the transmission address is the ground successively selected from the address that the FIFO memory stores
Location；
First descriptor generation unit, for for be not configured network message configuration transmission address while, according to configured
Network message be autonomously generated descriptor in the storage address at the board end, size of data and its corresponding transmission address, and
The descriptor is successively stored to the descriptor memory space reserved to the board end；
First execution unit, for executing Write according to stored descriptor while storing the descriptor just generated
DMA transfer.
9. being suitable for the dma controller of network transmission as claimed in claim 8, which is characterized in that the dma controller also wraps
It includes:
Priority presetting module, for the descriptor memory space that the board end is reserved to be divided into the more of different priorities in advance
Group queue-type memory space；Wherein, the descriptor stored in the high queue-type memory space of priority the queue lower than priority
The descriptor stored in formula memory space is preferentially read；
Then the network message in the transmission data for the board end configures in order transmission address, comprising:
According to the priority of the network message in the transmission data at the board end, it is followed successively by the network message configuration transmission ground
Location；Wherein, the high network message of the priority network message lower than priority preferentially configures, and board end network message is preferential
Grade classification is identical as the priority class of the queue-type memory space；
It is described that the descriptor is successively stored to the descriptor memory space reserved to the board end, comprising:
The descriptor is stored according to priority class belonging to its corresponding network message to the queue-type of the same category and is deposited
Store up space.
10. being suitable for the dma controller of network transmission as claimed in claim 7, which is characterized in that the RDMA module packet
It includes:
Second descriptor generation unit is used for while the host side configures board end register information, according to the master
The storage address for the descriptor that generator terminal has actively generated successively is moved descriptor from the host side pre- to the board end
The descriptor memory space stayed；
Second execution unit, for being retouched according to stored while moving newly-generated descriptor from the host side
It states symbol and executes Read DMA transfer.
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