CN111933580A - Preparation method of semiconductor structure - Google Patents
Preparation method of semiconductor structure Download PDFInfo
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- CN111933580A CN111933580A CN202011019411.7A CN202011019411A CN111933580A CN 111933580 A CN111933580 A CN 111933580A CN 202011019411 A CN202011019411 A CN 202011019411A CN 111933580 A CN111933580 A CN 111933580A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
Abstract
The invention discloses a preparation method of a semiconductor structure, which at least comprises the following steps: providing a substrate; forming a metal dielectric layer on the substrate, wherein the metal dielectric layer is provided with a metal structure; forming a plurality of dielectric layers on the metal dielectric layer; forming holes on the multilayer dielectric layer, wherein the holes are positioned in the metal structure, and the bottom of each hole is spaced from the metal structure; filling the hole with a high polymer material to form a hole filling layer; forming a patterned photoresist layer on the hole filling layer; etching, removing part of the dielectric layer and the hole filling layer to form a first through hole and a second through hole, wherein the first through hole is communicated with the second through hole, and the width of the first through hole is larger than that of the second through hole; deepening the second via to the metal dielectric layer. The invention can simplify the production process and improve the production efficiency.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure.
Background
At present, for example, in the process of manufacturing a damascene interconnect structure, holes are usually filled with an under layer material (UL) in a semiconductor, such as a bottom anti-reflective coating (BARC), and after the holes are filled with these materials, the thickness of the formed filling layer is relatively high, and since the material itself has relatively high viscosity and relatively soft texture, a photoresist layer cannot be directly formed thereon, the filling layer needs to be etched and further etched into the holes to a certain depth, so that a photoresist layer is formed on the holes, thereby facilitating the subsequent etching process.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor structure, which can directly form a photoresist layer (the polymer material serves as a bottom anti-reflective coating) on a polymer by filling a hole with, for example, a polymer material, thereby omitting a step of etching the hole filling layer, i.e., a back etching step, thereby simplifying the process and improving the production efficiency.
To achieve the above and other objects, the present invention provides a method for fabricating a semiconductor structure, comprising at least the following steps:
providing a substrate;
forming a metal dielectric layer on the substrate, wherein the metal dielectric layer is provided with a metal structure;
forming a plurality of dielectric layers on the metal dielectric layer;
forming holes on the multilayer dielectric layer, wherein the holes are positioned in the metal structure, and the bottom of each hole is spaced from the metal structure;
filling the hole with a high polymer material to form a hole filling layer;
forming a patterned photoresist layer on the hole filling layer;
etching, removing part of the dielectric layer and the hole filling layer to form a first through hole and a second through hole, wherein the first through hole is communicated with the second through hole, and the width of the first through hole is larger than that of the second through hole;
deepening the second via hole to the metal dielectric layer;
wherein the viscosity of the polymer materialThe degree of the alloy is 2.3-4.1 mm2/s。
In an embodiment, the thickness of the hole filling layer outside the hole is less than or equal to the thickness of the dielectric layer on the top end of the multi-layer dielectric layer.
In one embodiment, the width of the second through hole is 150 nm-180 nm, and the width of the first through hole is 160 nm-190 nm.
In one embodiment, the step of forming the multi-layer dielectric layer on the metal dielectric layer at least includes forming a first dielectric layer on the metal dielectric layer.
In one embodiment, the first dielectric layer is a doped silicon carbide thin film layer.
In one embodiment, the thickness of the first dielectric layer is 500-700 angstroms.
In one embodiment, the material of the multi-layer dielectric layer includes one or more of doped silicon carbide thin film, silicon nitride, tetraethyl silicate and silicon oxynitride.
In one embodiment, the multilayer dielectric layer includes five dielectric layers.
In one embodiment, the substrate is a wafer or a semiconductor structure including devices or circuits.
In one embodiment, the metal structures are copper wire structures arranged at intervals.
In one embodiment, the step of forming the multi-layer dielectric layer on the metal dielectric layer includes:
forming a first dielectric layer on the metal dielectric layer;
forming a second dielectric layer on the first dielectric layer;
forming a third dielectric layer on the second dielectric layer;
forming a fourth dielectric layer on the third dielectric layer;
and forming a fifth dielectric layer on the fourth dielectric layer.
In one embodiment, the first dielectric layer is a doped silicon carbide thin film layer, and the thickness of the first dielectric layer is 500-700 angstroms.
In an embodiment, the second dielectric layer and the fourth dielectric layer are tetraethoxysilane layers, and the thickness of the fourth dielectric layer is greater than that of the second dielectric layer.
In one embodiment, the thickness of the second dielectric layer is 2200 to 3200 angstroms. The thickness of the fourth dielectric layer is 3600 angstroms to 4400 angstroms.
In an embodiment, the third dielectric layer is a silicon nitride layer. The thickness of the third dielectric layer is 450-550 nm.
In an embodiment, the fifth dielectric layer is a silicon oxynitride layer.
In one embodiment, the etching step is dry etching, and HBr, HeHBr, Cl are used2、O2、N2、NF3Ar or HeO2And CF4One or more gases of the composition are used as etching gases.
According to the preparation method of the semiconductor structure, the high polymer material is used for filling the holes, and the photoresist layer can be directly formed on the high polymer, so that the step that the photoresist layer can be formed only by etching the hole filling layer, namely the back etching step, is omitted, the process is simplified, and the production efficiency is improved. The method is suitable for the process of preparing the Damascus structure or preparing other semiconductor structures which have holes and need to be filled with the holes. The invention not only has easily understood principle and simple process steps, but also is convenient for developing process.
Drawings
FIG. 1: a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;
FIG. 2: in one embodiment of the invention, a schematic diagram of five dielectric layers is formed;
FIG. 3: in one embodiment of the present invention, a schematic view of the hole is formed;
FIG. 4: in one embodiment of the present invention, a schematic diagram of the hole filling layer is formed;
FIG. 5: in one embodiment of the present invention, a schematic diagram of the photoresist layer is formed on the hole filling layer;
FIG. 6: in one embodiment of the present invention, a schematic diagram of the first through hole and the second through hole is formed after the etching step is performed;
FIG. 7: in an embodiment of the invention, the second via is deepened to the metal dielectric layer.
Description of the symbols
101. A substrate; 102. a metal dielectric layer; 103. a first dielectric layer; 104. a second dielectric layer; 105. a third dielectric layer; 106. a fourth dielectric layer; 107. a fifth dielectric layer; 108. a hole; 109. a hole-filling layer; 110. a first through hole; 111. a second through hole; 120. and (4) a photoresist layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," if any, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance.
The invention can directly form the light resistance layer on the macromolecule by filling the hole with the macromolecule material, thereby omitting the step of etching the hole filling layer to form the light resistance layer, namely the back etching step, simplifying the process and improving the production efficiency.
Referring to fig. 1, the present invention provides a method for fabricating a semiconductor structure, which comprises the following steps:
s1, providing a substrate;
s2, forming a metal dielectric layer on the substrate, wherein the metal dielectric layer has a metal structure;
s3, forming a multi-layer dielectric layer on the metal dielectric layer;
s4, forming holes in the multilayer dielectric layer, wherein the hole pairs are located in the metal structures, and the metal structures are spaced at the bottoms of the holes;
s5, filling the holes with a high polymer material to form a hole filling layer;
s6, forming a patterned photoresist layer on the hole filling layer;
s7, performing an etching step, removing part of the dielectric layer and the hole filling layer to form a first through hole and a second through hole, wherein the first through hole is communicated with the second through hole, and the width of the first through hole is larger than that of the second through hole;
and S8, deepening the second through hole to the metal dielectric layer.
Specifically, in step S1, please refer to fig. 1 and 2, the substrate 101 is, for example, a wafer substrate or a semiconductor structure including devices or circuits. The wafer substrate 100 may be single crystal silicon, polycrystalline silicon, silicon carbide, or a silicon-germanium compound, such as silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or another material, such as a semiconductor material, such as a iii or v compound, such as gallium arsenide. An active circuit is formed on the wafer substrate, and includes an active region and various doped regions, such as an N well, a P well, and lightly doped source/drain regions, and various other element isolations, such as a Shallow Trench Isolation (STI) structure, which is necessary for forming a semiconductor device.
Specifically, in step S2, please refer to fig. 2, wherein the metal structure 1021 is, for example, a copper wire structure arranged at intervals.
Specifically, in step S3, referring to fig. 1 and 2, the method for forming the multi-layer dielectric layer is, for example, Atomic Layer Deposition (ALD), and in other embodiments, wet oxidation, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), remote plasma CVD (rpcvd), plasma enhanced CVD (pecvd), metal organic CVD (mocvd), sputtering, plating, other suitable processes and/or combinations thereof may also be performed. Specifically, if a chemical vapor deposition method (CVD) is used, for example, one of Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD) is used.
Specifically, in step S3, referring to fig. 1 and fig. 2, the step of forming the multi-layer dielectric layer on the metal dielectric layer 102 includes the following steps: forming a first dielectric layer 103 (also called a barrier layer) on the metal dielectric layer 102, forming a second dielectric layer 104 on the first dielectric layer 103, forming a third dielectric layer 105 (also called a barrier layer) on the second dielectric layer 104, forming a fourth dielectric layer 106 on the third dielectric layer 105, and forming a fifth dielectric layer 107 (also called an anti-reflection coating) on the fourth dielectric layer 106. The first dielectric layer 103, the second dielectric layer 104, the third dielectric layer 105, the fourth dielectric layer 106, and the fifth dielectric layer 107 are formed by, for example, Atomic Layer Deposition (ALD), and in some other embodiments, wet oxidation, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), remote plasma CVD (rpcvd), plasma enhanced CVD (pecvd), metal organic CVD (mocvd), sputtering, plating, and other suitable processes and/or combinations thereof may also be performed. Specifically, if a chemical vapor deposition method (CVD) is used, for example, one of Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD) is used.
Specifically, in step S3, referring to fig. 1 and fig. 2, the first dielectric layer 103 is, for example, a doped silicon carbide thin film layer, and the thickness of the first dielectric layer 106 is, for example, 500 a to 700 a, specifically, 500 a, 550 a, 580 a, 600 a, 650 a, 680 a, 700 a, or other thicknesses suitable for the present invention. The second dielectric layer 104 and the fourth dielectric layer 106 are, for example, a tetraethyl silicate layer including, for example, an oxide material formed by using Tetraethoxysilane (TEOS) and ozone as reaction gases. The thickness of the fourth dielectric layer 106 is greater than the thickness of the second dielectric layer 104, wherein the thickness of the second dielectric layer 104 is 2200 to 3200 angstroms, specifically 2200 to 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms, or other thicknesses suitable for the present invention. For example, the thickness of the fourth dielectric layer 106 is 3600 angstroms to 4400 angstroms, specifically, 3600 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4400 angstroms, or other thicknesses suitable for the present invention. The second dielectric layer 104 and the fourth dielectric layer 106 may also be silicon oxycarbide (SICO) or other low dielectric constant (low K) dielectric material.
Specifically, in step S4, referring to fig. 1 to 3, for example, by an etching process, the holes 108 are formed on the fifth dielectric layer 107, the fourth dielectric layer 106, the third dielectric layer 105, the second dielectric layer 104 and the first dielectric layer 103, and the holes 108 do not penetrate through the first dielectric layer 103, that is, the bottoms of the holes 108 do not contact the metal structure 1021, so as to protect the metal structure 1021.
Specifically, in step S5, please refer to fig. 1 to 4, the hole 108 is filled with a polymer material to form a hole filling layer 109. The viscosity of the polymer material is, for example, 2.3 to 4.1mm2And s. Of the Polymer Material of the inventionThe high molecular material of the invention is used for filling the hole 108 to form the hole filling layer 109, and a photoresist layer can be directly formed on the hole filling layer 109, so that the subsequent etching step is convenient to carry out, and the step of etching back the hole filling layer 109 to form the photoresist layer 120 is not needed any more, thereby greatly simplifying the production process and improving the production efficiency. In the hole filling layer 109, the thickness of the hole filling layer 109 outside the hole 108 is also thinner.
Specifically, in step S6, referring to fig. 1 to 5, a patterned photoresist layer is formed on the hole filling layer 109, specifically, a photoresist layer 120 is first formed on the hole filling layer 109, and the photoresist layer 120 is exposed by a photolithography process using electromagnetic radiation (e.g., ultraviolet light) passing through a mask pattern corresponding to the first via hole 110 and the second via hole 111 (the exposure dimension is the dimension of the first via hole). The photoresist in the photoresist layer 120 is partially removed, thereby obtaining an etching pattern corresponding to the mask pattern in the photoresist layer 120.
Specifically, in step S7, please refer to fig. 1 to 6, an etching step is performed, in which a portion of the dielectric layer and the hole filling layer 109 are removed to form the first via 110 and the second via 111, the first via 110 is communicated with the second via 111, and a width of the first via 110 is greater than a width of the second via 111. Specifically, in an embodiment, for example, the fifth dielectric layer 107 and the fourth dielectric layer 106 are removed to the surface of the third dielectric layer 105, and when the third dielectric layer 105 is etched, a distance is continuously etched to the second dielectric layer 104, the distance is, for example, half of the thickness of the second dielectric layer 104, and meanwhile, the remaining hole filling layer 109 in the hole 108 is also removed to form the second through hole 111, that is, for example, a dry etching condition having a high etching selectivity to the hole filling layer 109, the fourth dielectric layer 106 and the third dielectric layer 105, for example, a dry etching condition having a high etching selectivity greater than 10 is selected, so as to obtain the second through hole 111Obtaining the first through hole 110 and the second through hole 111, wherein the etching step is, for example, dry etching using HBr, HeHBr, Cl2、O2、N2、NF3Ar or HeO2And CF4One or more gases in the composition are used as etching gas, and the etching rate of the etching gas to the hole filling layer 109 is greater than that of the multi-layer dielectric layer.
Specifically, in step S7, please refer to fig. 1 to 6, the fifth dielectric layer 107, the fourth dielectric layer 106, the third dielectric layer 105 and the hole filling layer 109 are etched, so as to obtain the first through holes 110 corresponding to the etching pattern in the photoresist layer. When the etching step etches the third dielectric layer 105, the first via hole 110 and the second via hole 111 are obtained, and the first via hole 110 is communicated with the second via hole 111, at this time, the width of the first via hole 110 is greater than that of the second via hole 111, and the width of the first via hole 111 is, for example, 160-190 nm, such as 160 nm, 175 nm, 180 nm, 185 nm, and 190 nm. The width of the second via 111 is, for example, 150 nm, 180 nm, such as 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 180 nm. In one embodiment, when the width of the first via 110 is 175 nm, the width of the second via 111 is less than 180 nm. When the width of the second via hole 111 is 175 nm, the width of the second via hole 110 is greater than 175 nm. The distance between the bottom of the first via hole 110 and the first dielectric layer 103 is, for example, 2200 to 2300 angstroms.
Specifically, in step S8, please refer to fig. 1 to 7, the second via 111 is deepened (i.e., continuously etched) to the metal dielectric layer 102. Etching the second via hole 111, removing the first dielectric layer 103 in the second via hole 111, and deepening the second via hole 111 until the metal dielectric layer 102 is completely exposed, for connection with a metal, wherein the etching process is, for example, a dry etching process, a wet etching process, or a plasma etching process, and in some embodiments, a source gas CH is used2F2And/or CHF3With nitrogenGas, argon and/or helium are used together to perform the etching process, in other embodiments, C may also be used4F6And/or C4F8Etching chemistry and CF4The plasma source gases are used together to perform the etching process.
Referring to fig. 1 to 7, in an embodiment, the method for manufacturing a semiconductor structure is applied to a method for manufacturing a copper damascene interconnect structure, and specifically, a metal dielectric layer 102 having a plurality of copper wire structures is formed on a substrate 101, a plurality of dielectric layers are formed on the metal dielectric layer 102, then a plurality of holes 108 are formed on the plurality of dielectric layers, the holes 108 are filled with a polymer material according to the present invention to form a hole filling layer 109, a patterned photoresist layer is formed on the hole filling layer 109, an etching step is performed, the etching step removes a part of the dielectric layers and the hole filling layer 109 to form a first via 110 and a second via 111, the first via 110 is communicated with the second via 111, and the width of the first via 110 is greater than the width of the second via 111, the etching step forms a plurality of through hole structures on the metal dielectric layer 102, so that the manufacturing method of the metal copper damascene interconnection structure simplifies the manufacturing process of the metal copper damascene interconnection structure, improves the production efficiency and saves the cost.
In summary, the present invention provides a method for manufacturing a semiconductor structure, wherein a hole is filled with a polymer material according to the present invention to form a hole filling layer, and a photoresist layer can be directly formed on the hole filling layer by using the properties of the polymer according to the present invention, such as viscosity, hardness, etc., so as to omit a step of etching the hole filling layer, i.e., a step of etching back, thereby simplifying the process and improving the production efficiency. Specifically, the polymer of the invention can be used for well filling holes, the formed hole filling layer is thinner in thickness and lower in viscosity, a light resistance layer can be directly formed on the hole filling layer, the step of etching the hole filling layer, namely the step of back etching, is omitted, and the subsequent direct etching process is facilitated. The method is suitable for the process of preparing the Damascus structure or preparing other semiconductor structures which have holes and need to be filled with the holes. The invention not only has easily understood principle and simple process steps, but also is convenient for developing process.
The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.
Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.
Claims (10)
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a metal dielectric layer on the substrate, wherein the metal dielectric layer is provided with a metal structure;
forming a plurality of dielectric layers on the metal dielectric layer;
forming holes on the multilayer dielectric layer, wherein the holes are positioned in the metal structure, and the bottom of each hole is spaced from the metal structure;
filling the hole with a high polymer material to form a hole filling layer;
forming a patterned photoresist layer on the hole filling layer;
etching, removing part of the dielectric layer and the hole filling layer to form a first through hole and a second through hole, wherein the first through hole is communicated with the second through hole, and the width of the first through hole is larger than that of the second through hole;
deepening the second via hole to the metal dielectric layer;
wherein the viscosity of the high polymer material is 2.3-4.1 mm2/s。
2. The method according to claim 1, wherein the thickness of the hole-filling layer outside the hole is less than or equal to the thickness of the top dielectric layer in the multi-layer dielectric layer.
3. The method of claim 1, wherein the second via has a width of 150 nm to 180 nm, and the first via has a width of 160 nm to 190 nm.
4. The method according to claim 1, wherein the step of forming the multi-layer dielectric layer on the metal dielectric layer comprises forming at least a first dielectric layer on the metal dielectric layer.
5. The method of claim 4, wherein the first dielectric layer is a doped silicon carbide thin film layer.
6. The method of claim 4, wherein the first dielectric layer has a thickness of 500-700 angstroms.
7. The method according to claim 4, wherein the material of the multi-layer dielectric layer comprises one or more of doped silicon carbide thin film, silicon nitride, tetraethyl silicate and silicon oxynitride.
8. The method of claim 1, wherein the plurality of dielectric layers comprises five dielectric layers.
9. The method of claim 1, wherein the substrate is a wafer or a semiconductor structure including devices or circuits.
10. The method of claim 1, wherein the metal structure is a copper wire structure arranged at intervals.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329118B1 (en) * | 1999-06-21 | 2001-12-11 | Intel Corporation | Method for patterning dual damascene interconnects using a sacrificial light absorbing material |
| US20030216026A1 (en) * | 2002-05-15 | 2003-11-20 | Institute Of Microelectronics | Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC) |
| US20060183348A1 (en) * | 2005-02-17 | 2006-08-17 | Meagley Robert P | Layered films formed by controlled phase segregation |
| WO2005029556A3 (en) * | 2003-09-19 | 2007-05-03 | Brewer Science Inc | Method of filling structures for forming via-first dual damascene interconnects |
| CN102044471A (en) * | 2009-10-09 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Interconnecting structure and forming method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329118B1 (en) * | 1999-06-21 | 2001-12-11 | Intel Corporation | Method for patterning dual damascene interconnects using a sacrificial light absorbing material |
| US20030216026A1 (en) * | 2002-05-15 | 2003-11-20 | Institute Of Microelectronics | Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC) |
| WO2005029556A3 (en) * | 2003-09-19 | 2007-05-03 | Brewer Science Inc | Method of filling structures for forming via-first dual damascene interconnects |
| US20060183348A1 (en) * | 2005-02-17 | 2006-08-17 | Meagley Robert P | Layered films formed by controlled phase segregation |
| CN102044471A (en) * | 2009-10-09 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Interconnecting structure and forming method thereof |
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