CN111916441A - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN111916441A CN111916441A CN201910376968.7A CN201910376968A CN111916441A CN 111916441 A CN111916441 A CN 111916441A CN 201910376968 A CN201910376968 A CN 201910376968A CN 111916441 A CN111916441 A CN 111916441A
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- 239000002184 metal Substances 0.000 claims description 45
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
- H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a semiconductor device. The semiconductor device includes a device region and a termination region, the termination region surrounding the device region, the device region including a plurality of Schottky regions of a first conductivity type and a plurality of diode regions of a second conductivity type, the plurality of diode regions including a first plurality of diode regions and a second plurality of diode regions, each of the first plurality of diode regions including a barrier region of the second conductivity type and a buffer region, the buffer region surrounding the barrier region, and the buffer region having an impurity concentration lower than that of the barrier region, each of the second plurality of diode regions being constituted by a buffer region of the second conductivity type. The semiconductor device can improve the current distribution in the device, improve the anti-surge capacity of the device and enable the device to have better electrical performance and reliability.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to semiconductor devices.
Background
Compared with silicon semiconductor devices, silicon carbide semiconductor devices can operate at higher temperatures and electric fields, and thus have a wide application prospect and market appeal. Various applications also require silicon carbide semiconductor devices to have high reliability, such as resistance to surge currents. For example, junction barrier schottky devices have been designed. The structure combines the advantages of the Schottky diode and the bipolar diode, and can greatly improve the surge current resistance of the Schottky device.
However, the performance of junction barrier schottky devices is greatly dependent on layout design. When the current is relatively large, heat is generated inside the device, so that the temperature of the device increases. Uneven heat dissipation tends to cause the device to generate excessive heat in certain areas, thus being fragile and easily damaged, which is one of the bottlenecks limiting the reliability of the device. Therefore, it is necessary to design such a semiconductor device having a more excellent layout design.
Disclosure of Invention
The present invention is directed to a semiconductor device that solves one or more of the problems set forth above in the prior art.
According to an aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a device region and a termination region, the termination region surrounding the device region, the device region including a plurality of Schottky regions of a first conductivity type and a plurality of diode regions of a second conductivity type, the plurality of diode regions including a first plurality of diode regions and a second plurality of diode regions, each of the first plurality of diode regions including a barrier region of the second conductivity type and a buffer region, the buffer region surrounding the barrier region, and the buffer region having an impurity concentration lower than that of the barrier region, each of the second plurality of diode regions being constituted by a buffer region of the second conductivity type.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, a plurality of Schottky regions, a plurality of diode regions, a first metal electrode, and a second metal electrode. The semiconductor layer includes silicon carbide and has a first face and a second face. The semiconductor layer includes a substrate of a first conductivity type and a drift layer formed on the substrate, the drift layer having an impurity concentration lower than that of the substrate. A plurality of Schottky regions are provided in the drift layer and extend from the first face in a direction toward the substrate. The plurality of diode regions have a second conductivity type different from the first conductivity type, are disposed in the drift layer and extend from the first face in a direction toward the substrate. The first metal electrode is arranged on the first surface and forms Schottky contact with the plurality of Schottky regions. The second metal electrode is disposed on the second face and forms an ohmic contact with the second face. The semiconductor device includes a device region in which a plurality of Schottky regions and a plurality of diode regions are located, each of the plurality of diode regions including a barrier region and a buffer region in a central region of the device region, the buffer region surrounding the barrier region, and the buffer region having an impurity concentration lower than that of the barrier region. In a corner region of the device region, each of the plurality of diode regions is composed of a buffer region of the second conductive type.
According to still another aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a device region and a termination region, the termination region surrounding the device region, the device region including a plurality of schottky regions of a first conductivity type and a plurality of diode regions of a second conductivity type, the second conductivity type being different from the first conductivity type. The device region includes a central region having sub-regions. The plurality of diode regions include a first plurality of diode regions and a second plurality of diode regions, each of the first plurality of diode regions includes a barrier region of the second conductivity type and a buffer region, the buffer region surrounds the barrier region, and an impurity concentration of the buffer region is lower than an impurity concentration of the barrier region. Each diode region of the second plurality of diode regions is comprised of a barrier region of the second conductivity type, the second plurality of diode regions being located in a sub-region.
According to still another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a semiconductor layer of a first conduction type, a plurality of Schottky regions, a plurality of diode regions, a first metal electrode and a second metal electrode. The semiconductor layer includes silicon carbide and has a first face and a second face. The semiconductor layer includes a substrate and a drift layer, the drift layer being an epitaxial layer formed on the substrate, the drift layer having an impurity concentration lower than that of the substrate. The first surface is a surface of the drift layer opposite the substrate, and the second surface is a surface of the substrate opposite the drift layer. A plurality of Schottky regions are located within the drift layer and extend from the first face in a direction toward the substrate. A plurality of diode regions are located within the drift layer, the plurality of diode regions having the second conductivity type and extending from the first face in a direction toward the substrate. A first metal electrode is disposed on the first face, the first metal electrode forming a Schottky contact with the plurality of Schottky regions and a low resistance contact with the plurality of diode regions. The second metal electrode forms an ohmic contact with the second face. The semiconductor device has a device region in which a plurality of Schottky regions and a plurality of diode regions are located, the device region including a central region including a sub-region, the device region outside the sub-region, each of the plurality of diode regions including a barrier region and a buffer region surrounding the barrier region, the buffer region having an impurity concentration lower than that of the barrier region, each of the plurality of diode regions being constituted by the barrier region in the sub-region.
According to the semiconductor device provided by one or more embodiments of the invention, the distribution of current in the device can be improved, so that the surge current resistance of the device is improved. For example, the layout design illustrated by one or more embodiments allows more current to flow through the central region or its sub-regions where heat dissipation is stronger, and thus less current flows through the regions where heat dissipation is poorer (e.g., corner regions and edge regions, especially corner regions), thereby avoiding heat from collecting in the regions where heat dissipation is poorer and damaging the semiconductor devices. The device can be made to carry higher surge currents, thereby improving the overall performance and reliability of the device.
Other embodiments and further technical effects of the present invention will be described in detail below.
Drawings
Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings. One or more embodiments are illustrated by the corresponding figures in the drawings, which are not meant to be limiting. For convenience, the same or similar elements are identified with the same or similar reference numerals in the drawings, and the drawings in the drawings are not to scale unless otherwise specified. Wherein the content of the first and second substances,
fig. 1 shows a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention;
fig. 2 shows a schematic top plan view of a semiconductor device according to a first embodiment;
fig. 3 shows a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention;
fig. 4 shows a schematic top plan view of a semiconductor device according to a second embodiment;
fig. 5 shows a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention;
fig. 6 shows a schematic top plan view of a semiconductor device according to a third embodiment;
fig. 7 shows a schematic top plan view of a semiconductor device according to a fourth embodiment;
fig. 8 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;
fig. 9 shows a schematic top plan view of a semiconductor device according to a fifth embodiment;
fig. 10 shows a schematic top plan view of a semiconductor device according to a sixth embodiment of the present invention;
fig. 11 shows a schematic top plan view of a semiconductor device according to a seventh embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will be described below in conjunction with the associated drawings.
As used herein, the term "device region" refers to a region functioning as a core of a semiconductor device that, under forward bias, serves to carry at least a majority of the current flowing through the semiconductor device.
As used herein, the term "termination region" refers to a region in a semiconductor device at an end or edge of the device that provides protection to the device region.
As used herein, the term "schottky region" refers to a region within the device region that is located within the drift layer below the schottky junction formed by the drift layer in contact with the metal electrode.
As used herein, the term "diode region" refers to a region in the drift layer of the device region having a conductivity type opposite to that of the drift layer.
As used herein, the term "corner region" refers to (1) a region that is located in the device region and near a corner of the termination region when the outer perimeter of the termination region constitutes a non-circular shape (e.g., square, hexagonal, etc.) from a top plan view perspective, "corner of the termination region" refers to a location where two adjacent edges, or adjacent faces, of the termination region intersect; (2) from a top plan view perspective, a region located in the device region and near the termination region when the outer periphery of the termination region constitutes a circle.
As used herein, the term "edge region" refers to (1) a region that is located in the device region and that is proximate to a perimeter or face of the termination region, but not proximate to a corner of the termination region, from a top plan view perspective, when the outer perimeter of the termination region constitutes a non-circular shape (e.g., square, hexagonal, etc.); (2) from a top plan view perspective, a region located in the device region and near the termination region when the outer periphery of the termination region constitutes a circle. In case (2), the corner region and the side region are indistinguishable, or in other words, the corner region and the side region coincide.
As used herein, the term "center region" refers to a region of the device region excluding corner regions and edge regions. The center region is generally located in the middle of the device region and is surrounded by the corner regions and the edge regions.
As used herein, the term "sub-region" refers to a portion or all of a region, e.g., a sub-region of a central region refers to a portion or all of a central region.
As used herein, the term "low resistance contact" refers to an ohmic contact or a contact close to an ohmic contact.
As used herein, the term "top plan view" or "plan view perspective" refers to a view of a face of a semiconductor layer on which a semiconductor device is disposed, and does not include a metal layer disposed on the face and layers above the metal layer. In other words, when referring to "top plan view" or "plan view perspective", the metal layer disposed on the side of the semiconductor layer and the layers above the metal layer have been removed.
As used herein, the term "dot-shaped" refers to a point-shaped view from a top plan view perspective in which the size of each diode region in each direction on a two-dimensional plane is not greatly different such that when a viewer moves away from the diode region to a position along a direction perpendicular to the two-dimensional plane, the viewer sees each diode region as a dot, and there is no position such that each diode region is seen by the viewer as a stripe before the viewer moves to that position. For example, from a top plan view perspective, diode regions having a circular, polygonal (e.g., square, hexagonal, etc.) shape may be considered as a typical dot pattern design, and diode regions having a stripe or stripe shape may not be considered as having a dot pattern design.
Fig. 1 and 2 are schematic views of a semiconductor device according to a first embodiment, according to an aspect of the present invention. Where fig. 1 shows a schematic cross-sectional view of a semiconductor device according to a first embodiment, fig. 1 may be a part of a cross-section, for example along the dashed line a-a in fig. 2. Fig. 2 is a schematic top plan view of a semiconductor device according to a first embodiment (with the metal electrode and layers above the metal electrode removed).
As shown in fig. 1, the semiconductor device is illustrated as a junction barrier schottky device. The semiconductor device includes a device region 100 and a termination region 20, the termination region 20 being disposed around the device region 100. The device region 100 is configured to carry a flow of current when forward biased, and the termination region 20 is configured to improve the distribution of the electric field at the edge or end of the device when reverse biased, thereby increasing the breakdown voltage of the device while providing protection to the device region 100. It will be appreciated by those skilled in the art that in fig. 1, the termination region located on the left, symmetrically disposed with respect to termination region 20, is not shown for purposes of clarity of illustration.
The semiconductor device includes a semiconductor layer 110, a first metal electrode or anode 130, and a second metal electrode or cathode 140. The semiconductor layer 110 includes a silicon carbide (SiC) material, such as single crystal 4H-SiC. The semiconductor layer 110 has a first or top surface 112 and a second or bottom or back surface 114. The first metal electrode 130 is in contact with the first face 112, and the second metal electrode 140 is in contact with the second face 114 (e.g., forming an ohmic contact), such that the semiconductor layer 110 is sandwiched between the first metal electrode 130 and the second metal electrode 140. At least a portion of the first face 112 of the termination region 20 is provided with a field oxide film 22. A passivation layer 150 is also disposed on the first metal electrode 130 and the field oxide film 22.
The metal electrodes 130, 140 may be formed of a suitable metal, such as aluminum (Al), nickel (Ni), titanium (Ti), silver (Ag), platinum (Pt), gold (Au), molybdenum (Mo), or a combination of two or more thereof. The field oxide film 22 may be, for example, a silicon oxide film. Passivation layer 150 may be polyimide or formed from other suitable materials.
The semiconductor layer 110 includes a substrate 116 of a first conductive type and a drift layer 118 formed thereon. In this particular embodiment, the substrate 116 is heavily doped n-type (n +) silicon carbide. The n-type impurity may be, for example, nitrogen or phosphorus, and the impurity concentration is, for example, 5E19cm-3(i.e., 5x 10)19cm-3) Or higher. The impurity concentration of the drift layer 118 is lower than that of the substrate 116. For example, the drift layer 118 has an n-type impurity concentration of 5E14cm-3To 2E16cm-3E.g., 8.5E15cm-3) And a thickness in the range of 5 microns to 80 microns. The drift layer 118 may be grown on the substrate 116 by epitaxy, for example.
The first side 112 is a side of the drift layer 118 opposite the substrate 116, and the second side 114 is a side of the substrate 116 opposite the drift layer 118. Within the device region 100, the drift layer 118 includes a plurality of schottky regions 120 and a plurality of diode regions 121. In the schottky region 120, the drift layer 118 contacts the first metal electrode 130 at the first side 112 to form a schottky junction or schottky contact. The diode region 121 is located within the drift layer 118 and extends from the first face 112 in a direction toward the second face 114. Two adjacent diode regions 121 are separated by a schottky region 120. The diode region 121 forms a low resistance contact (e.g., ohmic contact or near ohmic contact) with the first metal electrode 130.
As shown in fig. 1, each diode region 121 includes a barrier region 124 of the second conductive type and a buffer region 122. Both the buffer region 122 and the barrier region 124 are in contact with the first face 112, and in other dimensions or directions, the buffer region 122 surrounds or surrounds the barrier region 124.
In this particular embodiment, the barrier region 124 and the buffer region 122 are both p-type doped (e.g., the impurity is aluminum), and the impurity concentration of the barrier region 124 is higher than the impurity concentration of the buffer region 122. For example, the impurity concentration of the barrier region 124 is 7E18cm-3To 6E20cm-3In the range of 1E17cm, the impurity concentration of the buffer region 122-3To 6E18cm-3And (3) a range. The barrier region 124 has a first depth d1, the first depth d1 being the distance from the first face 112 to the location of the lower boundary of the barrier region 124 in the direction toward the substrate 116 (i.e., the negative y-axis direction in FIG. 1). The buffer region 122 has a second depth d2, and the second depth d2 is a distance from the first face 112 to a position of a lower boundary of the buffer region 122 in the drift layer 118 in a direction toward the substrate 116 (i.e., a negative y-axis direction in fig. 1). Here, the boundary refers to a position where the impurity concentration abruptly changes or the impurity conductivity type abruptly changes. The buffer region 122 and the barrier region 124 each have a width W in the x-axis direction in parallel with the first surface 112bAnd Wj(see FIG. 1), wherein Wb>Wj。
The buffer region 122 surrounds the barrier region 124, thereby improving the electric field characteristics at the sidewall and bottom of the barrier region 124, and improving the performance of the semiconductor device, such as reducing the leakage current and increasing the breakdown voltage.
In the region of termination region 20, drift layer 118 includes a well region 24 having a second conductivity type (e.g., p-type). Well region 24 extends from first side 112 of drift layer 118 toward substrate 116. A first doped region 26 of the second conductivity type and a plurality of second doped regions 28 are disposed in the well region 24. The first doped region 26 and the second doped region 28 each have an impurity concentration higher than that of the well region 24, and the width of the first doped region 26 is greater than that of the second doped region 28 in a direction parallel to the first plane 112 (i.e., the x direction in fig. 1) in the cross section shown in fig. 1.
Fig. 3 and 4 are schematic views of a semiconductor device according to a second embodiment of the present invention. Where fig. 3 shows a schematic cross-sectional view of a semiconductor device according to a second embodiment, fig. 3 may be a part of a cross-section, e.g. along the dashed line B-B in fig. 4. Fig. 4 is a schematic top plan view of a semiconductor device (with the metal electrode and layers above the metal electrode removed).
As shown in fig. 3, the semiconductor device includes a device region 200 and a termination region 30 surrounding the device region 200. The semiconductor device includes a semiconductor layer 210, a first metal electrode or anode 230, and a second metal electrode or cathode 240, a field oxide film 32, a passivation layer 250. The semiconductor layer 210 has a first side 212 and a second side 214 and includes a substrate 216 of a first conductivity type and a drift layer 218 disposed thereon. Within the device region 200, the drift layer 218 includes a plurality of schottky regions 220 and a plurality of diode regions 221, with adjacent two diode regions 221 separated by the schottky regions 220. The drift layer 218 comprises, in the region of the termination region 30, a well region 34 of the second conductivity type. A first doped region 36 of the second conductivity type having a higher impurity concentration and a plurality of second doped regions 38 are provided in the well region 34.
As shown in fig. 4, the device region 200 includes corner regions 202, edge regions 204, and a center region 206. The central region 206 is arranged to be surrounded or enclosed by the corner regions 202 and the edge regions 204. In this particular embodiment, device region 200 includes four corner regions 202 and four side regions 204. Each corner region 202 includes 2x2 (for a total of 4) diode regions and each side region 204 includes 2x10 (for a total of 20) diode regions. The remaining diode regions are in the central region 206.
In the edge region 204 and the central region 206, each diode region 221 includes a barrier region and a buffer region of the second conductivity type. The buffer region surrounds the barrier region. Whereas in the corner region 202 each diode region comprises only a buffer region and no barrier region (i.e. each diode region is constituted by a buffer region). That is, each diode region is a doped region of the second conductivity type having a relatively low impurity concentration. In this particular embodiment, the first conductivity type is n-type and the second conductivity type is p-type.
In this embodiment, the diode regions of the central region and the side regions may be referred to as a first plurality of diode regions, and the diode regions of the corner regions may be referred to as a second plurality of diode regions.
In this embodiment, since the corner regions do not have the barrier regions having relatively high impurity concentrations, the corner regions have a larger resistance than the edge regions and the center region. In forward bias, more current will flow through the less resistive center and edge regions, and less current will flow through the more resistive corner regions, and less heat will be generated in the corner regions. Since the corner regions generally have less heat dissipation than the central region and the edge regions, the corner regions often become weak points of the device region, and are prone to burning or damage due to heat concentration in the corner regions, which becomes a bottleneck limiting the overall performance (e.g., surge current resistance) of the device. Therefore, the layout design according to the present embodiment can avoid or reduce the occurrence of burning out in the corner regions, or the forward current threshold required for the corner regions to burn out or break will be increased. That is, the layout design according to the present embodiment can improve the surge current resistance of the semiconductor device and improve the performance of the device.
In addition, the impurity concentration of the buffer region in the corner region can be the same as the impurity concentration of the buffer region in the edge region and the central region, and the depth can also be the same, so that the ion implantation can be performed through the same mask, and the process complexity is not increased.
Fig. 5 and 6 are schematic views of a semiconductor device according to a third embodiment of the present invention. Where fig. 5 shows a schematic cross-sectional view of a semiconductor device according to a third embodiment, fig. 5 may be a part of a cross-section, for example along the dashed line C-C in fig. 6. Fig. 6 is a schematic top plan view of a semiconductor device (with the metal layer and layers above the metal layer removed). The cross section along the dashed line D-D is similar to fig. 3 and is therefore not shown.
The semiconductor device of the third embodiment is exemplified as a junction barrier schottky device. As shown in fig. 5, the semiconductor device includes a device region 300 and a termination region 40 surrounding the device region 300. The semiconductor device includes a semiconductor layer 310, a first metal electrode or anode 330, and a second metal electrode or cathode 340, a field oxide film 42, a passivation layer 350. Semiconductor layer 310 has a first side 312 and a second side 314 and includes a substrate 316 of a first conductivity type and a drift layer 318 disposed thereon. Within the device region 300, the drift layer 318 includes a plurality of schottky regions 320 and a plurality of diode regions 321, with two adjacent diode regions 321 separated by a schottky region 320. The drift layer 318 includes a well region 44 of the second conductivity type in the region of the termination region 40. A first doped region 46 of the second conductivity type having a higher impurity concentration and a plurality of second doped regions 48 are disposed in the well region 44.
As shown in fig. 6, device region 300 includes corner regions 302, edge regions 304, and center regions 306. The central region 306 is arranged to be surrounded by the corner regions 302 and the edge regions 304. In the central region 306, each diode region includes a barrier region and a buffer region of the second conductivity type. The buffer region surrounds the barrier region. Whereas in the corner region 302 and the edge region 304, each diode region includes only a buffer region and does not include a barrier region (i.e., each diode region is constituted by a buffer region). That is, in this region, each diode region is a doped region of the second conductivity type having a relatively low impurity concentration.
In this embodiment, the diode regions in the central region may be referred to as a first plurality of diode regions, and the diode regions in the corner and edge regions may be referred to as a second plurality of diode regions.
The central region generally has the best heat dissipation effect, the side regions are the next to the side regions, and the corner regions are the worst. In this embodiment, since the corner regions and the side regions do not have the barrier regions having relatively high impurity concentrations, the corner regions and the side regions have a higher resistance than the center region. In forward bias, more current will flow through the less resistive center region and less current will flow through the more resistive corner and edge regions, and less heat will be generated in the corner and edge regions. Therefore, the layout design according to the present embodiment can further improve the surge current resistance of the semiconductor device and improve the device performance as compared with the second embodiment.
Fig. 7 shows a schematic top plan view of a semiconductor device according to a fourth embodiment. As shown in fig. 7, termination region 50 surrounds device region 400. Device region 400 includes corner regions 402, edge regions 404, and center regions 406. Compared to fig. 6, the corner regions, the side regions, and the center region in fig. 7 have different shapes. For example, in fig. 7, the corner regions 402 are deeper into the central region 406, thereby further avoiding heat collection in the corner regions where heat dissipation is weak.
Fig. 8 and 9 are schematic views of a semiconductor device according to a fifth embodiment of the present invention. Where fig. 8 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment, fig. 8 may be a part of a cross-section, for example along the dashed line E-E in fig. 9. Fig. 9 is a schematic top plan view of a semiconductor device (with the metal electrode and layers over the metal electrode removed).
As shown in fig. 8, the semiconductor device includes a device region 500 and a termination region 60 surrounding the device region 500. The semiconductor device includes a semiconductor layer 510, a first metal electrode or anode 530, and a second metal electrode or cathode 540, a field oxide film 62, a passivation layer 550. Semiconductor layer 510 has a first side 512 and a second side 514 and includes a substrate 516 of a first conductivity type and a drift layer 518 disposed thereon. Within the device region 500, the drift layer 518 includes a plurality of schottky regions 520 and a plurality of diode regions 521, with two adjacent diode regions 521 separated by a schottky region 520. In the region of the termination region 60, the drift layer 518 comprises a well region 64 of the second conductivity type. A first doped region 66 of the second conductivity type having a higher impurity concentration and a plurality of second doped regions 68 are disposed in the well region 64.
As shown in fig. 9, the device region 500 includes corner regions 502, edge regions 504, and a center region 506. The central region 506 is arranged to be surrounded or enclosed by the corner regions 502 and the edge regions 504. In this particular embodiment, device region 500 includes four corner regions 502 and four side regions 504. Each corner region 502 includes 2x2 (for a total of 4) diode regions and each side region 504 includes 2x10 (for a total of 20) diode regions. The remaining diode regions are in the central region 506.
Referring to fig. 9 and 8 simultaneously, the central region 506 includes a sub-region 507. In the device region outside the sub-region 507, each diode region 521 includes a barrier region 524 and a buffer region 522 of the second conductivity type. The buffer region 522 surrounds the barrier region 524. And in the sub-region 507, each diode region 523 includes only the barrier region 525 and no buffer region (i.e., each diode region 523 is constituted by the barrier region 525). That is, each diode region 523 is a doped region of the second conductivity type having a relatively high impurity concentration, which is not surrounded by a buffer region having a relatively low impurity concentration. In this particular embodiment, the first conductivity type is n-type and the second conductivity type is p-type.
The impurity concentration of the barrier region 525 in the sub region 507 is the same as the impurity concentration of the barrier region 524 in the diode region 521 outside the sub region 507. The depth of the barrier region 525 in the sub-region 507 (i.e., the depth in the negative y-axis direction in fig. 8) is the same as the depth of the barrier region 524 in the diode region 521 outside the sub-region 507, i.e., dji＝djo. The width (W) of the barrier region 525 in the sub-region 507 in a direction parallel to the first face 512, e.g., the x-direction of FIG. 8ji) Equal to the width (i.e., W) of the buffer area 522 in the diode area 521 outside the sub area 507bo). Therefore, on one hand, the area of each schottky region in the sub-region 507 can be ensured to be the same as that of each schottky region outside the sub-region 507 (which is beneficial to keeping consistency of structural parameters of the device), and on the other hand, the barrier region 525 in the sub-region 507 and the barrier region 524 outside the sub-region 507 can be completed under the same mask and the same ion implantation process, so that the increase of process complexity is avoided, and the increase of manufacturing cost of the device is avoided.
In this embodiment, the diode regions in the device region outside the sub-region 507 may be referred to as a first plurality of diode regions, and the diode regions in the sub-region 507 may be referred to as a second plurality of diode regions.
In the present embodiment, the area of the barrier region in which the impurity concentration in the diode region is relatively high in the sub region is larger than that in the diode region other than the sub region, and thus the resistance of the diode region in the sub region is smaller. When forward biased, more current will flow through the less resistive sub-regions, and thus less current will flow through the more resistive regions outside the sub-regions. The current flowing through the corner and edge regions is reduced so that less heat will be generated in the corner and edge regions. Since the heat dissipation effect of the corner regions and the edge regions (especially the corner regions) is generally poor, the heat dissipation effect becomes a weak point of the device region, and the region is easy to burn or damage due to heat concentration in the first place, and becomes a bottleneck limiting the overall performance (such as surge current resistance) of the device. Therefore, the layout design according to the present embodiment can avoid or alleviate the heat concentration generated in the corner region and the side region (especially, the corner region), thereby improving the surge current resistance of the semiconductor device and improving the performance of the device.
Fig. 10 shows a schematic top plan view of a semiconductor device of a sixth embodiment of the present invention. As shown in fig. 10, the semiconductor device includes a device region 600 and a termination region 70 surrounding the device region 600. Device region 600 includes corner regions 602, edge regions 604, and center regions 606. The central region 606 is arranged to be surrounded or enclosed by the corner regions 602 and the edge regions 604. The device region 606 includes sub-regions 607. In the sub-region 607, each diode region includes only a barrier region having a relatively high impurity concentration. Unlike fig. 9, the sub-region 607 in fig. 10 has a different shape, but similarly the ability to increase the surge current resistance of the semiconductor device can be achieved.
Fig. 11 shows a schematic top plan view of a semiconductor device according to a seventh embodiment of the present invention. As shown in fig. 11, the semiconductor device includes a device region 700 and a termination region 80 surrounding the device region 700. Device region 700 includes corner regions 702, edge regions 704, and center regions 706. The central region 706 includes three sub-regions 706a, 706b, and 706c that are not in communication with each other. In each sub-region, each diode region includes only a barrier region having a relatively high impurity concentration.
The above-described embodiments are only for the purpose of illustrating the idea of the present invention and are not to be construed as limiting the present invention. For example, while embodiments have been described above using terms such as first, second, etc. to refer to various elements, it should be understood that these elements should not be limited by the above terms. The above terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
In the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. It will be appreciated by those skilled in the art that the first conductivity type may also be p-type and the second conductivity type may also be n-type.
In the above embodiments, the drift layer is shown as only one layer for illustrative purposes. It will be appreciated by those skilled in the art that any of these drift layers may comprise two or more layers, for example, may comprise one or more buffer layers, epitaxial layers, and combinations thereof, as desired.
In the above-described embodiment, each corner region 202, 302, 502, 602, 702 is shown to include 2x2 diode regions, and each side region 204, 304, 504, 604, 704 is shown to include 2x10 diode regions. It will be appreciated by those skilled in the art that both corner regions and edge regions may be provided according to actual needs, e.g. fewer or more diode regions may be included, e.g. each corner region may contain only one diode region, or eight diode regions. For example, each of the side regions may be provided to include diode regions of only one row (or column) nearest to the terminal region, and may also be provided to include diode regions of three or more rows (or columns) nearest to the terminal region. In some embodiments, the edge regions are arranged to contain more rows (or columns) of diode regions from the termination region at locations closer to the corner regions, and to contain fewer rows (or columns) of diode regions from the termination region at locations further from the corner regions. Other arrangements are possible with respect to the specific planar shape of the respective regions (corner regions, edge regions, central regions) as long as the layout design concept proposed by the present invention is met.
In the above embodiments, there are gaps shown between the regions, for example, the corner regions are not seamlessly connected with the adjacent edge regions and the central region, and there are gaps between the corner regions, the edge regions and the terminal regions. It is understood by those skilled in the art that these are merely illustrative of the design concepts of the embodiments that can be more intuitively understood (e.g., for ease of reference by arrows to be read and understood by those skilled in the art). It will be appreciated by those skilled in the art that adjacent regions may be seamlessly joined without gaps.
In the embodiments described above, such as in fig. 2, 4, 6, 7, 9-11, the diode regions are arranged in a regular arrangement (i.e., regularly aligned rows and columns). It will be appreciated by those skilled in the art that this is for illustrative purposes only and that other arrangements are possible, e.g. adjacent rows and columns may be offset by some amount, depending on the actual requirements.
It will be further appreciated by those of ordinary skill in the art that for purposes of clarity of illustration, elements (e.g., elements, regions, layers, etc.) in the figures have not necessarily been drawn to scale. For example, the thickness of the drift layer may be from a few microns to tens of microns, while the thickness of the substrate may be up to about 200 microns, which if drawn to scale would reduce the legibility of the drawing.
In addition, each element in the drawings is not necessarily the actual shape thereof. For example, the cross-sections of the barrier, buffer, well, doped regions in fig. 1, 3, 5, 8 are shown as squares, which are understood by those skilled in the art to be illustrative purposes only, e.g., actual doping profiles typically have certain transition regions or slopes or gradients, rather than profiles where the gradient is infinite at certain points or boundaries.
For another example, in the above-described embodiments, the plan views of the termination region, the device region, and the diode region show a square shape. It will be appreciated by those skilled in the art that these regions may be of other suitable shapes. Such as square with rounded corners, circular, or other polygonal shapes (e.g., other quadrilateral, hexagonal, etc.). For example, the plan view of the barrier region may have a shape selected from the group consisting of circular, square, hexagonal. The plan view of the buffer region may have a shape selected from the group consisting of circular, square, hexagonal.
Fig. 9 and 10 show the shape of the sub-regions, which are for illustrative purposes only. One skilled in the art can select the appropriate shape of the subregion as desired. For example, in the embodiment shown in FIG. 11, the central region includes three sub-regions. In other embodiments, less than three (e.g., two) or more than three sub-regions are possible, as may be desired, wherein the diode region of each sub-region contains only barrier regions with relatively high impurity concentrations.
In the above embodiments (e.g., the embodiment shown in fig. 1), the cross-sectional view shows a specific configuration of the termination region. It will be appreciated by those skilled in the art that other configurations of the termination region are possible, as long as the same or substantially the same effect is achieved.
Moreover, the reference numerals for each element in the repeating units are not all labeled for the sake of brevity. For example, for the repeated configuration of schottky regions and diode regions in fig. 1, the reference numerals for each schottky region and each diode region are not shown for the sake of brevity.
Similarly, in the above-described embodiments (e.g. fig. 1, 3, 5, 8), the termination region located on the left, symmetrically disposed with respect to the termination region, is not shown for the sake of simplicity.
However, it will be appreciated by those skilled in the art that the drawings herein do not detract from the generality of the description of the various embodiments of the invention. Rather, the drawings herein illustrate rather well the design concepts of the various embodiments of the invention.
Furthermore, it will be appreciated by those skilled in the art that the above embodiments are intended to illustrate the invention in different respects, and that they are not intended to be in isolation; rather, those skilled in the art can combine the different embodiments appropriately according to the above examples to obtain other technical solutions.
Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Embodiments of the present invention are illustrated in non-limiting examples. Variations that may occur to those skilled in the art upon consideration of the above-disclosed embodiments are within the scope of the invention.
Claims (16)
1. A semiconductor device comprising a device region and a termination region, the termination region surrounding the device region, the device region comprising a plurality of schottky regions of a first conductivity type and a plurality of diode regions of a second conductivity type, the plurality of diode regions comprising a first plurality of diode regions and a second plurality of diode regions, each of the first plurality of diode regions comprising a barrier region of the second conductivity type and a buffer region, the buffer region surrounding the barrier region, the buffer region having an impurity concentration lower than that of the barrier region, each of the second plurality of diode regions being formed of a buffer region of the second conductivity type.
2. The semiconductor device of claim 1, wherein the device region comprises a corner region, the second plurality of diode regions being disposed in the corner region.
3. The semiconductor device of claim 1, wherein the device region comprises a corner region and an edge region, the second plurality of diode regions being disposed in the corner region and the edge region.
4. The semiconductor device according to any one of claims 1 to 3, wherein a plan view of the barrier regions in the first plurality of diode regions has a shape selected from the group consisting of a circle, a square, and a hexagon, wherein a plan view of the buffer regions in the first plurality of diode regions has a shape selected from the group consisting of a circle, a square, and a hexagon, and wherein a plan view of the buffer regions in the second plurality of diode regions has a shape selected from the group consisting of a circle, a square, and a hexagon.
5. A semiconductor device, characterized in that the semiconductor device comprises:
a semiconductor layer including silicon carbide and having a first face and a second face, the semiconductor layer including a substrate of a first conductivity type and a drift layer formed on the substrate, the drift layer having an impurity concentration lower than that of the substrate;
a plurality of schottky regions provided in the drift layer and extending from the first face in a direction toward the base;
a plurality of diode regions having a second conductivity type different from the first conductivity type, the plurality of diode regions being disposed in the drift layer and extending from the first face in a direction toward the substrate;
a first metal electrode disposed on the first face, the first metal electrode forming a schottky contact with the plurality of schottky regions; and
a second metal electrode disposed on the second face and forming an ohmic contact with the second face,
the semiconductor device includes a device region in which the plurality of schottky regions and the plurality of diode regions are located, each of the plurality of diode regions includes a barrier region and a buffer region in a central region of the device region, the buffer region surrounds the barrier region, and has an impurity concentration lower than that of the barrier region, and each of the plurality of diode regions is composed of a buffer region of a second conductive type in a corner region of the device region.
6. The semiconductor device according to claim 5, wherein each of the plurality of diode regions is constituted by a buffer region of the second conductivity type in a side region of the device region.
7. The semiconductor device according to claim 5 or 6, wherein the impurity concentration of the buffer region in each of the diode regions is the same.
8. A semiconductor device comprising a device region and a termination region, the termination region surrounding the device region, the device region comprising a plurality of Schottky regions of a first conductivity type and a plurality of diode regions of a second conductivity type, the second conductivity type being different from the first conductivity type, the device region comprising a central region having sub-regions,
the plurality of diode regions include a first plurality of diode regions and a second plurality of diode regions, each of the first plurality of diode regions includes a barrier region of the second conductivity type and a buffer region, the buffer region surrounds the barrier region, and an impurity concentration of the buffer region is lower than an impurity concentration of the barrier region,
each diode region of the second plurality of diode regions is comprised of a barrier region of a second conductivity type, the second plurality of diode regions being located in the sub-region.
9. The semiconductor device according to claim 8, wherein a barrier region in the second plurality of diode regions is the same as an impurity concentration of a barrier region in the first plurality of diode regions.
10. The semiconductor device according to claim 8 or 9, wherein a depth of the barrier region in the second plurality of diode regions is the same as a depth of the barrier region in the first plurality of diode regions.
11. The semiconductor device according to claim 8 or 9, wherein a plan view of the barrier regions in the first plurality of diode regions has a shape selected from the group consisting of a circle, a square, and a hexagon, a plan view of the buffer regions in the first plurality of diode regions has a shape selected from the group consisting of a circle, a square, and a hexagon, and a plan view of the barrier regions in the second plurality of diode regions has a shape selected from the group consisting of a circle, a square, and a hexagon.
12. A semiconductor device, characterized in that the semiconductor device comprises:
a semiconductor layer of a first conductivity type including silicon carbide and having a first face and a second face, the semiconductor layer including a substrate and a drift layer, the drift layer being an epitaxial layer formed on the substrate, the drift layer having an impurity concentration lower than that of the substrate, the first face being a face of the drift layer opposite the substrate, the second face being a face of the substrate opposite the drift layer;
a plurality of schottky regions located within the drift layer and extending from the first face in a direction toward the base;
a plurality of diode regions within the drift layer, the plurality of diode regions having
A second conductivity type and extending from the first face in a direction toward the substrate;
a first metal electrode disposed on the first face, the first metal electrode forming a schottky contact with the plurality of schottky regions and forming a low resistance contact with the plurality of diode regions; and
a second metal electrode forming an ohmic contact with the second face,
the semiconductor device has a device region in which the plurality of schottky regions and the plurality of diode regions are located, the device region including a central region including a sub-region, a device region outside the sub-region, each of the plurality of diode regions including a barrier region and a buffer region surrounding the barrier region, the buffer region having an impurity concentration lower than that of the barrier region, each of the plurality of diode regions being constituted by the barrier region in the sub-region.
13. The semiconductor device according to claim 12, wherein an impurity concentration of the barrier region of each diode region in the sub-region is equal to an impurity concentration of the barrier region of each diode region in the device region outside the sub-region, and a depth of the barrier region of each diode region in the sub-region is equal to a depth of the barrier region of each diode region in the device region outside the sub-region.
14. A semiconductor device as claimed in claim 12 or 13, characterized in that the width of the barrier region of each diode region in the sub-region is equal to the width of the buffer region of each diode region in the device region outside the sub-region, in a plane parallel to the first face.
15. A semiconductor device as claimed in claim 12 or 13, characterized in that the sub-regions are square or circular in a plane parallel to the first face.
16. The semiconductor device according to claim 12 or 13, wherein the sub-region is two or more sub-regions that are not connected to each other.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113540257A (en) * | 2021-06-16 | 2021-10-22 | 先之科半导体科技(东莞)有限公司 | Schottky diode with high surge capacity |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070029634A1 (en) * | 2005-05-24 | 2007-02-08 | Hans-Joachim Schulze | High speed diode |
| US20080296587A1 (en) * | 2007-05-30 | 2008-12-04 | Denso Corporation | Silicon carbide semiconductor device having junction barrier schottky diode |
| CN208819891U (en) * | 2018-11-09 | 2019-05-03 | 无锡新洁能股份有限公司 | Optimize the SiC schottky diode of heat distribution |
-
2019
- 2019-05-07 CN CN201910376968.7A patent/CN111916441A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070029634A1 (en) * | 2005-05-24 | 2007-02-08 | Hans-Joachim Schulze | High speed diode |
| US20080296587A1 (en) * | 2007-05-30 | 2008-12-04 | Denso Corporation | Silicon carbide semiconductor device having junction barrier schottky diode |
| CN208819891U (en) * | 2018-11-09 | 2019-05-03 | 无锡新洁能股份有限公司 | Optimize the SiC schottky diode of heat distribution |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113540257A (en) * | 2021-06-16 | 2021-10-22 | 先之科半导体科技(东莞)有限公司 | Schottky diode with high surge capacity |
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