CN111913669B

CN111913669B - SSD power-down speed improving method and device, computer equipment and storage medium

Info

Publication number: CN111913669B
Application number: CN202010789563.9A
Authority: CN
Inventors: 龚宁波; 贾宗铭; 郭芳芳
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2023-04-28
Anticipated expiration: 2040-08-07
Also published as: CN111913669A

Abstract

The invention relates to a SSD power-down speed improving method, a SSD power-down speed improving device, computer equipment and a storage medium, wherein the method comprises the steps of storing log information when power is down; acquiring a transmit VU command from a first core; and sending the information corresponding to the VU command to a third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and the power-down operation is completed. In the invention, the power-down operation is carried out by monitoring the first core and the second core by the third core, so that the interaction action between the three cores is reduced, the time required by shutdown is saved, in addition, an exception handling mechanism is arranged for the second core and the third core, an Nvme custom command is used for acquiring an exception log in a shutdown process, the SSD error detection efficiency is improved, the time of the shutdown process is shortened, and the power-down speed of the SSD is effectively improved.

Description

SSD power-down speed improving method and device, computer equipment and storage medium

Technical Field

The invention relates to a solid state disk, in particular to a method and a device for improving the power-down speed of an SSD, computer equipment and a storage medium.

Background

Currently, SSD (Solid State Disk) is widely applied to PC terminals, and the existing SSD has imperfect power-down flow, taking 3 cores as an example, and the traditional SSD master control design adopts a first core to monitor the states of other two cores. The first core shares a shared FIFO (first in first out, first Input First Output) with the second core and the second core shares a shared FIFO with the third core. 3 core commands flow from the first core to the second core and then to the third core, and the status of the completion command flows from the third core to the second core and then to the first core. The first core comprehensively manages the second core and the third core, and the second core and the third core need to return the completion state of the command to the first core, but in the shutdown process, the first core can be caused to wait until the actions of the other two cores are completed completely to inform the host of power failure. In this period, after the second core action is completed, the completion state of the third core command is set in the shared FIFO, after the second core detects that the state is transferred to the first core through the FIFO, the csts.shst field is set after the first core detects that the state is completed, and the host considers that the master control completes the shutdown process after detecting that the state is completed, thereby powering down the SSD.

In the power-down process, the main control has completed the storage of information such as protection measures, but some data in the DRAM (dynamic random access memory ) is not stored in the NAND, the first core needs to send a VU (custom command) to store, the first core needs to wait for the second core to complete the command with the third core, and then the power-down process can be finished.

Therefore, a new method is necessary to be designed, so that the time of a shutdown process is shortened, and the power-down speed of the SSD is effectively improved.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a method, a device, computer equipment and a storage medium for improving the power-down speed of an SSD.

In order to achieve the above purpose, the present invention adopts the following technical scheme: the SSD power-down speed improving method comprises the following steps:

when power is lost, log information is stored;

acquiring a transmit VU command from a first core;

and sending the information corresponding to the VU command to a third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and the power-down operation is completed.

The further technical scheme is as follows: the obtaining a transmit VU command from a first core includes:

the VU commands are polled through the shared FIFO.

The further technical scheme is as follows: the information corresponding to the VU command comprises a logical-physical mapping table and written data.

The further technical scheme is as follows: the step of sending the information corresponding to the VU command to the third core so that the third core writes the information corresponding to the VU command into the NAND Flash to complete the power-down operation, including:

transmitting information corresponding to the VU command to a third core, and writing the information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state;

judging whether the writing completion state is a data writing error or not by a third core;

if the writing completion state is a data writing error, the third core wakes up the second core through interruption, so that the second core transmits data once again for writing, if the data writing error occurs, abnormal data is recorded, a specific field is juxtaposed, and the third core informs the host to perform power-down operation;

if the write completion status is not a data write error, the third core notifies the host to perform a power down operation.

The further technical scheme is as follows: the method includes the steps of sending information corresponding to the VU command to a third core, writing the information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state, and further comprising:

transmitting information corresponding to the VU command to a third core to obtain a transmission result;

judging whether the sending result is not submitted to completion;

if the sending result is that the power failure is not completed, an exception log is saved, and a specific field is set for the host to perform the power failure operation according to the specific field;

if the sending result is not the non-submitted completion, writing information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state.

The further technical scheme is as follows: after the third core informs the host to perform the power-down operation, the method further comprises:

the host sends Nvme custom commands to obtain the saved exception log.

The invention also provides an SSD power down speed improving device, which comprises:

the information storage unit is used for storing log information when power is lost;

a command acquisition unit configured to acquire a transmit VU command from a first core;

the information sending unit is used for sending information corresponding to the VU command to the third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and power-down operation is completed.

The further technical scheme is as follows: the information storage unit is used for polling the VU command through the shared FIFO.

The invention also provides a computer device which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the method when executing the computer program.

The present invention also provides a storage medium storing a computer program which, when executed by a processor, performs the above-described method.

Compared with the prior art, the invention has the beneficial effects that: in the invention, the power-down operation is carried out by monitoring the first core and the second core by the third core, so that the interaction action between the three cores is reduced, the time required by shutdown is saved, in addition, an exception handling mechanism is arranged for the second core and the third core, an Nvme custom command is used for acquiring an exception log in a shutdown process, the SSD error detection efficiency is improved, the time of the shutdown process is shortened, and the power-down speed of the SSD is effectively improved.

The invention is further described below with reference to the drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is an application scenario schematic diagram of an SSD power failure speed improvement method according to an embodiment of the invention;

fig. 2 is a flow chart of a method for improving the SSD power-down speed according to an embodiment of the invention;

fig. 3 is a schematic sub-flowchart of a method for improving the SSD power-down speed according to an embodiment of the invention;

fig. 4 is a schematic sub-flowchart of a method for improving the SSD power-down speed according to an embodiment of the invention;

FIG. 5 is a schematic block diagram of an SSD power down speed improving device provided by an embodiment of the present invention;

fig. 6 is a schematic block diagram of a computer device according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic diagram of an application scenario of an SSD power failure speed improvement method according to an embodiment of the invention. Fig. 2 is a schematic flowchart of a method for improving the SSD power-down speed according to an embodiment of the invention. The SSD power-down speed increasing method is applied to terminals such as computers with solid state disks. The server performs data interaction with a computer with a solid state disk, and the solid state disk is integrated in the computer and consists of a first core, a second core and a third core.

Fig. 2 is a flowchart of a method for improving the SSD power failure speed according to an embodiment of the invention. As shown in fig. 2, the method includes the following steps S110 to S130.

S110, when power is lost, log information is stored.

In this embodiment, the log information includes information of security performance, data, and the like, that is, information of the completion portion security, smart, and the like.

And when the solid state disk stops running, the log information is stored.

S120, a VU command sent from the first core is acquired.

In this embodiment, after the first core sends the VU command, it enters a state waiting for an interrupt to wake.

Specifically, the VU command is polled through the shared FIFO.

S130, sending information corresponding to the VU command to a third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and power-down operation is completed.

In this embodiment, the information corresponding to the VU command includes a logical-physical mapping table and written data.

The second core polls the command through the shared FIFO, and submits information such as the logical-physical mapping table, the written data, etc. to the NFC (near field communication ) module of the third core through the shared FIFO. And the third core receives the information submitted by the second core, writes the information into the NAND Flash through the NFC module, detects the writing completion state of the information, and enters a waiting interrupt awakening state after the submitted information is completed. After the third core detects that the information is completely written into the NAND Flash, the CSTS.SHST field is set, and the host computer is powered down after detecting that the information is completely written into the NAND Flash.

In one embodiment, referring to fig. 3, the step S130 may include steps S131 to S135.

S131, sending information corresponding to the VU command to a third core, and writing the information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state.

In one embodiment, referring to fig. 4, the step S131 may include steps S1311 to S1314.

S1311, transmitting information corresponding to the VU command to a third core to obtain a transmission result;

s1312, judging whether the sending result is not submitted to completion;

s1313, if the sending result is that the sending is not submitted to completion, saving an exception log and setting a specific field for the host to perform power-down operation according to the specific field;

s1314, if the sending result is not uncommitted, writing information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state.

S132, judging whether the writing completion state is a data writing error or not by a third core;

s133, if the writing completion state is a data writing error, a third core wakes up a second core through interruption, so that the second core transmits data once again for writing, if the data writing error occurs, abnormal data is recorded, a specific field is juxtaposed, the third core informs a host to perform power-down operation, and step S135 is executed;

s134, if the writing completion state is not a data writing error, the third core informs the host to perform power-down operation;

s135, the host sends an Nvme custom command to acquire the saved exception log.

In the above process, the second core designs an exception handling mechanism, if the second core does not complete data submission, an exception log is saved, and the exception log is set in a csts.shst field to notify the host of power failure to the solid state disk. The third core part designs an exception handling mechanism, if the second core detects a data writing error, the second core is awakened through interruption, so that the second core submits data to the NFC module again, if writing has a problem, the third core stores an exception log, a CSTS (solid state disk) field is set, and a host is notified of power failure of the solid state disk. After the next power-on, the host can issue an Nvme custom command to acquire the abnormal log information stored in the second core and the third core.

Specifically, when the host computer performs a power-down operation on the solid state disk, the host computer monitors that the csts.shst field is set.

By reasonably modifying the shutdown flow, the coordination relationship among the three cores in the shutdown stage is reorganized. The mode of supervising the first core and the second core by the second core reduces the interaction frequency between the three cores, thereby saving the time required by shutdown, improving the shutdown speed of the computer terminal, saving the time of a user and improving the user satisfaction. Meanwhile, the Nvme custom command is innovatively used, log information stored in abnormal conditions is obtained, and a basis for solving the problem is provided for after-sales personnel.

According to the SSD power-down speed increasing method, the first core and the second core are supervised by the third core to conduct power-down operation, interaction among the three cores is reduced, time required by shutdown is saved, in addition, an exception handling mechanism is arranged for the second core and the third core, nvme custom commands are used for obtaining exception logs in a shutdown process, SSD error detection efficiency is improved, time of the shutdown process is shortened, and power-down speed of the SSD is effectively increased.

Fig. 5 is a schematic block diagram of an SSD power failure speed improvement device 300 according to an embodiment of the invention. As shown in fig. 5, the present invention further provides an SSD power failure rate improving apparatus 300 corresponding to the above SSD power failure rate improving method. The SSD power-down speed improvement device 300 includes a unit for performing the above-described SSD power-down speed improvement method, and may be configured in a desktop computer, a tablet computer, a portable computer, or the like. Specifically, referring to fig. 5, the SSD power-down speed improvement device 300 includes an information holding unit 301, a command acquiring unit 302, and an information transmitting unit 303.

An information storage unit 301, configured to store log information when power is turned off;

a command acquisition unit 302 for acquiring a transmit VU command from a first core;

the information sending unit 303 is configured to send information corresponding to the VU command to the third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and complete the power-down operation.

In an embodiment, the information holding unit 301 is configured to poll the VU command through the shared FIFO.

In an embodiment, the information sending unit 303 is configured to send information corresponding to the VU command to a third core, where the third core writes the information corresponding to the VU command into the NAND Flash to obtain a writing completion status; judging whether the writing completion state is a data writing error or not by a third core; if the writing completion state is a data writing error, the third core wakes up the second core through interruption, so that the second core transmits data once again for writing, if the data writing error occurs, abnormal data is recorded, a specific field is juxtaposed, and the third core informs the host to perform power-down operation; if the writing completion state is not the data writing error, the third core informs the host to perform power-down operation, and the host sends an Nvme custom command to acquire the saved exception log.

Specifically, the sending the information corresponding to the VU command to the third core, where the third core writes the information corresponding to the VU command into the NAND Flash to obtain the writing completion status, and the method further includes: transmitting information corresponding to the VU command to a third core to obtain a transmission result; judging whether the sending result is not submitted to completion; if the sending result is that the power failure is not completed, an exception log is saved, and a specific field is set for the host to perform the power failure operation according to the specific field; if the sending result is not the non-submitted completion, writing information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state.

It should be noted that, as those skilled in the art can clearly understand, the specific implementation process of the SSD power failure speed improving device 300 and each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, the description is omitted here.

The above-described SSD power down speed improvement device 300 may be implemented in the form of a computer program that can be run on a computer apparatus as shown in fig. 6.

Referring to fig. 6, fig. 6 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 500 may be a terminal, where the terminal may be an electronic device having a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device.

With reference to FIG. 6, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a SSD power down speed improvement method.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for the execution of a computer program 5032 in the non-volatile storage medium 503, which computer program 5032, when executed by the processor 502, causes the processor 502 to perform a method for improving the power down speed of an SSD.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of a portion of the architecture in connection with the present application and is not intended to limit the computer device 500 to which the present application is applied, and that a particular computer device 500 may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 502 is configured to execute a computer program 5032 stored in a memory to implement the steps of:

when power is lost, log information is stored; acquiring a transmit VU command from a first core; and sending the information corresponding to the VU command to a third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and the power-down operation is completed.

The information corresponding to the VU command comprises a logical-physical mapping table and written data.

In one embodiment, the processor 502, when implementing the step of obtaining the transmit VU command from the first core, specifically implements the following steps:

the VU commands are polled through the shared FIFO.

In an embodiment, when the processor 502 sends the information corresponding to the VU command to the third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, the following steps are specifically implemented:

transmitting information corresponding to the VU command to a third core, and writing the information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state; judging whether the writing completion state is a data writing error or not by a third core; if the writing completion state is a data writing error, the third core wakes up the second core through interruption, so that the second core transmits data once again for writing, if the data writing error occurs, abnormal data is recorded, a specific field is juxtaposed, and the third core informs the host to perform power-down operation; if the write completion status is not a data write error, the third core notifies the host to perform a power down operation.

In an embodiment, when the processor 502 sends the information corresponding to the VU command to the third core, and the third core writes the information corresponding to the VU command into the NAND Flash to obtain the writing completion status, the following steps are specifically implemented:

transmitting information corresponding to the VU command to a third core to obtain a transmission result; judging whether the sending result is not submitted to completion; if the sending result is that the power failure is not completed, an exception log is saved, and a specific field is set for the host to perform the power failure operation according to the specific field; if the sending result is not the non-submitted completion, writing information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state.

In one embodiment, after implementing the step of notifying the host to perform the power-down operation by the third core, the processor 502 further implements the following steps:

the host sends Nvme custom commands to obtain the saved exception log.

It should be appreciated that in embodiments of the present application, the processor 502 may be a central processing unit (Central Processing Unit, CPU), the processor 502 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

Those skilled in the art will appreciate that all or part of the flow in a method embodying the above described embodiments may be accomplished by computer programs instructing the relevant hardware. The computer program comprises program instructions, and the computer program can be stored in a storage medium, which is a computer readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer readable storage medium. The storage medium stores a computer program which, when executed by a processor, causes the processor to perform the steps of:

In one embodiment, the processor, when executing the computer program to perform the step of obtaining the transmit VU command from the first core, performs the steps of:

the VU commands are polled through the shared FIFO.

In an embodiment, when the processor executes the computer program to send the information corresponding to the VU command to the third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, the following steps are specifically implemented when the power-down operation step is completed:

In an embodiment, when the processor executes the computer program to send the information corresponding to the VU command to the third core, the third core writes the information corresponding to the VU command into the NAND Flash to obtain the writing completion status step, the following steps are specifically implemented:

In one embodiment, after executing the computer program to implement the third core to notify the host computer of the step of power down operation, the processor further implements the steps of:

the host sends Nvme custom commands to obtain the saved exception log.

The storage medium may be a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, or other various computer-readable storage media that can store program codes.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The integrated unit may be stored in a storage medium if implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a terminal, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

The SSD power-down speed improving method is characterized by comprising the following steps:

when power is lost, log information is stored;

acquiring a VU command sent from a first core;

transmitting information corresponding to the VU command to a third core, so that the third core writes the information corresponding to the VU command into the NAND Flash, and the power-down operation is completed;

the obtaining a transmit VU command from a first core includes:

polling the VU command through the shared FIFO;

the step of sending the information corresponding to the VU command to the third core so that the third core writes the information corresponding to the VU command into the NAND Flash to complete the power-down operation, including:

transmitting information corresponding to the VU command to a third core, and writing the information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state;

judging whether the writing completion state is a data writing error or not by a third core;

if the writing completion state is a data writing error, the third core wakes up the second core through interruption, so that the second core transmits data once again for writing, if the data writing error occurs, abnormal data is recorded, a specific field is juxtaposed, and the third core informs the host to perform power-down operation;

if the write completion status is not a data write error, the third core notifies the host to perform a power down operation.
2. The SSD power down speed improvement method of claim 1, wherein the information corresponding to the VU command includes a logical-physical mapping table and written data.
3. The SSD power down speed improvement method of claim 1, wherein the sending the information corresponding to the VU command to a third core, the third core writing the information corresponding to the VU command into the NAND Flash to obtain the write-complete state, further comprising:

transmitting information corresponding to the VU command to a third core to obtain a transmission result;

judging whether the sending result is not submitted to completion;

if the sending result is that the power failure is not completed, an exception log is saved, and a specific field is set for the host to perform the power failure operation according to the specific field;

if the sending result is not the non-submitted completion, writing information corresponding to the VU command into the NAND Flash by the third core to obtain a writing completion state.
4. The SSD power down speed improvement method of claim 1, wherein the third core, after notifying the host of the power down operation, further comprises:

the host sends Nvme custom commands to obtain the saved exception log.
SSD power down speed improving device, its characterized in that includes:

the information storage unit is used for storing log information when power is lost;

a command acquisition unit for acquiring a VU command transmitted from the first core;

the information sending unit is used for sending information corresponding to the VU command to the third core so that the third core writes the information corresponding to the VU command into the NAND Flash to finish power-down operation;

the information storage unit is used for polling the VU command through the shared FIFO;

the information sending unit is used for sending information corresponding to the VU command to a third core, and the third core writes the information corresponding to the VU command into the NAND Flash to obtain a writing completion state; judging whether the writing completion state is a data writing error or not by a third core; if the writing completion state is a data writing error, the third core wakes up the second core through interruption, so that the second core transmits data once again for writing, if the data writing error occurs, abnormal data is recorded, a specific field is juxtaposed, and the third core informs the host to perform power-down operation; if the writing completion state is not the data writing error, the third core informs the host to perform power-down operation, and the host sends an Nvme custom command to acquire the saved exception log.
6. A computer device, characterized in that it comprises a memory on which a computer program is stored and a processor which, when executing the computer program, implements the method according to any of claims 1-4.
7. A storage medium storing a computer program which, when executed by a processor, performs the method of any one of claims 1 to 4.