CN111902873A - 2T2R resistive random access memory with differential architecture, MCU and equipment - Google Patents
2T2R resistive random access memory with differential architecture, MCU and equipment Download PDFInfo
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Abstract
The application provides a 2T2R resistive random access memory with a differential architecture, an MCU and a device. The memory comprises a memory cell array formed by a plurality of memory cells; each memory cell comprises a first transistor, a second transistor, a first resistive switching device and a second resistive switching device; the grid electrode of the first transistor and the grid electrode of the second transistor are connected to the same word line, the source electrode of the first transistor and the source electrode of the second transistor are respectively connected to a first bit line and a second bit line, the drain electrode of the first transistor is connected with the first electrode of the first resistance change device, the drain electrode of the second transistor is connected with the first electrode of the second resistance change device, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are connected to the same source line; the first electrodes of the first resistance changing device and the second resistance changing device are located in the same layer, and the second electrodes of the first resistance changing device and the second resistance changing device are located in the same layer. So that the reliability of the memory can be guaranteed.
Description
The present application relates to the field of semiconductor memory technologies, and in particular, to a 2T2R resistive random access memory with a differential architecture, a Micro Controller Unit (MCU) and a device.
A Resistive Random Access Memory (RRAM) is a novel Non-volatile Memory (NVM) that uses the characteristic of variable resistance of a device to store data, and has attracted attention because of its advantages of low operating power consumption, fast read/write speed, and the like.
Typically, RRAMs include: a common memory cell structure of an array of a plurality of memory cells includes 1T1R, 1D1R, 1S1R, etc., where T refers to a Transistor (Transistor), R refers to a Resistive Switching Device (Resistive Switching Device), and D refers to a Diode (Diode). Fig. 1 is a schematic diagram of a memory cell array of a 1T1R structure provided in the prior art, and as shown in fig. 1, each memory cell 10 is composed of a transistor (T)11 and a resistive device (R)12 connected in series. The resistive device 12 is generally composed of an electrode 120, a resistive layer 121, and an electrode 122, and the Resistance value thereof changes with the change of an applied voltage, and can be divided into a Low Resistance State (LRS) and a High Resistance State (HRS) according to the Resistance value, and can correspond to logical "1" and "0". The process of writing the low resistance state is called set, and the specific steps are as follows: the corresponding row is selected through a Word Line (WL), a starting voltage is applied to the word line to start the transistors of the row, an operation voltage is applied to the Bit Line (BL) of the corresponding column, the Source Line (SL) of the corresponding column is grounded, and the set process of the RRAM can be completed through the voltage on the bit line. The process of writing the high resistance state is called reset, which is similar to the process of writing the low resistance state except that the operating voltage is applied to the source line of the corresponding column and the bit line is grounded. The reading process of the state of the memory cell (i.e. the resistance change device 12 is in the low resistance state or the high resistance state) is as follows: and selecting the corresponding row through the word line, grounding the source line of the corresponding column, and applying a reading voltage on the bit line to finish the reading process of the low-resistance state or the high-resistance state.
However, the resistive random access memory has many problems in the prior art, such as: various parasitics and line noises existing in the resistive random access memory can adversely affect the reading of a high-resistance state or a low-resistance state, so that the problem of low reliability of the resistive random access memory is caused.
Disclosure of Invention
The application provides a 2T2R resistive random access memory with a differential architecture, an MCU and a device. The 2T2R resistive random access memory can counteract the negative effects caused by various parasitic parameters and line noise in the memory, so that the reliability of the 2T2R resistive random access memory is improved.
In a first aspect, the present application provides a 2T2R resistive random access memory having a differential architecture, including: a memory cell array including a plurality of 2T2R resistance change memory cells; each 2T2R resistive random access memory unit comprises a first transistor, a second transistor, a first resistive random access device and a second resistive random access device; the grid electrode of the first transistor and the grid electrode of the second transistor are connected to the same word line, the source electrode of the first transistor and the source electrode of the second transistor are respectively connected to a first bit line and a second bit line, the drain electrode of the first transistor is connected with the first electrode of the first resistance change device, the drain electrode of the second transistor is connected with the first electrode of the second resistance change device, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are connected to the same source line; the first electrode of the first resistance change device and the first electrode of the second resistance change device are located on the same layer, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are located on the same layer. The connection mode of the first resistive switching device and the second resistive switching device may be referred to as a same-direction connection mode.
On one hand, due to the structural design of the 2T2R resistive random access memory, negative effects caused by various parasitic parameters and line noise in the memory can be counteracted, and the reading of high and low resistance states is more accurate and stable. On the other hand, the problem of poor consistency of the memory cells can be effectively solved through the structural design of the 2T2R resistive random access memory. In addition, the requirement of the memory cell with the 2T2R structure on the process consistency is reduced compared with the memory cell with the 1T1R structure. Furthermore, due to the same-direction connection mode of the two resistance change devices, the 2T2R resistance change type memory is simpler in circuit design and easy to realize in process.
In a second aspect, the present application provides an MCU, wherein the MCU has a 2T2R resistive random access memory as described in the first aspect. The effect can be referred to the effect of the 2T2R resistive random access memory.
In one possible design, the MCU is configured to control the charging unit to apply a turn-on voltage to the word line to turn on the first transistor and the second transistor, control the charging unit to apply a first operating voltage to the first bit line, and apply a second operating voltage to the second bit line; the first operating voltage is different from the second operating voltage, the voltage difference of the first operating voltage relative to the voltage on the source line enables the first resistive random access device to be changed from a high-resistance state to a low-resistance state, and the voltage difference of the second operating voltage relative to the voltage on the source line enables the second resistive random access device to be changed from the low-resistance state to the high-resistance state; alternatively, a voltage difference of the first operating voltage with respect to a voltage on the source line causes the first resistive switching device to change from a low resistance state to a high resistance state, and a voltage difference of the second operating voltage with respect to a voltage on the source line causes the second resistive switching device to change from a high resistance state to a low resistance state.
In one possible design, the MCU is configured to control the charging unit to charge the first bit line and the second bit line so that voltages of the first bit line and the second bit line reach a same read voltage, control the charging unit to stop charging the first bit line and the second bit line after a preset time, control the charging unit to apply a voltage to the source line, apply a turn-on voltage to the word line to turn on the first transistor and the second transistor so that the first bit line and the second bit line start to discharge, obtain relative resistance values of the first resistive switching device and the second resistive switching device according to a discharge speed of the first bit line and the second bit line, and determine a state of the 2T2R resistive switching memory cell according to the relative resistance values of the first resistive switching device and the second resistive switching device.
In one possible design, the voltage applied on the source line is less than the read voltage, and the difference between the read voltage and the voltage applied on the source line is less than a preset threshold, where the preset threshold may be 0.2 volts or 0.1 volts. Therefore, the state change of the resistance change device caused by overlarge voltage difference can be avoided.
In one possible design, the state of the 2T2R resistive random access memory unit is that the first resistive random access device is in a high-resistance state relative to the second resistive random access device, and the second resistive random access device is in a low-resistance state relative to the first resistive random access device; or the first resistive switching device is in a low resistance state relative to the second resistive switching device, and the second resistive switching device is in a high resistance state relative to the first resistive switching device.
In a third aspect, the present application provides an apparatus comprising: a 2T2R resistive switching memory as described in the first aspect.
In a fourth aspect, the present application provides an apparatus comprising: the MCU as described in the first aspect.
The application provides a 2T2R resistive random access memory with a differential architecture, an MCU and a device. Firstly, due to the structural design of the 2T2R resistive random access memory, the negative effects caused by various parasitic parameters and line noise in the memory can be counteracted, and the reading of high and low resistance states is more accurate and stable. Secondly, the problem of poor consistency of the memory cells can be effectively solved through the structural design of the 2T2R resistive random access memory. Third, the memory cell of the 2T2R structure also has reduced process uniformity requirements as compared to the memory cell of the 1T1R structure. Fourthly, due to the same-direction connection mode of the two resistance change devices, the 2T2R resistance change type memory is simpler in circuit design and easy to achieve in process. In addition, compared with an SRAM, the 2T2R resistive random access memory with the differential architecture has the advantages of high storage density and data power-down retention.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a memory cell array of a 1T1R structure provided in the prior art;
FIG. 2A is a schematic diagram of a memory cell array of the 2T2R structure provided herein;
fig. 2B is a schematic diagram of a 2T2R resistive random access memory cell according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of an MCU provided in an embodiment of the present application;
fig. 4 is a timing diagram of a word line WL, a source line SL, a first bit line BL, and a second bit line BLB during writing of a memory state of a memory cell according to an embodiment of the present disclosure;
fig. 5 is a timing diagram of a word line WL, a source line SL, a first bit line BL, and a second bit line BLB during reading of a memory state of a memory cell according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an apparatus 60 provided in an embodiment of the present application.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described above, the conventional resistive random access memory has many problems in the art. First, various parasitics and line noises existing inside the resistive random access memory may adversely affect reading of a high resistance state or a low resistance state, thereby causing a problem of low reliability of the resistive random access memory. Secondly, the consistency (uniformity) of the resistive random access memory is not good enough at present, and the consistency is related to the generation and disappearance of a conductive filament (conductive film), which is the working mechanism of the resistive random access memory, with certain randomness and uncontrollable controllability. Especially after the current resistive random access memory goes through thousands of cycles (generally, one set plus one reset operation is called as one cycle), the problem of consistency of the high resistance state resistance value distribution is more prominent. For example: for a 1Kb resistive random access memory, along with the increase of the cycle number, the proportion of the memory cells with high resistance state close to low resistance state is continuously increased, and the reduction of the difference between the high resistance state and the low resistance state puts high requirements on the reading of the high resistance state and the low resistance state. Third, the resistive random access memory with the 1T1R structure is sensitive to process conditions, and even on the same wafer, memory cells at different positions may exhibit different resistive random behaviors due to process fluctuation, thereby further increasing the difficulty in reading high and low resistance states.
In order to solve the technical problem, the application provides a 2T2R resistive random access memory with a differential architecture, an MCU and a device.
The main idea of the application is as follows: the application provides a 2T2R resistive random access memory with a differential architecture, and the 2T2R resistive random access memory has a symmetrical structure of 2T2R and specifically comprises a first transistor (T1), a second transistor (T2), a first resistive random access device (R1) and a second resistive random access device (R2). The gates (Gate) of T1 and T2 are connected to the same Word Line (WL), the sources (Source) are connected to two different bit lines (BL and BLB), and the drains (Drain) are connected to one electrode of R1 and R2, respectively, such as BE. The other electrodes of R1 and R2, e.g., TE, are connected to the same Source Line (SL). The first resistive switching device (R1) and the second resistive switching device (R2) are connected in the same direction. For the 2T2R resistive random access memory, the MCU can determine the state of the memory cell by the relative sizes of the resistances of the two resistive random access devices. On one hand, due to the structural design of the 2T2R resistive random access memory, negative effects caused by various parasitic parameters and line noise in the memory can be counteracted, and the reading of high and low resistance states is more accurate and stable. On the other hand, the problem of poor consistency of the memory cells can be effectively solved through the structural design of the 2T2R resistive random access memory. In addition, the requirement of the memory cell with the 2T2R structure on the process consistency is reduced compared with the memory cell with the 1T1R structure. Furthermore, due to the same-direction connection mode of the two resistance change devices, the 2T2R resistance change type memory is simpler in circuit design and easy to realize in process.
Specifically, the 2T2R resistive random access memory with a differential architecture comprises: and a memory cell array including a plurality of 2T2R resistance change memory cells. Fig. 2A is a schematic diagram of a memory cell array with a 2T2R structure provided in the present application, and as shown in fig. 2A, two ends of a 2T2R resistive random access memory cell 20 located in the same row are respectively connected to one WL and one SL, and two ends of a 2T2R resistive random access memory cell 20 located in the same column are respectively connected to one BL and one BLB. Fig. 2B is a schematic diagram of a 2T2R resistive switching memory cell according to an embodiment of the present disclosure, and as shown in fig. 2B, the 2T2R resistive switching memory cell includes a first transistor 21, a second transistor 22, a first resistive switching device 23, and a second resistive switching device 24. The gate 210 of the first transistor 21 and the gate 220 of the second transistor 22 are connected to the word line 25; the source 211 of the first transistor 21 and the source 221 of the second transistor 22 are connected to the first bit line 26 and the second bit line 27, respectively; the drain 212 of the first transistor 21 and the drain 222 of the second transistor 22 are connected to the first electrode 231 of the first resistive switching device 23 and the first electrode 241 of the second resistive switching device 24, respectively; the second electrode 232 of the first resistive device 23 and the second electrode 242 of the second resistive device 24 are connected to the source line 28, the first electrode 231 of the first resistive device 23 and the first electrode 241 of the second resistive device 24 are located in the same layer, and the second electrode 232 of the first resistive device 23 and the second electrode 242 of the second resistive device 24 are located in the same layer. That is, the first electrode 231 of the first resistive switching device 23 is prepared prior to the second electrode 232 of the first resistive switching device 23, and the first electrode 241 of the second resistive switching device 24 is prepared prior to the second electrode 242 of the second resistive switching device 24. Or the first electrode 231 of the first resistive device 23 is prepared after the second electrode 232 of the first resistive device 23, and the first electrode 241 of the second resistive device 24 is prepared after the second electrode 242 of the second resistive device 24. The circuit design of the same-direction connection mode is more simplified, and the process is easy to realize.
The MCU may determine the state of the 2T2R resistive switching memory cell by reading the relative resistance values of the first resistive switching device 23 and the second resistive switching device 24, for example: the first resistive switching device 23 is in a high resistance state with respect to the second resistive switching device 24, and the second resistive switching device 24 is in a low resistance state with respect to the first resistive switching device 23, or the first resistive switching device 23 is in a low resistance state with respect to the second resistive switching device 24, and the second resistive switching device 24 is in a high resistance state with respect to the first resistive switching device 23. This reading method can be referred to as differential reading, and since the 2T2R resistive memory cell can implement differential reading, the memory cell can be referred to as a memory cell having a "differential architecture".
In addition, compared with the conventional resistive random access memory with the 1T1R structure, although the area of the memory cell in the resistive random access memory with the 2T2R structure is doubled, the beneficial effect is also great, that is, the reliability and stability of reading the state of the memory cell can be greatly improved through the structural design. Specifically, for the memory cell with the 1T1R structure, the absolute value of the resistance of a single resistive device is read, and due to the influence of many factors, such as the uniformity of the resistance distribution of the resistive devices, line noise, process fluctuation, etc., a data reading error often occurs, for example, a high resistance state with an abnormally low resistance is mistaken for a low resistance state, or a low resistance state with an abnormally high resistance is mistaken for a high resistance state. In the resistive random access memory with the 2T2R structure, as long as the resistance states of the two resistive random access devices in the memory cell are always opposite after certain initialization, that is, "one low and one high", but cannot be "two low" or "two high". Based on the structural design of the memory cell, the resistance value of a single resistance change device is not read by the MCU, but the relative sizes of the resistance values of two resistance change devices are used, so that the influence caused by the nonuniformity of the resistance value distribution can be minimized, and meanwhile, the influence of various parasitic parameters and line noise (mutual offset in the cell) is avoided, and the reliability and the stability of state reading of the memory cell can be greatly improved through the structural design; in addition, since the two resistive devices in the memory cell can be regarded as equivalent process conditions, the 2T2R resistive random access memory adopting the differential architecture also has relaxed requirement on consistency of process conditions.
The present application further provides an MCU, wherein the MCU includes: the 2T2R resistive random access memory described above. Specifically, fig. 3 is a schematic diagram of an MCU provided in an embodiment of the present application, and as shown in fig. 3, the 2T2R resistive random access memory 31 is integrated on the MCU 30.
As described above, the 2T2R resistive switching memory having a differential architecture includes: a memory cell array including a plurality of 2T2R resistance change memory cells; each 2T2R resistive random access memory unit comprises a first transistor, a second transistor, a first resistive random access device and a second resistive random access device; the gate of the first transistor and the gate of the second transistor are connected to the same word line, the source of the first transistor and the source of the second transistor are respectively connected to a first bit line and a second bit line, the drain of the first transistor is connected to the first electrode of the first resistive switching device, the drain of the second transistor is connected to the first electrode of the second resistive switching device, and the second electrode of the first resistive switching device and the second electrode of the second resistive switching device are connected to the same source line; the first electrode of the first resistance change device and the first electrode of the second resistance change device are located in the same layer, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are located in the same layer. That is, the first electrode of the first resistance change device is prepared before the second electrode of the first resistance change device, and the first electrode of the second resistance change device is prepared before the second electrode of the second resistance change device. Or the first electrode of the first resistance change device is prepared behind the second electrode of the first resistance change device, and the first electrode of the second resistance change device is prepared behind the second electrode of the second resistance change device.
In the present application, when the state of the memory cell in the 2T2R resistive random access memory is: the first resistive switching device is in a high-resistance state relative to the second resistive switching device, and the second resistive switching device is in a low-resistance state relative to the first resistive switching device; or the first resistive switching device is in a low resistance state relative to the second resistive switching device, and the second resistive switching device is in a high resistance state relative to the first resistive switching device.
The logic '0' indicates that the first resistive switching device is in a low-resistance state relative to the second resistive switching device, the second resistive switching device is in a high-resistance state relative to the first resistive switching device, and the logic '1' indicates that the first resistive switching device is in a high-resistance state relative to the second resistive switching device, and the second resistive switching device is in a low-resistance state relative to the first resistive switching device.
Alternatively, the first and second electrodes may be,
a logic "1" indicates that the first resistive switching device is in a low resistance state with respect to the second resistive switching state, the second resistive switching device is in a high resistance state with respect to the first resistive switching device, and a logic "0" indicates that the first resistive switching device is in a high resistance state with respect to the second resistive switching state, and the second resistive switching device is in a low resistance state with respect to the first resistive switching device.
The following describes the process of reading and writing the memory state of the 2T2R resistance change memory cell by the MCU:
assume that a logic "0" indicates that the first resistive switching device is in a low resistance state with respect to the second resistive switching state, the second resistive switching device is in a high resistance state with respect to the first resistive switching device, and a logic "1" indicates that the first resistive switching device is in a high resistance state with respect to the second resistive switching state, and the second resistive switching device is in a low resistance state with respect to the first resistive switching device. Assuming that an initial memory state of a 2T2R resistive random access memory cell is logic "0", taking writing logic "1" as an example, fig. 4 is a timing diagram of a word line WL, a source line SL, a first bit line BL, and a second bit line BLB in a writing process of a memory state of a memory cell provided in an embodiment of the present application, where a horizontal axis in fig. 4 represents time and a vertical axis represents voltage. The description will be made with reference to fig. 2B and 4. At time t1, the MCU controls the charging unit to apply the turn-on voltage VG on the word line 25 to turn on the first transistor 21 and the second transistor 22. Also at time t1, the MCU controls the charging unit to apply an operating voltage of VDD on the first bitline 26 and an operating voltage of the same magnitude, but opposite direction, VDD, on the second bitline 27. The source line 28 is grounded, and at this time, the first resistive switching device 23 connected to the first bit line 26 generates reset under the action of a voltage difference Δ V between two electrodes — VDD, and changes from a low-resistance state to a high-resistance state; the second resistive switching device 34 on the second bit line 27 generates set under the action of the voltage difference Δ V between the two electrodes, which is VDD, and changes from a high-resistance state to a low-resistance state. So far, the writing of the logic "1" is completed.
The method of writing a logic "0" is similar, except that the voltages applied to the two bit lines are interchanged.
Specifically, assume that a logic "0" indicates that the first resistive switching device is in a low resistance state with respect to the second resistive switching device, the second resistive switching device is in a high resistance state with respect to the first resistive switching device, and a logic "1" indicates that the first resistive switching device is in a high resistance state with respect to the second resistive switching device, and the second resistive switching device is in a low resistance state with respect to the first resistive switching device. Assuming that the initial memory state of a 2T2R resistive random access memory cell is logic "1", for example, writing logic "0", at time T1, the MCU controls the charging unit to apply a turn-on voltage VG to the word line 25 to turn on the first transistor 21 and the second transistor 22. Also at time t1, the MCU controls the charging unit to apply an operating voltage of-VDD to the first bitline 26 and an operating voltage VDD of the same magnitude but opposite direction to the second bitline 27. The source line 28 is grounded, and at this time, the first resistive switching device 23 connected to the first bit line 26 generates a set under the action of a voltage difference Δ V between two electrodes, and changes from a high-resistance state to a low-resistance state; the second resistive switching device 34 on the second bit line 27 generates reset under the action of a voltage difference Δ V between two electrodes — VDD, and changes from a low-resistance state to a high-resistance state. By this time, the writing of the logic "0" is completed.
Assume that a logic "0" indicates that the first resistive switching device is in a low resistance state with respect to the second resistive switching state, the second resistive switching device is in a high resistance state with respect to the first resistive switching device, and a logic "1" indicates that the first resistive switching device is in a high resistance state with respect to the second resistive switching state, and the second resistive switching device is in a low resistance state with respect to the first resistive switching device. Fig. 5 is a timing diagram of a word line WL, a source line SL, a first bit line BL, and a second bit line BLB during reading of a memory state of a memory cell according to an embodiment of the present application, in which a horizontal axis in fig. 5 represents time and a vertical axis represents voltage. The description will be made with reference to fig. 2B and 5. During reading logic "1", at time t0, the MCU controls the charging unit to precharge (precharge) the first bit line 26 and the second bit line 27 to the same reading voltage VRD until time t1, and then applies a voltage to the source line 28, and at the same time, applies the turn-on voltage VG to the word line 25 to turn on the first transistor 21 and the second transistor 22. It should be noted that the voltage applied to the source line 28 should be slightly less than the read voltage, for example, the voltage applied to the source line 28 is VRD-0.2 v, so that the state change of the resistive switching device caused by the excessive voltage difference can be avoided. The first bit line 26 and the second bit line 27 start discharging (discharge) from time t 1. Since the first resistance change device 23 is in a high resistance state, the discharge rate thereof is relatively slow; and the second resistive device 24 is in a low resistance state, and the discharge rate is relatively fast. The potentials on the first bit line 26 and the second bit line 27 are detected synchronously at time t2, the MCU compares the potentials, and the memory cell data is read as logic 1 because the potential of the first bit line 26 is higher than the potential of the second bit line 27. Similarly, if the potential of the first bit line 26 is lower than the potential of the second bit line 27, the data of the memory cell is read as "logic 0".
It should be noted that, the writing and reading modes of the 2T2R resistive Random Access Memory provided by the present application are closer to those of a conventional Static Random Access Memory (SRAM), for example, different voltages are applied to two bit lines in the writing process, and the precharging is adopted in the reading process, and then the discharging speed is compared, so that the 2T2R resistive Random Access Memory provided by the present application can be used to replace the SRAM without changing or slightly changing the design of the peripheral circuit.
Compared with an SRAM (static random access memory), the 2T2R resistive random access memory with the differential architecture has the following advantages:
first, the storage density is high. The SRAM is generally in a 6-transistor (6T) structure, while the 2T2R resistive random access memory has only 2 transistors, and the memory cell area is smaller.
And secondly, data power failure is maintained. The SRAM must keep the data consistently and supply power, and the data of the resistive random access memory cannot be lost in the case of power failure.
In summary, the 2T2R resistive random access memory with the differential architecture has a wide application prospect.
The application also provides a device, which can be an intelligent device such as a mobile phone, a tablet computer, a wearable device, and the like, and all devices having a memory are within the protection scope of the application, wherein the memory is the 2T2R resistive random access memory having the differential architecture. Fig. 6 is a schematic diagram of an apparatus 60 provided in an embodiment of the present application, as shown in fig. 6, the apparatus including: the memory comprises an MCU61, the 2T2R resistive random access memory 62 with the differential architecture, and a transceiver 63, wherein the transceiver 63 is used for data transmission with other devices.
As described above, the 2T2R resistive switching memory having a differential architecture includes: a memory cell array including a plurality of 2T2R resistance change memory cells; each 2T2R resistive random access memory unit comprises a first transistor, a second transistor, a first resistive random access device and a second resistive random access device; the grid electrode of the first transistor and the grid electrode of the second transistor are connected to the same word line, the source electrode of the first transistor and the source electrode of the second transistor are respectively connected to a first bit line and a second bit line, the drain electrode of the first transistor is connected with the first electrode of the first resistance change device, the drain electrode of the second transistor is connected with the first electrode of the second resistance change device, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are connected to the same source line; the first electrode of the first resistance change device and the first electrode of the second resistance change device are located on the same layer, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are located on the same layer.
In one possible design, the apparatus further includes: the charging unit is electrically connected with the 2T2R resistive random access memory with the differential architecture.
In one possible design, the MCU is configured to control the charging unit to apply a turn-on voltage to the word line to turn on the first transistor and the second transistor, control the charging unit to apply a first operating voltage to the first bit line, and apply a second operating voltage to the second bit line; the first operating voltage is different from the second operating voltage, the voltage difference of the first operating voltage relative to the voltage on the source line enables the first resistive random access device to be changed from a high-resistance state to a low-resistance state, and the voltage difference of the second operating voltage relative to the voltage on the source line enables the second resistive random access device to be changed from the low-resistance state to the high-resistance state; alternatively, a voltage difference of the first operating voltage with respect to a voltage on the source line causes the first resistive switching device to change from a low resistance state to a high resistance state, and a voltage difference of the second operating voltage with respect to a voltage on the source line causes the second resistive switching device to change from a high resistance state to a low resistance state.
In one possible design, the MCU is configured to control the charging unit to charge the first bit line and the second bit line so that voltages of the first bit line and the second bit line reach a same read voltage, control the charging unit to stop charging the first bit line and the second bit line after a preset time, control the charging unit to apply a voltage to the source line, apply a turn-on voltage to the word line to turn on the first transistor and the second transistor so that the first bit line and the second bit line start to discharge, obtain relative resistance values of the first resistive switching device and the second resistive switching device according to a discharge speed of the first bit line and the second bit line, and determine a state of the 2T2R resistive switching memory cell according to the relative resistance values of the first resistive switching device and the second resistive switching device.
In one possible design, the voltage applied to the source line is less than a read voltage, and the difference between the read voltage and the voltage applied to the source line is less than a preset threshold, which may be 0.2 volts or 0.1 volts.
The equipment that this application embodiment provided, it includes: the content and effect of the 2T2R resistive random access memory with the differential architecture can refer to the above embodiments, and details are not repeated here.
The present application further provides an apparatus comprising: the content and effect of the MCU integrated with the 2T2R resistive random access memory with the differential architecture can refer to the above embodiments, and are not described herein again.
Although the application is described by taking the example of integrating the above resistive random access memory on the MCU, those skilled in the art can understand that the application of the embedded memory is not limited to the MCU, but also includes various circuits or chips such as CPU, FPGA, DSP, ASIC, etc., or the resistive random access memory of the present invention can be widely applied to various socs.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
- A2T 2R resistive switching memory with a differential architecture, comprising: a memory cell array including a plurality of 2T2R resistance change memory cells; each 2T2R resistive random access memory unit comprises a first transistor, a second transistor, a first resistive random access device and a second resistive random access device;the gate of the first transistor and the gate of the second transistor are connected to the same word line, the source of the first transistor and the source of the second transistor are respectively connected to a first bit line and a second bit line, the drain of the first transistor is connected to the first electrode of the first resistive switching device, the drain of the second transistor is connected to the first electrode of the second resistive switching device, and the second electrode of the first resistive switching device and the second electrode of the second resistive switching device are connected to the same source line;the first electrode of the first resistance change device and the first electrode of the second resistance change device are located in the same layer, and the second electrode of the first resistance change device and the second electrode of the second resistance change device are located in the same layer.
- A MCU, wherein the MCU has thereon the 2T2R resistive switching memory with differential architecture as claimed in claim 1.
- MCU according to claim 2,the MCU is used for controlling the charging unit to apply a starting voltage on the word line so as to start the first transistor and the second transistor, controlling the charging unit to apply a first operating voltage on the first bit line and apply a second operating voltage on the second bit line;wherein the first operating voltage is different from a second operating voltage, a voltage difference of the first operating voltage relative to a voltage on the source line causes the first resistive switching device to change from a high resistance state to a low resistance state, and a voltage difference of the second operating voltage relative to a voltage on the source line causes the second resistive switching device to change from a low resistance state to a high resistance state; or the first resistive switching device is changed from a low-resistance state to a high-resistance state by a voltage difference of the first operating voltage relative to a voltage on the source line, and the second resistive switching device is changed from the high-resistance state to the low-resistance state by a voltage difference of the second operating voltage relative to the voltage on the source line.
- MCU according to claim 2,the MCU is used for controlling the charging unit to charge on the first bit line and the second bit line so that the voltages of the first bit line and the second bit line reach the same reading voltage, controlling the charging unit to stop charging the first bit line and the second bit line after a preset time, controlling the charging unit to apply a voltage on the source line, applying a starting voltage on the word line to start the first transistor and the second transistor so that the first bit line and the second bit line start to discharge, acquiring the relative resistance values of the first resistive switching device and the second resistive switching device according to the discharge speed of the first bit line and the second bit line, and determining the state of the 2T2R resistive switching type memory cell according to the relative resistance values of the first resistive switching device and the second resistive switching device.
- The MCU of claim 4, wherein the voltage applied on the source line is less than the read voltage, and wherein the difference between the read voltage and the voltage applied on the source line is less than a preset threshold.
- The MCU of claim 4 or 5, wherein the 2T2R resistive switching memory cell is in a state in which the first resistive switching device is in a high resistive state with respect to the second resistive switching device, and the second resistive switching device is in a low resistive state with respect to the first resistive switching device; or the first resistive switching device is in a low resistance state relative to the second resistive switching device, and the second resistive switching device is in a high resistance state relative to the first resistive switching device.
- An apparatus, comprising: the 2T2R resistive switching memory having a differential architecture as defined in claim 1.
- An apparatus, comprising: the MCU of claim 2.
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| PCT/CN2019/077093 WO2020177089A1 (en) | 2019-03-06 | 2019-03-06 | 2t2r resistive random access memory with differential architecture, and mcu and device |
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| US8947909B1 (en) * | 2012-10-05 | 2015-02-03 | Marvell International Ltd. | System and method for creating a bipolar resistive RAM (RRAM) |
| JP6021688B2 (en) * | 2013-02-25 | 2016-11-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device and control method thereof |
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| CN101872647A (en) * | 2009-04-27 | 2010-10-27 | 复旦大学 | One-time programming resistance random memory unit, array, memory and operation method thereof |
| US20110063902A1 (en) * | 2009-09-17 | 2011-03-17 | Macronix International Co., Ltd. | 2t2r-1t1r mix mode phase change memory array |
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