CN111902873A - 2T2R resistive random access memory with differential architecture, MCU and equipment - Google Patents
2T2R resistive random access memory with differential architecture, MCU and equipment Download PDFInfo
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- CN111902873A CN111902873A CN201980000337.3A CN201980000337A CN111902873A CN 111902873 A CN111902873 A CN 111902873A CN 201980000337 A CN201980000337 A CN 201980000337A CN 111902873 A CN111902873 A CN 111902873A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
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- Static Random-Access Memory (AREA)
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Abstract
本申请提供一种具有差分架构的2T2R阻变式存储器、MCU及设备。该存储器包括多个存储单元构成的存储单元阵列；每个存储单元包括第一晶体管、第二晶体管、第一阻变器件和第二阻变器件；第一晶体管的栅极和第二晶体管的栅极连接在同一根字线上，第一晶体管的源极和第二晶体管的源极分别连接在第一位线和第二位线上，第一晶体管的漏极与第一阻变器件的第一电极连接，第二晶体管的漏极与第二阻变器件的第一电极连接，第一阻变器件的第二电极和第二阻变器件的第二电极连接在同一根源线上；第一阻变器件与第二阻变器件的第一电极位于同一层，第一阻变器件与第二阻变器件的第二电极位于同一层。从而可以保证所述存储器的可靠性。
The present application provides a 2T2R resistive memory, MCU and device with a differential architecture. The memory includes a memory cell array composed of a plurality of memory cells; each memory cell includes a first transistor, a second transistor, a first resistive device and a second resistive device; the gate of the first transistor and the gate of the second transistor The electrode is connected to the same word line, the source electrode of the first transistor and the source electrode of the second transistor are connected to the first bit line and the second bit line respectively, and the drain electrode of the first transistor is connected to the second bit line of the first resistive device. An electrode is connected, the drain of the second transistor is connected to the first electrode of the second resistive device, and the second electrode of the first resistive device and the second electrode of the second resistive device are connected to the same root line; the first The resistive switching device and the first electrode of the second resistive switching device are located on the same layer, and the first resistive switching device and the second electrode of the second resistive switching device are located on the same layer. Thus, the reliability of the memory can be guaranteed.
Description
PCT国内申请，说明书已公开。PCT domestic application, the description has been published.
Claims (8)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2019/077093 WO2020177089A1 (en) | 2019-03-06 | 2019-03-06 | 2t2r resistive random access memory with differential architecture, and mcu and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111902873A true CN111902873A (en) | 2020-11-06 |
| CN111902873B CN111902873B (en) | 2021-11-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980000337.3A Active CN111902873B (en) | 2019-03-06 | 2019-03-06 | 2T2R resistive random access memory with differential architecture, MCU and equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111902873B (en) |
| WO (1) | WO2020177089A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115701637A (en) * | 2021-08-02 | 2023-02-10 | 中国科学院微电子研究所 | Memory computing circuit and method and resistive random access memory |
| CN117157990A (en) * | 2021-04-12 | 2023-12-01 | 特忆智能科技 | Artificial intelligent pixel sensor based on memristor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11069742B2 (en) * | 2019-11-23 | 2021-07-20 | Tetramem Inc. | Crossbar array circuit with parallel grounding lines |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872647A (en) * | 2009-04-27 | 2010-10-27 | 复旦大学 | One-time programming resistance random access memory cell, array, memory and method of operation thereof |
| US20110063902A1 (en) * | 2009-09-17 | 2011-03-17 | Macronix International Co., Ltd. | 2t2r-1t1r mix mode phase change memory array |
| CN207009083U (en) * | 2017-07-13 | 2018-02-13 | 高科创芯(北京)科技有限公司 | Double deference negative-feedback data reading circuit based on memristor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006099866A (en) * | 2004-09-29 | 2006-04-13 | Sony Corp | Storage device and semiconductor device |
| CN102169719A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof |
| CN102368536A (en) * | 2011-11-25 | 2012-03-07 | 北京大学 | Resistive random access memory (RRAM) unit |
| US8947909B1 (en) * | 2012-10-05 | 2015-02-03 | Marvell International Ltd. | System and method for creating a bipolar resistive RAM (RRAM) |
| JP6021688B2 (en) * | 2013-02-25 | 2016-11-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device and control method thereof |
-
2019
- 2019-03-06 WO PCT/CN2019/077093 patent/WO2020177089A1/en active Application Filing
- 2019-03-06 CN CN201980000337.3A patent/CN111902873B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872647A (en) * | 2009-04-27 | 2010-10-27 | 复旦大学 | One-time programming resistance random access memory cell, array, memory and method of operation thereof |
| US20110063902A1 (en) * | 2009-09-17 | 2011-03-17 | Macronix International Co., Ltd. | 2t2r-1t1r mix mode phase change memory array |
| CN207009083U (en) * | 2017-07-13 | 2018-02-13 | 高科创芯(北京)科技有限公司 | Double deference negative-feedback data reading circuit based on memristor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117157990A (en) * | 2021-04-12 | 2023-12-01 | 特忆智能科技 | Artificial intelligent pixel sensor based on memristor |
| CN115701637A (en) * | 2021-08-02 | 2023-02-10 | 中国科学院微电子研究所 | Memory computing circuit and method and resistive random access memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111902873B (en) | 2021-11-09 |
| WO2020177089A1 (en) | 2020-09-10 |
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Effective date of registration: 20250526 Address after: No. 667 Zhongshan Avenue, Jiang'an District, Wuhan City, Hubei Province 430010 Patentee after: Wuhan xunzhiyun Technology Co.,Ltd. Country or region after: China Address before: 13 / F, block B, Tengfei Industrial Building, Futian Free Trade Zone, Shenzhen, Guangdong 518045 Patentee before: SHENZHEN GOODIX TECHNOLOGY Co.,Ltd. Country or region before: China |
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