CN111900093A - 一种bcb薄膜太赫兹电路及其制作方法 - Google Patents

一种bcb薄膜太赫兹电路及其制作方法 Download PDF

Info

Publication number
CN111900093A
CN111900093A CN202010671626.0A CN202010671626A CN111900093A CN 111900093 A CN111900093 A CN 111900093A CN 202010671626 A CN202010671626 A CN 202010671626A CN 111900093 A CN111900093 A CN 111900093A
Authority
CN
China
Prior art keywords
bcb
circuit
manufacturing
terahertz
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010671626.0A
Other languages
English (en)
Inventor
牛斌
范道雨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Zhongdian Xingu High Frequency Device Industry Technology Research Institute Co ltd
Original Assignee
Nanjing Zhongdian Xingu High Frequency Device Industry Technology Research Institute Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing Zhongdian Xingu High Frequency Device Industry Technology Research Institute Co ltd filed Critical Nanjing Zhongdian Xingu High Frequency Device Industry Technology Research Institute Co ltd
Priority to CN202010671626.0A priority Critical patent/CN111900093A/zh
Publication of CN111900093A publication Critical patent/CN111900093A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种BCB薄膜太赫兹电路及其制作方法,方法包括:1)在半导体衬底上外延生长带有腐蚀停止层的太赫兹二极管或三极管外延材料,2)完成二极管、三极管等有源器件及电阻、电容等无源器件工艺制作,3)旋涂总厚度覆盖所有片上器件的BCB并固化,4)在所有器件电极接触上方处制作BCB通孔,5)在BCB上方制作电路金属布线,连接BCB通孔中的器件电极,6)完全去除半导体衬底及腐蚀停止层,完成BCB薄膜太赫兹电路制作。通过本方法可制作微米级厚度的BCB薄膜电路金属布线基板,且BCB材料具有极低的介电常数及太赫兹损耗,可提高太赫兹电路性能。

Description

一种BCB薄膜太赫兹电路及其制作方法
技术领域
本发明属于半导体集成电路领域,具体涉及一种BCB薄膜太赫兹电路及其制作方法。
背景技术
太赫兹(THz)科学技术是近二十年来迅速发展的一个新兴交叉学科和研究热点,涉及电磁学、光电子学、光学、半导体物理学、材料科学、生物、医学等多门科学。太赫兹频段覆盖电磁频谱的0.3THz~3THz频率范围,是一个蕴含着丰富物理内涵的宽频段电磁辐射区域。在近乎所有的太赫兹技术应用系统中,基于半导体工艺的太赫兹二极管如GaAs SBD、GaN SBD等,三极管如GaAs HEMT、InP HEMT、InP HBT等及其集成电路,是构成太赫兹发射极、接收、处理的核心技术。
目前太赫兹集成电路整体结构仍与传统半导体集成电路近似,在半导体衬底上制作器件与布线,完成正面工艺后将衬底减薄至几十微米至百微米厚度进行解理完成芯片制作,即使最新的薄膜太赫兹集成电路工艺,仍有几微米厚的半导体材料作为电路基板。然而在太赫兹频段下,半导体材料如GaAs、InP、GaN等,一般具有较大的微波损耗角正切,以及较高的介电常数。一方面直接带来了片上太赫兹波导的传输损耗,另一方面高介电常数电路半导体基板存在干扰波导模式设计,引起寄生电容等问题,限制高频段(工作频率≥0.5THz)太赫兹电路性能。
苯并环丁烯(BCB)介质具有极低介电常数(约2.65),介质损耗角正切约为0.0008,而一般的GaAs衬底介电常数约为12.9,介质损耗角正切约为0.006。并且BCB材料厚度可通过旋涂、固化的方式达到微米级。另一方面,由于高频段太赫兹电路尺寸一般相比中低频段太赫兹电路尺寸较小,小尺寸电路对电路基板机械强度要求降低,掩盖了BCB作为太赫兹电路基板的弱点。可见BCB比传统半导体材料更适合作为太赫兹电路基板,尤其是工作在高太赫兹频段太赫兹电路基板。
发明内容
本发明的目的在于提供一种BCB薄膜太赫兹电路及其制作方法,降低芯片上太赫兹波传输损耗,降低寄生电容,减小电路基板介电常数对太赫兹模式的干扰。
实现本发明目的的技术解决方案为:一种BCB薄膜太赫兹电路制作方法,包括以下步骤:
1)在半导体衬底上外延生长带有腐蚀停止层的太赫兹二极管或三极管外延材料;
2)完成有源器件及无源器件工艺制作;
3)旋涂总厚度覆盖所有片上器件的BCB并固化;
4)在所有器件电极接触上方处制作BCB通孔;
5)在BCB上方制作电路金属布线,连接BCB通孔中的器件电极;
6)完全去除半导体衬底以及腐蚀停止层,完成BCB薄膜太赫兹电路制作。
本发明还提供一种BCB薄膜太赫兹电路,包括有源器件、无源器件、覆盖有源器件及无源器件的BCB;
所述有源器件、无源器件电极上方设有BCB通孔,BCB上方设有电路金属布线,连接BCB通孔中的器件电极。
与现有技术相比,本发明的显著优点为:通过制作BCB薄膜将有源、无源器件包裹,将电路金属布线制作在BCB薄膜上,并完全去除半导体衬底,降低芯片上太赫兹波传输损耗,降低寄生电容,减小电路基板介电常数对太赫兹模式的干扰,该方法可有效提高太赫兹电路,尤其是高太赫兹频段电路性能。
附图说明
图1是在半导体衬底上外延生长腐蚀停止层及器件功能层后的剖面图。
图2是制作完二极管、三极管等有源器件及电阻、电容等无源器件工艺的剖面图。
图3是旋涂总厚度覆盖所有片上器件的BCB并固化后的剖面图。
图4是完成在所有器件电极接触上方处制作BCB通孔后的剖面图。
图5是完成在BCB上方制作电路金属布线及器件互联的剖面图。
图6是完全去除半导体衬底及腐蚀停止层,完成BCB薄膜太赫兹电路制作后的剖面图。
具体实施方式
如图1~图5所示,一种BCB薄膜太赫兹电路制作方法,包括以下步骤:
1)在半导体衬底上外延生长带有腐蚀停止层的太赫兹二极管或三极管外延材料;
2)完成二极管、三极管等有源器件及电阻、电容等无源器件制作工艺;
3)旋涂总厚度覆盖所有片上器件的BCB并固化;
4)所有器件电极接触上方处制作BCB通孔;
5)在BCB上方制作电路金属布线,连接BCB通孔中的器件电极;
6)完全去除半导体衬底及腐蚀停止层,完成BCB薄膜太赫兹电路制作。
进一步的,步骤4)通过光刻、干法刻蚀,在所有有源、无源器件电极上方制作出BCB通孔,露出器件电极。
进一步的,步骤5)通过光刻、蒸发剥离,或者电镀的方式,在BCB上及BCB通孔中制作电路金属布线,连接BCB通孔中的器件电极。
进一步的,步骤6)通过机械研磨、抛光、化学腐蚀的方法将半导体衬底及腐蚀停止层全部去除。
本发明还提供一种BCB薄膜太赫兹电路,如图6所示,包括有源器件、无源器件、覆盖有源器件及无源器件的BCB;所述有源器件、无源器件电极上方设有BCB通孔,BCB上方设有电路金属布线,连接BCB通孔中的器件电极。
所述有源器件包括二极管、三极管,所述无源器件包括电阻、电容。
通过该方法制作的太赫兹电路没有半导体衬底,微米级BCB薄膜替代原半导体衬底成为集成电路结构的支撑,实现芯片上太赫兹波传输损耗的降低,降低寄生电容,减小电路基板介电常数对太赫兹模式的干扰。
下面以GaAs SBD太赫兹集成电路为实例,结合附图,进一步说明本发明的技术方案。
实施例
一种BCB薄膜太赫兹电路制作方法,具体方法如下:
1)在半绝缘GaAs衬底上,进行材料外延,包括腐蚀停止层、GaAs功能层,本实施例中腐蚀停止层为InGaP,GaAs功能层为n+GaAs及n-GaAs。剖面图如图1所示。
2)在器件功能层上进行GaAs SBD器件工艺制作,并在腐蚀停止层上进行电容、电阻等无源器件工艺制作,剖面图如图2所示。
3)在晶圆正面旋涂BCB,厚度足够覆盖GaAs有源器件及电容、电阻等无源器件,并进行BCB固化,剖面图如图3所示。
4)通过光刻、干法刻蚀,在所有有源、无源器件电极上方制作出BCB通孔,露出器件电极,剖面图如图4所示。
5)通过光刻、蒸发剥离,或者电镀的方式,在BCB上及BCB通孔中制作电路金属布线,连接BCB通孔中的器件电极,剖面图如图5所示。
6)通过机械研磨、抛光、化学腐蚀的方法将半绝缘GaAs衬底及腐蚀停止层全部去除,剩下以BCB薄膜太赫兹电路,剖面图如图6所示。

Claims (9)

1.一种BCB薄膜太赫兹电路制作方法,其特征在于,包括以下步骤:
1)在半导体衬底上外延生长带有腐蚀停止层的太赫兹二极管或三极管外延材料;
2)完成有源器件及无源器件工艺制作;
3)旋涂总厚度覆盖所有片上器件的BCB并固化;
4)在所有器件电极接触上方处制作BCB通孔;
5)在BCB上方制作电路金属布线,连接BCB通孔中的器件电极;
6)完全去除半导体衬底以及腐蚀停止层,完成BCB薄膜太赫兹电路制作。
2.根据权利要求1所述的BCB薄膜太赫兹电路制作方法,其特征在于,所述有源器件包括二极管、三极管。
3.根据权利要求1所述的BCB薄膜太赫兹电路制作方法,其特征在于,所述无源器件包括电阻、电容。
4.根据权利要求1所述的BCB薄膜太赫兹电路制作方法,其特征在于,步骤4)通过光刻、干法刻蚀,在所有有源、无源器件电极上方制作出BCB通孔,露出器件电极。
5.根据权利要求1所述的BCB薄膜太赫兹电路制作方法,其特征在于,步骤5)通过光刻、蒸发剥离,或者电镀的方式,在BCB上及BCB通孔中制作电路金属布线,连接BCB通孔中的器件电极。
6.根据权利要求1所述的BCB薄膜太赫兹电路制作方法,其特征在于,步骤6)通过机械研磨、抛光、化学腐蚀的方法将半导体衬底及腐蚀停止层全部去除。
7.一种BCB薄膜太赫兹电路,其特征在于,包括有源器件、无源器件,以及覆盖有源器件和无源器件的BCB;
所述有源器件、无源器件电极上方设有BCB通孔,BCB上方设有电路金属布线,连接BCB通孔中的器件电极。
8.根据权利要求7所述的BCB薄膜太赫兹电路,其特征在于,所述有源器件包括二极管、三极管。
9.根据权利要求7所述的BCB薄膜太赫兹电路,其特征在于,所述无源器件包括电阻、电容。
CN202010671626.0A 2020-07-14 2020-07-14 一种bcb薄膜太赫兹电路及其制作方法 Pending CN111900093A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010671626.0A CN111900093A (zh) 2020-07-14 2020-07-14 一种bcb薄膜太赫兹电路及其制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010671626.0A CN111900093A (zh) 2020-07-14 2020-07-14 一种bcb薄膜太赫兹电路及其制作方法

Publications (1)

Publication Number Publication Date
CN111900093A true CN111900093A (zh) 2020-11-06

Family

ID=73192554

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010671626.0A Pending CN111900093A (zh) 2020-07-14 2020-07-14 一种bcb薄膜太赫兹电路及其制作方法

Country Status (1)

Country Link
CN (1) CN111900093A (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1717847A2 (en) * 2005-04-28 2006-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102714176A (zh) * 2010-02-26 2012-10-03 住友化学株式会社 电子器件及电子器件的制造方法
CN103811364A (zh) * 2013-12-26 2014-05-21 中国电子科技集团公司第五十五研究所 一种实现基于bcb的磷化铟微波电路多层互联方法
CN111009466A (zh) * 2019-11-14 2020-04-14 中国电子科技集团公司第五十五研究所 一种材料结构倒置型异质衬底肖特基二极管电路制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1717847A2 (en) * 2005-04-28 2006-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN1870233A (zh) * 2005-04-28 2006-11-29 株式会社半导体能源研究所 半导体器件及其制造方法
CN102714176A (zh) * 2010-02-26 2012-10-03 住友化学株式会社 电子器件及电子器件的制造方法
CN103811364A (zh) * 2013-12-26 2014-05-21 中国电子科技集团公司第五十五研究所 一种实现基于bcb的磷化铟微波电路多层互联方法
CN111009466A (zh) * 2019-11-14 2020-04-14 中国电子科技集团公司第五十五研究所 一种材料结构倒置型异质衬底肖特基二极管电路制作方法

Similar Documents

Publication Publication Date Title
US10492301B2 (en) Method for manufacturing an integrated circuit package
US7763976B2 (en) Integrated circuit module with integrated passive device
US9666930B2 (en) Interface between a semiconductor die and a waveguide, where the interface is covered by a molding compound
US6746938B2 (en) Manufacturing method for semiconductor device using photo sensitive polyimide etching mask to form viaholes
US10411328B2 (en) Patch antenna structures and methods
CN108155092B (zh) 一种bcb辅助增强的肖特基二极管阳极空气桥制作方法
US20210305237A1 (en) Heterolithic microwave integrated circuits including gallium-nitride devices on intrinsic semiconductor
US20190229115A1 (en) Heterolithic microwave integrated circuits including gallium-nitride devices formed on highly doped semiconductor
US4673958A (en) Monolithic microwave diodes
US20200020681A1 (en) Heterolithic microwave integrated circuits including gallium-nitride devices on highly doped regions of intrinsic silicon
US6833606B2 (en) Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor
CN111540712A (zh) 集成器件制造方法及相关产品
CN115763446B (zh) 射频集成化设备及制备方法、包含其的收发机芯片
Mehdi et al. Fabrication and performance of planar Schottky diodes with T-gate-like anodes in 200-GHz subharmonically pumped waveguide mixers
CN111900093A (zh) 一种bcb薄膜太赫兹电路及其制作方法
US20230207558A1 (en) Microwave integrated circuits including gallium-nitride devices on silicon
CN111952161A (zh) 一种无衬底垂直型肖特基二极管的制作方法
US8426290B1 (en) Suspended-membrane/suspended-substrate monolithic microwave integrated circuit modules
KR20020070739A (ko) 단일 칩 고주파 집적회로 및 그 제조 방법
US20160181242A1 (en) Passive device and manufacturing method thereof
US7348864B2 (en) Integrated MMIC modules for millimeter and submillimeter wave system applications
JPS62211962A (ja) 高周波半導体装置の製造方法
CN111009466A (zh) 一种材料结构倒置型异质衬底肖特基二极管电路制作方法
JP6833691B2 (ja) 集積回路と製造の方法
US8344430B2 (en) Multiple substrate electrical circuit device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20201106