CN111884743B - FM broadcast intermediate frequency sampling demodulation system - Google Patents
FM broadcast intermediate frequency sampling demodulation system Download PDFInfo
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- CN111884743B CN111884743B CN202010744134.XA CN202010744134A CN111884743B CN 111884743 B CN111884743 B CN 111884743B CN 202010744134 A CN202010744134 A CN 202010744134A CN 111884743 B CN111884743 B CN 111884743B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/44—Arrangements characterised by circuits or components specially adapted for broadcast
- H04H20/46—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95
- H04H20/47—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems
- H04H20/48—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems for FM stereophonic broadcast systems
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Abstract
A frequency modulation broadcast intermediate frequency sampling demodulation system relates to the field of broadcast television, and solves the problem that the existing 10.7MHz intermediate frequency signal has too high frequency for a singlechip frequency measurement demodulation system and can not be directly measured, and comprises a tuner U1, a D trigger U2, a singlechip U3, a capacitor C1 and an oscillation circuit; the invention adopts a sampling method to realize the demodulation of a single-track program of frequency modulation broadcasting, only needs to use one DMA to arrange captured data into a memory, not only does not need to jointly use a plurality of DMAs, but also can obtain an audio sampling value by one-time calculation in an interrupt service program without circulation, thereby avoiding the need of circulating multiple collision detection in the interrupt service program of the existing frequency measurement demodulation system; compared with the existing system, the system has simple structure, and can sample the audio signal with higher frequency because of high execution efficiency.
Description
Technical Field
The invention relates to the field of broadcast television, in particular to a frequency modulation broadcast sampling demodulation system.
Background
According to national standard regulation of national frequency modulation broadcasting in China, frequency modulation is adopted for frequency modulation broadcasting programs, and the maximum frequency deviation is 75 KHz; the traditional program demodulation method is that a frequency discriminator is used for demodulating an intermediate frequency signal to obtain an audio frequency analog signal, and the audio frequency analog signal is converted into a digital sound data stream by an analog-to-digital converter after being amplified; the prior documents disclose a frequency modulation broadcast monitoring demodulation method for directly measuring the frequency by a single chip microcomputer, a frequency modulation broadcast frequency measurement demodulation electronic system, a frequency modulation stereo demodulation system of a single chip microcomputer frequency measurement type and a frequency modulation stereo frequency measurement decoding system, and provide a demodulation method for directly measuring the frequency by the single chip microcomputer or a digital circuit, and an input signal is required to be a low intermediate frequency of 1.25 MHz; in the industry standard of the traditional fm broadcast, the frequency of the if signal is 10.7MHz, which is much larger than the input range of the above direct fm demodulation.
Disclosure of Invention
The invention provides a frequency modulation broadcast intermediate frequency sampling demodulation system, aiming at solving the problem that the frequency of the existing 10.7MHz intermediate frequency signal is too high for a singlechip frequency measurement demodulation system and cannot be directly measured.
The FM broadcast intermediate frequency sampling demodulation system comprises a high frequency head U1, a D trigger U2, a singlechip U3, a capacitor C1 and an oscillating circuit; the OUT end of the tuner U1 is connected with a capacitor C1, and the capacitor C1 is connected with the input end of the oscillating circuit;
the output end of the oscillating circuit is connected with the D end of a D trigger U2, the Q end of the D trigger U2 is connected with the IN input end of a singlechip U3, and the TIM output end of the singlechip U3 is connected with the clock end C of the D trigger U2;
the single chip microcomputer U3 comprises a capture timer, a rising edge capture device, a DMA arbitrator, a capture register, a DMA controller, a memory, a sampling timer and a sampling timer;
the IN input end of the singlechip U3 is used as an intermediate frequency input end and is respectively connected with the rising edge capturer and the DMA arbitrator,
when a rising edge appears at the intermediate frequency input end, the rising edge capturer stores the value of the capture timer to the capture register and simultaneously initiates a DMA request to the DMA arbiter;
when the bus of the singlechip U3 has an idle cycle, the DMA arbiter informs the DMA controller to execute a DMA operation, and stores the value in the capture register into the memory;
the OUT end of the tuner U1 outputs FM broadcast intermediate frequency signals, the center frequency is 10.7MHz,
the sampling timer generates a 10MHz square wave signal, the square wave signal is output to the outside of the single chip microcomputer through a TIM output end of the single chip microcomputer U3, the D trigger U2 is driven to sample the signal output by the oscillating circuit, and the square wave signal obtained by sampling is output to an IN input end of the single chip microcomputer U3 from a Q end of the D trigger U2;
the sampling timer initiates interruption to the single chip microcomputer U3 at the frequency of 16KHz, the interruption service program calculates the program audio sampling value of the intermediate frequency signal digitization, each interruption obtains a sampling value, the sampling value is stored in the audio data queue, after multiple interruptions, the data accumulated in the audio data queue is the frequency modulation broadcast program sound data stream, the sound data stream is used for program transmission, and the program demodulation of the frequency modulation broadcast 10.7MHz intermediate frequency signal is realized.
The invention has the beneficial effects that: the demodulation system adopts a sampling method to realize the demodulation of a single-channel program of frequency modulation broadcasting, and solves the problems that in the industrial standard of the traditional frequency modulation broadcasting, the frequency of an intermediate frequency signal is 10.7MHz which is far larger than the input range of the direct frequency measurement demodulation, and the existing 10.7MHz intermediate frequency signal has too high frequency for a single-chip frequency measurement demodulation system and can not be directly measured; in addition, the captured data is arranged in the memory by using only one DMA, so that not only is a plurality of DMAs not needed to be jointly used, but also the audio sampling value can be obtained by calculation once in the interrupt service program without circulation, and the problem that the conventional frequency measurement demodulation system needs to carry out repeated collision detection in the interrupt service program is avoided; compared with the existing system, the system has simple structure, and can sample the audio signal with higher frequency because of high execution efficiency.
Drawings
Fig. 1 is a schematic circuit diagram of an fm broadcast if sampling demodulation system according to the present invention;
fig. 2 is a block diagram of the internal working principle of a single chip in the fm broadcast if sampling demodulation system according to the present invention.
Detailed Description
The embodiment is described with reference to fig. 1 and fig. 2, and the fm broadcast intermediate frequency sampling demodulation system includes a tuner U1, a D flip-flop U2, a single chip U3, a resistor R1, a resistor R2, a resistor R4, a resistor R5, a capacitor C1, a triode Q1, a triode Q2, a potentiometer R3, and a ceramic filter Y1;
the OUT end of a tuner U1 is connected with a capacitor C1, a capacitor C1 is respectively connected with bases of a resistor R1, a resistor R4 and a triode Q1, and a collector of a triode Q1 is respectively connected with bases of a resistor R1, a resistor R2 and a triode Q2;
VCC is respectively connected with a collector of a triode Q2 and a resistor R2, an emitter of a triode Q1 is respectively connected with a resistor R5 and an output end of a ceramic filter Y1, and an emitter of a triode Q2 is respectively connected with a potentiometer R3 and a D end of a D trigger U2; the sliding end of the potentiometer R3 is connected with the input end of the ceramic filter Y1;
GND is respectively connected with the grounding ends of the resistor R4, the resistor R5, the potentiometer R3 and the ceramic filter Y1; the Q end of the D trigger U2 is connected with the IN end of the singlechip U3, and the TIM end of the singlechip U3 is connected with the clock end of the D trigger U2;
the OUT end of the tuner U1 outputs a frequency modulation broadcast intermediate frequency signal, and the center frequency is 10.7 MHz; the TIM end of the singlechip U3 outputs a 10MHz square wave signal to drive the D trigger U2 to sample the signal output by the Q2, and the square wave signal obtained by sampling is output from the Q end of the D trigger U2 and is sent to the IN end of the singlechip U3;
the IN end of the singlechip is a timer input capture pin and can trigger the DMA at the same time;
the resistor R1, the resistor R2, the resistor R4, the resistor R5, the triode Q1, the triode Q2, the potentiometer R3 and the ceramic filter Y1 form an oscillating circuit, the oscillating frequency is 10.7MHz, and the output waveform amplitude can be stabilized by adjusting the R3;
when the broadcasting signal is normally received, the OUT end of the high-frequency head U1 outputs a frequency modulation broadcasting intermediate frequency signal which is coupled to the oscillating circuit through the capacitor C1, and frequency traction is generated, so that the oscillating frequency of the oscillating circuit deviates and changes along with the frequency of the frequency modulation broadcasting intermediate frequency signal;
when the broadcast signal is very weak, so that almost no signal is output from the OUT end of the tuner U1, the oscillation circuit does not generate frequency traction at the moment, and a stable 10.7MHz signal can be output;
the single chip microcomputer is internally provided with an intermediate frequency input end 1, a capture timer 2, a rising edge capture device 3, a DMA arbiter 4, a capture register 5, a DMA controller 6, a memory 7, a sampling timer 8, a sampling timer 9 and a TIM output end 10; the capture timer 2 accumulates and counts at the highest clock frequency of the singlechip system;
the embodiment is described with reference to fig. 2, and fig. 2 is a functional block diagram of the internal operation of the single chip microcomputer, wherein; the intermediate frequency input end 1 is the IN end of the single chip computer IN FIG. 1, and is respectively connected to the rising edge capturer 3 and the DMA arbiter 4, when a rising edge occurs at the intermediate frequency input end 1, the rising edge capturer 3 stores the value of the capture timer 2 IN the capture register 5, and simultaneously, a DMA request is initiated to the DMA arbiter 4; when the bus of the singlechip has an idle period, the DMA arbiter 4 informs the DMA controller 6 that one DMA operation can be executed, and the value in the capture register 5 can be saved in the memory 7;
setting DMA controller 6 as cycle working mode to make data stored in memory 7 in mode of cycle buffer area, able to store data in infinite number;
the sampling timer 9 generates 10MHz square waves and outputs the square waves to the outside of the single chip microcomputer from the TIM output end 10;
the sampling timer 8 initiates interruption to the singlechip at the frequency of 16KHz, an interruption service program calculates the program audio sampling value of the digitization of the intermediate frequency signal, and each interruption can obtain a sampling value, and the specific steps are as follows:
1. setting an address backup register as a storage unit, and storing the value of the address register written in the DMA controller 6 at each interrupt;
2. obtaining the value of a write address register in the DMA controller 6, and subtracting the backup value of the write address register to obtain an address increment value C;
3. subtracting one from the value of the write address register to obtain the latest write address, and obtaining the latest write data B from the latest write address;
4. subtracting one from the backup value of the write address register to obtain a backup address, and obtaining backup write data A from the backup address;
5. if the counting frequency of the capture timer is E, the numerical value of an N-bit binary digital audio sampling numerical value Z obtained by each interruption can be calculated;
Z＝(C*E/(B-A)-625000)*2N/150000
6. the interrupt service routine saves the value Z into an audio data queue and then quits the interrupt service routine; and when the interrupt occurs next time, returning to the step two to start the execution.
After multiple interruptions, the data accumulated in the audio data queue is the sound data stream of the FM broadcast program, and can be used for program transmission, storage or content analysis, so as to realize the program demodulation of FM broadcast 10.7MHz intermediate frequency signals.
Claims (3)
1. The FM broadcast intermediate frequency sampling demodulation system comprises a high frequency head U1, a D trigger U2, a singlechip U3, a capacitor C1 and an oscillating circuit; the method is characterized in that:
the OUT end of the tuner U1 is connected with a capacitor C1, and the capacitor C1 is connected with the input end of the oscillating circuit;
the output end of the oscillating circuit is connected with the D end of a D trigger U2, the Q end of the D trigger U2 is connected with the IN input end of a singlechip U3, and the TIM output end of the singlechip U3 is connected with the clock end C of the D trigger U2;
the single chip microcomputer U3 comprises a capture timer (2), an edge rising capture device (3), a DMA arbiter (4), a capture register (5), a DMA controller (6), a memory (7), a sampling timer (8) and a sampling timer (9) inside;
the IN input end of the singlechip U3 is used as an intermediate frequency input end (1) and is respectively connected with the rising edge capturer (3) and the DMA arbitrator (4),
when a rising edge appears at the intermediate frequency input end (1), the rising edge capturer (3) stores the value of the capture timer (2) to the capture register (5), and simultaneously initiates a DMA request to the DMA arbiter (4);
when the bus of the singlechip U3 has an idle cycle, the DMA arbiter (4) informs the DMA controller (6) to execute a DMA operation, and saves the value in the capture register (5) to the memory (7);
the OUT end of the tuner U1 outputs FM broadcast intermediate frequency signals, the center frequency is 10.7MHz,
the sampling timer (9) generates a 10MHz square wave signal, the square wave signal is output to the outside of the single chip microcomputer through a TIM output end (10) of the single chip microcomputer U3, the D trigger U2 is driven to sample the signal output by the oscillating circuit, and the square wave signal obtained by sampling is output to an IN input end of the single chip microcomputer U3 from a Q end of the D trigger U2;
the sampling timer (8) initiates interruption to the single chip microcomputer U3 at the frequency of 16KHz, the interruption service program calculates the program audio sampling value of the intermediate frequency signal digitization, each interruption obtains a sampling value, the sampling value is stored in an audio data queue, after multiple interruptions, the data accumulated in the audio data queue is the frequency modulation broadcast program sound data stream, the sound data stream is used for program transmission, and the program demodulation of the frequency modulation broadcast 10.7MHz intermediate frequency signal is realized; the specific process is as follows:
the sampling timer (8) initiates interruption to the singlechip at the frequency of 16KHz, an interruption service program calculates the program audio sampling value of the digitization of the intermediate frequency signal, and each interruption obtains a sampling value; the method comprises the following specific steps:
step one, setting an address backup register as a storage unit, and storing the numerical value of a write address register in a DMA controller (6) during each interrupt;
step two, the numerical value of a write address register in the DMA controller (6) is taken, and the numerical value of the address backup register is subtracted to obtain an address increment numerical value C;
subtracting one from the value of the write address register to obtain a new write address, and taking write data B from the new write address;
step four, subtracting one from the numerical value of the address backup register to obtain a new backup address, and taking backup write data A from the new backup address;
and step five, if the counting frequency of the capture timer (2) is E, obtaining an N-bit binary digital audio sampling value Z, which is expressed by a formula as follows:
Z＝(C*E/(B-A)-625000)*2N/150000
step six, saving the value of the write address register in the DMA controller (6) to an address backup register, and then exiting the interrupt service program; and when the interrupt occurs next time, returning to the step two to start the execution.
2. An fm broadcast if sample demodulation system as claimed in claim 1, wherein: the oscillating circuit comprises a resistor R1, a resistor R2, a resistor R4, a resistor R5, a triode Q1, a triode Q2, a potentiometer R3 and a ceramic filter Y1;
the capacitor C1 is respectively connected with the resistor R1, the resistor R4 and the base electrode of the triode Q1, and the collector electrode of the triode Q1 is respectively connected with the resistor R1, the resistor R2 and the base electrode of the triode Q2;
an emitter of the triode Q1 is respectively connected with the output ends of the resistor R5 and the ceramic filter Y1, an emitter of the triode Q2 is respectively connected with the D ends of the potentiometer R3 and the D trigger U2, and VCC is respectively connected with a collector of the triode Q2 and the resistor R2;
the sliding end of the potentiometer R3 is connected with the input end of a ceramic filter Y1;
GND is connected to the ground terminals of the resistor R4, the resistor R5, the potentiometer R3, and the ceramic filter Y1, respectively.
3. An fm broadcast if sample demodulation system as claimed in claim 1, wherein: the capture timer (2) accumulates and counts at the highest clock frequency of the singlechip system; the DMA controller (6) is set to a circular operation mode, and data is stored in the memory (7) in a circular buffer mode.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EA200001063A1 (en) * | 1998-04-14 | 2001-06-25 | Фраунхофер-Гезелльшафт Цур Фердерунг Дер Ангевандтен Форшунг Е.Ф. | TWO-MODE RECEIVER FOR RECEPTION OF SATELLITE AND GROUND SIGNALS IN A DIGITAL RADIO BROADCAST SYSTEM |
| CN2728097Y (en) * | 2004-04-05 | 2005-09-21 | 南京邮电学院 | Middle frequency digital modem |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100484172B1 (en) * | 2002-11-01 | 2005-04-19 | 삼성전자주식회사 | Apparatus for receiving television and radio using single tuner |
| US9819480B2 (en) * | 2015-08-04 | 2017-11-14 | Ibiquity Digital Corporation | System and method for synchronous processing of analog and digital pathways in a digital radio receiver |
| CN206759611U (en) * | 2017-05-19 | 2017-12-15 | 吉林省广播电视研究所(吉林省新闻出版广电局科技信息中心) | A kind of device of multiplex broadcasting digital modulation simultaneously |
| CN108183877B (en) * | 2018-01-11 | 2021-04-13 | 成都烨软科技有限公司 | Multi-tone frequency modulation signal demodulation method based on FPGA |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EA200001063A1 (en) * | 1998-04-14 | 2001-06-25 | Фраунхофер-Гезелльшафт Цур Фердерунг Дер Ангевандтен Форшунг Е.Ф. | TWO-MODE RECEIVER FOR RECEPTION OF SATELLITE AND GROUND SIGNALS IN A DIGITAL RADIO BROADCAST SYSTEM |
| CN2728097Y (en) * | 2004-04-05 | 2005-09-21 | 南京邮电学院 | Middle frequency digital modem |
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