CN111883656A - Memristor and preparation method thereof - Google Patents
Memristor and preparation method thereof Download PDFInfo
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
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Abstract
The invention discloses a memristor and a preparation method thereof in the technical field of memories, and the memristor comprises a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top, wherein the bottom electrode comprises an active electrode Ag and Cu or one of an oxygen-philic electrode W, Ti and TiN, the dielectric layer comprises a multilayer film formed by alternately depositing at least two oxide layers, and the top electrode comprises an inert electrode Pt and Au; the memristor prepared by the method can improve the erasing speed of the memory and reduce the energy consumption.
Description
Technical Field
The invention belongs to the technical field of memories, and particularly relates to a memristor and a preparation method thereof.
Background
As CMOS logic and memory devices continue to shrink in size, approaching the size limit, integrated circuit technology "moore's law" will also face significant challenges. The memristor is one of the leading subjects of memory category research at present, and mainly comprises a top electrode, a resistance change dielectric layer and a bottom electrode, and electrode materials can be further mainly divided into three types, namely an active electrode (copper, silver and the like), an inert electrode (platinum, gold and the like) and an oxygen-philic electrode (tungsten, titanium and the like). The resistive switching medium layer material can be divided into binary metal oxide, perovskite structure oxide, solid electrolyte material, chalcogenide semiconductor material and organic material. The overall electrical performance of the single-layer dielectric layer memristor is generally much worse than that of a double-layer or multi-layer dielectric layer memristor through analysis on the structure of the memristor, and is reflected in the aspects of switching speed of a device and stability of the device. The resistance change dielectric layer plays a crucial role in the resistance conversion process of the memristor, however, the performance of the memristor still needs to be further improved, so how to reasonably select and prepare the resistance change dielectric layer is crucial to improving the overall electrical performance of the memristor, the memristor prepared in the prior art needs a tedious activation process in the test process, and the energy consumption of the device is high.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a memristor and a preparation method thereof, solves the technical problem of high energy consumption in the prior art, and is beneficial to reducing the voltage of a device and low in energy consumption.
The purpose of the invention is realized as follows: a memristor and a preparation method thereof comprise a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top, wherein the bottom electrode comprises an active electrode Ag and Cu or one of an oxygen-philic electrode W, Ti and TiN, the dielectric layer comprises a multilayer film formed by alternately depositing at least two oxide layers, and the top electrode comprises an inert electrode Pt and Au.
As a further improvement of the invention, the thickness of the bottom electrode is 30-200 nm.
As a further improvement of the invention, the thickness of the dielectric layer is 4-30 nm.
As a further improvement of the invention, the thickness of the top electrode is 30-200 nm.
As a further improvement of the present invention, the dielectric layer is any one of a hafnium oxide layer, a titanium oxide layer, a zirconium oxide layer and an aluminum oxide layer or a combination of at least two of them.
As a further improvement of the invention, the dielectric layer is a multilayer film obtained by alternately depositing any two materials of hafnium oxide, zirconium oxide, tantalum oxide, copper oxide, iron oxide, silicon oxide, titanium oxide and aluminum oxide layers.
As a further improvement of the invention, the dielectric layers are prepared by adopting an atomic layer deposition method, the dielectric layers are different from bottom to top in an alternating mode, the dielectric layer I, the dielectric layer II, the dielectric layer I and the dielectric layer II … … sequentially circulate, and the dielectric layer I and the dielectric layer II are made of the two materials.
In order to further reduce the tunneling voltage, the thickness of the first dielectric layer is gradually reduced, and the thickness of the second dielectric layer is gradually increased.
A method of making a memristor, comprising the steps of:
(1) for Si/SiO2Carrying out standard cleaning process on the surface of the substrate, drying by using a nitrogen gun after cleaning is finished, carrying out glue homogenizing by using PMMA (polymethyl methacrylate), exposing by using an electron beam and developing to obtain a bottom electrode pattern;
(2) growing a bottom electrode by adopting a thermal evaporation method at a rate of 0.1-2A/s, then putting the sample into acetone, and finally displaying a bottom electrode pattern;
(3) preparing a top electrode pattern perpendicular to or intersecting the bottom electrode by electron beam exposure;
(4) preparing a dielectric layer by adopting an atomic layer deposition method, wherein the growth temperature is 100-350 ℃;
(5) depositing Pt for 10 min on the sample obtained in the step (4) by adopting radio frequency magnetron sputtering, wherein the thickness is 10-100 nm, the sputtering pressure of the radio frequency magnetron sputtering is set to be 0.1-1 Pa, the atmosphere is Ar, the flow is 8-30 sccm, the growth temperature is 20-100 ℃, and if the thickness of the metal electrode obtained by deposition is smaller than the set thickness value, turning to the step (6);
(6) and (5) evaporating Au on the surface of the Pt electrode by using thermal evaporation on the basis of the step (5), wherein the thickness is about 10-100 nm, and the growth rate is 0.1-2A/s.
As a further improvement of the invention, in the step (1), ultrasonic cleaning is adopted, and acetone, isopropanol or ethanol and deionized water are sequentially and respectively used for cleaning.
As a further improvement of the present invention, the growth rate of the bottom electrode in step (2) is 1 a/s; in the step (4), the growth temperature is 180 ℃; in the step (5), the sputtering pressure is set to be 0.95Pa, the flow rate is 20 sccm, the growth temperature is 20-25 ℃, and the thickness of Pt is 14 nm; in the step (6), the thickness of Au is 45 nm.
Compared with the prior art, the top electrode, the bottom electrode and the dielectric layer are all made of compact film materials with nanometer-scale thickness, the bottom electrode is made of titanium, the titanium metal has good oxygen affinity, can absorb oxygen atoms in the dielectric layer and form an interface layer between the titanium electrode and the dielectric layer, plays a good role in buffering in the resetting process of the device, is beneficial to thoroughly and quickly completing the resetting process, and simultaneously greatly improves the stability and the switching speed of the device; the dielectric layer is alternately deposited by adopting hafnium oxide and titanium oxide, the thickness of the titanium oxide layer is gradually reduced from the Ti electrode to the Pt electrode, the thickness of the hafnium oxide layer is gradually increased, and a structure with gradient change of an oxide layer can be formed in the region of the dielectric layer, so that TiOx forms a conductive filament by using a short oxygen vacancy defect, and charges can easily tunnel through the HfOx layer by using a low voltage; the device does not need an activation process, so that the complexity of the operation of the device is greatly reduced; the method realizes lower erasing voltage and has wide application prospect.
Drawings
Fig. 1 is a schematic structural diagram of a memristor in the present invention.
Fig. 2 is an electrode pattern effect diagram of a memristor in the present invention.
Fig. 3 is a scanning electron microscope image of a memristor bottom electrode Ti obtained in the present invention.
Fig. 4 is a scanning electron microscope image of a memristor dielectric layer prepared by the methods in example 1 and example 2.
FIG. 5 is a Transmission Electron Microscope (TEM) image of a cross section of a device obtained in example 1 of the present invention.
FIG. 6 is an Energy Dispersive Spectroscopy (EDS) chart of a local line scan of a cross section of a device obtained in example 1 of the present invention.
FIG. 7 is a DC I-V characteristic curve obtained by semi-logarithmic treatment of the memristor prepared in example 1 in the present invention.
Fig. 8 is a dc I-V characteristic curve of the device prepared in example 1 according to the present invention, obtained by double logarithmic processing of the High Resistance State (HRS) and the Low Resistance State (LRS) of the positive voltage scan section.
Fig. 9 is a direct current I-V characteristic diagram obtained by performing a semilogarithmic process on the memristor prepared in example 2 in the present invention.
Fig. 10 is a direct current I-V characteristic diagram of a memristor positive voltage scan section prepared in example 2, in which a High Resistance State (HRS) and a Low Resistance State (LRS) are subjected to a double logarithm process in the present invention.
Fig. 11 is a direct current I-V characteristic diagram obtained by performing a semilogarithmic process on the memristor prepared in example 3 in the present invention.
Fig. 12 is a direct current I-V characteristic diagram of a memristor positive voltage scan section prepared in example 3, in which a High Resistance State (HRS) and a Low Resistance State (LRS) are subjected to a double logarithm process in the present invention.
FIG. 13 is a DC I-V characteristic curve for different scan voltage settings for the memristor prepared in example 1 in the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
A memristor comprises a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top, wherein the bottom electrode comprises active electrodes Ag and Cu and one of an oxygen-philic electrode W, Ti and TiN, the dielectric layer comprises an oxide layer with gradually-changed and alternately-deposited thickness, the top electrode comprises inert electrodes Pt and Au, the thickness of the bottom electrode is 30-200 nm, the thickness of the dielectric layer is 4-30 nm, the thickness of the top electrode is 30-200 nm, and the dielectric layer is a combination of at least two films of a hafnium oxide layer with a high dielectric constant, zirconium oxide, tantalum oxide, copper oxide, iron oxide, silicon oxide, a titanium oxide layer, a zirconium oxide layer and aluminum oxide with a low dielectric constant which are alternately deposited.
In order to further reduce the required tunneling voltage, different dielectric layers are alternated from bottom to top, a first dielectric layer, a second dielectric layer, a first dielectric layer and a second dielectric layer … … are sequentially circulated, the first dielectric layer and the second dielectric layer are made of two materials, the thickness of the first dielectric layer is gradually reduced, and the thickness of the second dielectric layer is gradually increased; in this embodiment, when the first dielectric layer is a titanium oxide layer and the second dielectric layer is a hafnium oxide layer, the number of deposition turns of the dielectric layer from bottom to top is: multiples of 6 × n, 2 × 0, 6 × 1, 2 × 1 … … 6 × 1, 2 × 1, 6 × 0 and 14, 6 correspond to the number of deposition turns of the titanium oxide layer, the others represent the number of deposition turns of the hafnium oxide layer, where n is an integer and is equal to or greater than 3, the deposition thickness of the hafnium oxide layer is 0.1 to 0.12 nm/turn, the titanium oxide layer: 0.045 nm/circle; in this design, TiOxThe oxygen vacancy concentration in the Ti electrode is gradually reduced from the Ti electrode to the Pt electrode, and each layer of thin HfOxCan be used as a tunneling layer, thereby enabling TiO to bexThe oxygen vacancies reduce the required tunneling voltage while forming a conductive filament.
A method of making a memristor, comprising the steps of:
(1) for Si/SiO2Carrying out standard cleaning process on the surface of the substrate, drying by using a nitrogen gun after cleaning is finished, carrying out glue homogenizing by using PMMA (polymethyl methacrylate), exposing by using an electron beam and developing to obtain a bottom electrode pattern;
(2) growing a bottom electrode by adopting a thermal evaporation method at a rate of 0.1-2A/s, then putting the sample into acetone, and finally displaying a bottom electrode pattern;
(3) preparing a top electrode pattern perpendicular to or intersecting the bottom electrode by electron beam exposure;
(4) preparing a dielectric layer by adopting an atomic layer deposition method, wherein the growth temperature is 100-350 ℃;
(5) depositing Pt for 10 min on the sample obtained in the step (4) by adopting radio frequency magnetron sputtering, wherein the thickness is about 10-100 nm, the sputtering pressure of the radio frequency magnetron sputtering is set to be 0.1-1 Pa, the atmosphere is Ar, the flow is 8-30 sccm, the growth temperature is 20-100 ℃, and if the thickness of the metal electrode obtained by deposition is smaller than the set thickness value, turning to the step (6);
(6) on the basis of the step (5), thermally evaporating Au on the surface of the Pt electrode by using thermal evaporation, wherein the thickness is about 10-100 nm, and the growth rate is 0.1-2A/s;
ultrasonic cleaning is adopted in the step (1), and acetone, isopropanol or ethanol and deionized water are sequentially and respectively used for cleaning; in the step (2), a magnetron sputtering method can be adopted to grow the bottom electrode Ti, and in the step (6), magnetron sputtering can be adopted to evaporate Au on the surface of the Pt electrode.
Example 1
A memristor comprises a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top, wherein the bottom electrode is preferably titanium, the dielectric layer is preferably a combination of hafnium oxide and a titanium oxide layer, and the top electrode is preferably Pt and Au.
A method of making a memristor, comprising the steps of,
(1) 1.2 cm by 1.2 cm of Si/SiO2Ultrasonically cleaning the sheet in acetone, isopropanol and deionized water respectively, carrying out 15 minutes each time, then blowing by using nitrogen, carrying out glue homogenizing on the blown-dry sheet by using PMMA with the molecular weight of 950k, wherein the rotating speed of a glue homogenizing machine is 3000 r/min, the time is 1 min, then drying on a heating table at 180 ℃ for 2 min, finally obtaining the PMMA with the thickness of about 150 nm, then exposing a pre-designed Ti bottom electrode pattern by using an electron beam, developing (time is 1 min), fixing (time is 30 s), and finally blowing by using a nitrogen gun into a clean vessel;
(2) thermal evaporation of Ti electrode (60 nm) in bulk vacuum of 7.6X10-4Pa, evaporation source voltage 8.6V, heating current 78A, evaporation rate 1A/s, chamber pressure at 5.1x10 during evaporation-3-5.4x10-3Fluctuation in a Pa range;
(3) spin-coating a PMMA film on the substrate with the evaporated electrode in the step (2) again according to the operation in the step (1), carrying out secondary electron beam exposure, development and fixation, drying by using a nitrogen gun to show a top electrode Pt pattern, wherein the top electrode pattern is vertical to or intersected with the bottom electrode pattern;
(4) the method is characterized in that tetrakis (dimethylamino) hafnium is used as a hafnium oxide source, water is used as an oxygen source, the source heating temperature is 75 ℃, tetrakis (dimethylamino) titanium is used as a titanium source, water is used as an oxygen source, the source heating temperature is 75 ℃, the purification and carrier gas is nitrogen, the flow rate is 23.7 sccm, the temperature of a reaction chamber is 180 ℃, and the number of turns of the dielectric layer doped by using atomic layer deposition gradient is as follows:
| TiOx(Ring) | HfOx(Ring) |
| 30 | 0 |
| 24 | 2 |
| 18 | 4 |
| 12 | 6 |
| 6 | 8 |
| 0 | 14 |
And (3) deposition sequence: 30 turns of TiO x0 ring HfOx24 turns of TiO x2 rings of HfOx…, 0 turn TiOx14 circles HfOxFinally, the overall thickness of the titanium oxide and the hafnium oxide is ensured to be 8 nm, the gradient doping schematic diagram is shown in fig. 2, and as can be seen from fig. 3, after the bottom electrode Ti is made by thermal evaporation, the Ti electrode observed by SEM 8200The surface appearance is compact and smooth; the scanning electron microscope image of the dielectric layer after deposition is shown in FIG. 4, i.e., Ti/TiOx：HfOxAfter the observation, the film forming condition is observed, and as can be seen from fig. 3, the film forming quality is good, and the film is compact and flat, so that the overall performance of the device is ensured;
(5) depositing a Pt top electrode pattern on a sample subjected to dielectric layer deposition by using radio frequency magnetron sputtering, wherein the sputtering power is 20W, and the bulk vacuum is 1.7x10-4Pa, the starting pressure is 0.4 Pa, the sputtering pressure is 0.95Pa, the sputtering time is 10 min, the temperature of the reaction chamber is 20 ℃, and finally, the thickness of the Pt is measured by a spectroscopic ellipsometer to be 14 nm, so that the deposition rate of the Pt is 1.4 nm/min;
(6) in order to ensure the whole thickness of the bottom electrode, Au with the thickness of about 45 nm is grown on the Pt electrode in the step (5) by a thermal evaporation method, and the vacuum of a thermal evaporation body is 5x10-4Pa, working pressure 4.3x10-3Pa, the evaporation current is 75-80A, the deposition rate of Au is controlled, and the uniformity and firmness of the Au film are finally ensured;
(7) stripping: clamping the prepared device by using tweezers, putting the device into a beaker filled with acetone, sucking acetone solution by using a dropper, continuously blowing and wiping the surface of the device, replacing the acetone for 4-5 times, trying to strip Au and Pt around an electrode, transferring the device into another beaker filled with the acetone, sealing the device by using a sealing film, trying to perform ultrasonic treatment by using a 70% power ultrasonic instrument for 2 min, then respectively performing ultrasonic cleaning by using isopropanol and deionized water for 10 min, then drying the device by using a nitrogen gun, and finally observing an intact device pattern through a microscope.
In order to further prove the structure and the cross-sectional composition of the device, the energy dispersion spectrums of the transmission electron microscope picture and the local line scanning are shown in FIGS. 5 and 6; FIG. 5: transmission electron microscopy of the components of the device cross-section, a-a' indicating the extent of the line sweep, fig. 6: the energy dispersion spectrogram of local linear scanning of the cross section of the device mainly explores the element composition and approximate film thickness of each part of a gradient doped dielectric layer, and the actual thickness of Pt is smaller than the thickness during deposition, because the Pt is related to the adhesiveness of the dielectric layer and is related to shedding during TEM sample preparation.
Wherein the developing solution in the step (1) is isopropanol: tetramethylpentanone in a volume ratio of 3: 1, taking an appropriate amount of isopropanol as a fixing solution in the step (1); the spectroscopic ellipsometer is of the type SE-850; the heating temperature in the step (3) is 180 ℃, and the thickness of the well-homogenized glue obtained by measuring with a step profiler in the step (3) is 140 nm-150 nm.
In the present invention, the terms used herein are defined as follows:
the term "PMMA" refers to: polymethyl methacrylate;
the term "HfOx"means that: a hafnium oxide compound;
the term "TiOx"means that: a titanyl compound;
the term "SiO2"means that: silicon dioxide.
Example 2
The difference from example 1 is that steps (1) to (7) remain, and the device prepared on this basis is annealed by magnetron sputtering using high vacuum nitrogen gas at a temperature set at 400 ℃ for 4 min.
Example 3
This example differs from examples 1 and 2 in that TiOxBy conversion to AlOxThe gradient multilayer structure is also adopted, and the thickness of the whole dielectric layer is also 8 nm, so that the design of the gradient multilayer structure is further verified to be beneficial to reducing the energy consumption of devices and improving the storage density, and the universality of the method is proved.
A method of making a memristor, comprising the steps of,
(1) 1.2 cm by 1.2 cm of Si/SiO2Ultrasonically cleaning the sheet in acetone, isopropanol and deionized water respectively for 15 minutes each time, then blow-drying with nitrogen, homogenizing the blow-dried sheet with PMMA with the molecular weight of 950k at the rotating speed of 3000 r/min for 1 min, and then drying on a heating table at 180 ℃ for 2 min to obtain the final PMMA with the thickness of about 150 nm; exposing a pre-designed Ti bottom electrode pattern by using an electron beam, developing (time 1 min), fixing (time 30 s), and finally blowing and drying in a clean vessel by using a nitrogen gun;
(2) magnetron sputtering Ti electrode (100 nm), sputtering power of 150W, bulk vacuum of 5x10-4Pa, starting pressure of 1.3 Pa, sputtering pressure of 0.5 Pa, sputtering time of 20 min, reaction chamber temperature of 20 ℃, and applying bias voltage of 30V to ensure compact film formation; finally, the thickness of Ti is measured by a spectroscopic ellipsometer to be 100 nm, so that the deposition rate of Ti is 5 nm/min;
(3) the method is characterized in that tetrakis (dimethylamino) hafnium is used as a hafnium oxide source, water is used as an oxygen source, the source heating temperature is 75 ℃, trimethylaluminum is used as an aluminum source, water is used as an oxygen source, the source heating temperature is 25 ℃, the purification and carrier gas is nitrogen, the flow is 23.7 sccm, the temperature of a reaction chamber is 180 ℃, and the ratio of the number of layers of the dielectric layer using atomic layer deposition gradient is as follows:
| AlOx(Ring) | HfOx(Ring) |
| 14 | 0 |
| 8 | 2 |
| 6 | 4 |
| 4 | 6 |
| 2 | 8 |
| 0 | 14 |
And (3) deposition sequence: 14-turn AlO x0 ring HfOx8 circles AlO x2 rings of HfOx…, circle AlO 0x14 circles HfOxFinally, the whole thickness of the aluminum oxide and the hafnium oxide is ensured to be 8 nm.
(4) Spin-coating a PMMA film again according to the step (1) in the embodiment 1, carrying out secondary electron beam exposure, development and fixation, drying by using a nitrogen gun to reveal a top electrode Pt pattern, wherein the top electrode pattern is vertical to or intersected with a bottom electrode pattern;
(5) depositing a Pt top electrode pattern on a sample subjected to dielectric layer deposition by using radio frequency magnetron sputtering, wherein the sputtering power is 50W, and the bulk vacuum is 4.5x10-4Pa, starting pressure of 1.3 Pa, sputtering pressure of 0.5 Pa, sputtering time of 20 min, reaction chamber temperature of 20 ℃, and finally measuring the thickness of the Pt by a spectroscopic ellipsometer to be 80 nm, thereby obtaining the deposition rate of the Pt to be 4 nm/min;
(6) stripping: the method was the same as in step (7) of example 1, and after peeling, the devices were stored in a clean dish until testing.
The prepared memristor is subjected to the following electrical performance tests: in the test, a semiconductor parameter tester is utilized, a sample is placed on a probe station, and two probes are respectively contacted with an electrode to be tested, as shown in figure 1, wherein a Pt electrode is grounded, a Ti electrode is applied with positive and negative bias voltage, the voltage is increased from 1V, the scanning mode is set to be bidirectional, the scanning speed is 10 mv/s, the clamping current is set to be 1 mA, and when the device is activated, the scanning can be repeatedly carried out; as shown in fig. 7 and 8 (corresponding to example 1), it can be seen from fig. 7 that the voltage sweep range is-2-2V, when the voltage is 1.2V, the resistance state of the device starts to transition, from the high resistance state to the low resistance state and the "1" state, and exhibits self-clamping characteristics, which are much less than 1 mA for setting the clamping current, and when a negative voltage is added to the titanium bottom electrode, the device slowly transitions from the low resistance state to the high resistance state, and the "0" state; in fig. 8, the direct current I-V positive pressure swept portion performs high-low configuration log processing on the device, analyzes the device operation mechanism by fitting, and can visually see the size of the resistive window or the on-off ratio of the device, and as can be seen from fig. 8, the on-off ratio is 10; fig. 9 and 10 correspond to example 2, (device fabrication conditions are the same as example 1 except that magnetron sputtering is used for 400 ℃ nitrogen annealing treatment in example 2), the annealed device starts to be converted into a low-resistance state by using a voltage less than 1V, compared with example 1, the SET voltage is reduced, and the device also shows self-clamping and does not need a cumbersome electrical activation process, and as can be seen from fig. 10, the resistance change window of the device is obviously increased to 80-100; as shown in fig. 11 and 12 (corresponding to example 3), the memristor prepared by the method in example 3 and the memristor prepared by the method in example 3 are used to further verify the superiority of the gradient multilayer structure design, and by optimizing material matching, the energy consumption can be further reduced, the storage density can be improved, and the superiority of the gradient multilayer structure design can be further verified; since the combination of two materials, namely TiOx and HfOx, is mainly researched, but not limited to the combination of the two materials, the third example verifies the universality of the method; as shown in fig. 13, the dielectric layer adopts a gradient multilayer structure, when two different ranges of scanning voltages are adopted (-2V, -2.5V), two resistance states appear, which is more obvious in Reset process, and is beneficial to improving the storage density of the device.
In summary, the performance of the memristor prepared using the method of example 2 is optimal; wherein, Voltage is Voltage and Current is Current.
Compared with the prior art, the top electrode, the bottom electrode and the dielectric layer are all made of compact film materials with nanometer-scale thickness, the bottom electrode is made of titanium, the titanium metal has good oxygen affinity, can absorb oxygen atoms in the dielectric layer and form an interface layer between the titanium electrode and the dielectric layer, plays a good role in buffering in the resetting process of the device, is beneficial to thoroughly and quickly completing the resetting process, and simultaneously greatly improves the stability and the switching speed of the device; the dielectric layer is formed into a plurality of layers of films by adopting hafnium oxide and titanium oxide through alternate deposition, the thickness of each layer of film is changed in a gradient manner, the voltage of the device is reduced, the energy consumption is reduced, the on-off ratio of the device is improved by annealing the device in a nitrogen atmosphere, the device is accidentally discovered in the test process without an activation process, and the complexity of the operation of the device is greatly reduced.
The present invention is not limited to the above-mentioned embodiments, and based on the technical solutions disclosed in the present invention, those skilled in the art can make some substitutions and modifications to some technical features without creative efforts according to the disclosed technical contents, and these substitutions and modifications are all within the protection scope of the present invention.
Claims (10)
1. A memristor comprises a bottom electrode, a dielectric layer and a top electrode which are sequentially arranged from bottom to top, and is characterized in that the bottom electrode comprises an active electrode Ag and Cu or one of an oxophilic electrode W, a pro-oxidant electrode Ti and a pro-oxidant electrode TiN, the dielectric layer comprises a multilayer film formed by alternately depositing at least two oxide layers, and the top electrode comprises an inert electrode Pt and Au.
2. The memristor according to claim 1, wherein the thickness of the bottom electrode is 30-200 nm.
3. The memristor according to claim 1, wherein the dielectric layer has a thickness of 4-30 nm.
4. The memristor according to claim 1, wherein the thickness of the top electrode is 30-200 nm.
5. The memristor according to any one of claims 1 to 4, wherein the dielectric layer is a multilayer film obtained by alternately depositing any two materials of hafnium oxide, zirconium oxide, tantalum oxide, copper oxide, iron oxide, silicon oxide, titanium oxide and aluminum oxide layers.
6. The memristor according to claim 5, wherein the dielectric layers are prepared by an atomic layer deposition method, the dielectric layers are different from bottom to top alternately, the dielectric layer one, the dielectric layer two, the dielectric layer one and the dielectric layer two … … are sequentially circulated, and the dielectric layer one and the dielectric layer two are made of the two materials.
7. The memristor according to claim 5, wherein the thickness of the first dielectric layer gradually decreases, and the thickness of the second dielectric layer gradually increases.
8. A method of making the memristor of any of claims 1 to 7, comprising the steps of:
(1) for Si/SiO2Carrying out standard cleaning process on the surface of the substrate, drying by using a nitrogen gun after cleaning is finished, carrying out glue homogenizing by using PMMA (polymethyl methacrylate), exposing by using an electron beam and developing to obtain a bottom electrode pattern;
(2) growing a bottom electrode by adopting a thermal evaporation method at a rate of 0.1-2A/s, then putting the sample into acetone, and finally displaying a bottom electrode pattern;
(3) preparing a top electrode pattern perpendicular to or intersecting the bottom electrode by electron beam exposure;
(4) preparing a dielectric layer by adopting an atomic layer deposition method, wherein the growth temperature is 100-350 ℃;
(5) depositing Pt for 10 min on the sample obtained in the step (4) by adopting radio frequency magnetron sputtering, wherein the thickness is about 10-100 nm, the sputtering pressure of the radio frequency magnetron sputtering is set to be 0.1-1 Pa, the atmosphere is Ar, the flow is 8-30 sccm, the growth temperature is 20-100 ℃, and if the thickness of the metal electrode obtained by deposition is smaller than the set thickness value, turning to the step (6);
(6) and (5) evaporating Au on the surface of the Pt electrode by using thermal evaporation on the basis of the step (5), wherein the thickness is about 10-100 nm, and the growth rate is 0.1-2A/s.
9. The method for preparing the memristor according to claim 8, wherein ultrasonic cleaning is adopted in the step (1), and the cleaning solution is acetone, isopropanol or ethanol, or deionized water.
10. The method of making a memristor according to claim 8, wherein the growth rate of the bottom electrode in step (2) is 1 a/s; in the step (4), the growth temperature is 180 ℃; in the step (5), the sputtering pressure is set to be 0.95Pa, the flow rate is 20 sccm, the growth temperature is 20-25 ℃, and the thickness of Pt is 14 nm; in the step (6), the thickness of Au is 45 nm.
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| CN114512604A (en) * | 2022-04-20 | 2022-05-17 | 山东科技大学 | Copper-doped metal oxide dual-functional-layer memristor |
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| CN112510148A (en) * | 2020-12-08 | 2021-03-16 | 扬州大学 | Resistive random access memory and preparation method thereof |
| CN114512604A (en) * | 2022-04-20 | 2022-05-17 | 山东科技大学 | Copper-doped metal oxide dual-functional-layer memristor |
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