CN111883539A - Preparation method of three-dimensional memory and ion implantation device - Google Patents

Preparation method of three-dimensional memory and ion implantation device Download PDF

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CN111883539A
CN111883539A CN202010873525.1A CN202010873525A CN111883539A CN 111883539 A CN111883539 A CN 111883539A CN 202010873525 A CN202010873525 A CN 202010873525A CN 111883539 A CN111883539 A CN 111883539A
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ion implantation
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stack
substrate
dimensional memory
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CN111883539B (en
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孙璐
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3171—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation for ion implantation
    • H01J37/3172—Maskless patterned ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30—Electron or ion beam tubes for processing objects
    • H01J2237/317—Processing objects on a microscale
    • H01J2237/31701—Ion implantation
    • H01J2237/31706—Ion implantation characterised by the area treated

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Abstract

The application discloses a preparation method of a three-dimensional memory and an ion implantation device. The preparation method of the three-dimensional memory comprises providing a substrate; forming a stack layer on the substrate, and etching the stack layer to form a channel hole penetrating through the stack layer; and ion implanting the surface of the stacked layer, which faces away from the substrate. According to the preparation method of the three-dimensional memory, ions are injected to break the valence bonds of crystal lattices in the stacking layers, stress between internal structures of the stacking layers is released, the warping degree of the stacking layers is reduced, the accuracy of the processes such as binding of the three-dimensional memory is improved, and the reliability of the preparation method of the three-dimensional memory is improved.

Description

Preparation method of three-dimensional memory and ion implantation device
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a three-dimensional memory and an ion implantation apparatus.
Background
A three-dimensional (3D) memory, which is a typical vertical channel type three-dimensional memory, includes a substrate and a stack of layers on the substrate. Generally, the larger the number of stacked layers in a three-dimensional memory, the higher the capacity of the three-dimensional memory, and therefore, in order to achieve the higher capacity of the three-dimensional memory, the number of stacked layers is increasing accordingly.
In the process of manufacturing the three-dimensional memory, the stack layer is processed to form a memory structure in the stack layer, for example, the stack layer is etched to form a plurality of Channel Holes (CH), and a memory structure core is formed in the channel holes. With the increase of the number of stacked layers, after the stacked layers are etched to form the channel holes, the stress difference of each region in the stacked layers is larger, the warping degree of the stacked layers is larger, the flatness of the stacked layers is poorer, and the reliability of preparing the three-dimensional memory is reduced.
Disclosure of Invention
The application provides a preparation method of a three-dimensional memory and an ion implantation device. In the process of preparing the three-dimensional memory, ions are injected to break the valence bonds of crystal lattices in the stacked layers, the stress between the internal structures of the stacked layers is released, the warping degree of the stacked layers is reduced, and the reliability of the preparation method of the three-dimensional memory is improved. The application also provides an ion implantation device which can be used for preparing the three-dimensional memory.
In a first aspect, the present application provides a method for fabricating a three-dimensional memory. The preparation method of the three-dimensional memory comprises the following steps:
providing a substrate;
forming a stacking layer on the substrate, and etching the stacking layer to form a channel hole penetrating through the stacking layer;
and ion implantation is carried out on the surface of the stacked layer, which faces away from the substrate.
In the embodiment of the application, ions are injected to break the valence bonds of crystal lattices in the stacked layers, and the stress between the internal structures of the stacked layers is released, so that the warping degree of the stacked layers is reduced, the accuracy of the processes such as binding of the three-dimensional memory is improved, and the reliability of the preparation method of the three-dimensional memory is improved.
In some embodiments, the "implanting ions into the stack" comprises:
disposing a patterned shield over the stack of layers; the patterned shielding piece comprises a plurality of shielding strips arranged at intervals along the same direction, and a gap is formed between any two adjacent shielding strips;
ions are implanted into the stack of layers through the gap through the patterned shield.
In some embodiments, prior to the "ion implanting the stack", the method further comprises:
detecting the warping degree of the stacked layers along a first direction and the warping degree of the stacked layers along a second direction; wherein the first direction and the second direction are arranged crosswise;
when the warping degree in the first direction is larger than that in the second direction, a plurality of shielding strips are arranged at intervals along the second direction, and the gaps extend along the first direction;
when the warping degree of the second direction is larger than that of the first direction, a plurality of shielding strips are arranged at intervals along the first direction, and the gaps extend along the second direction.
In some embodiments, prior to the "ion implanting the stack", the method further comprises:
a memory stem is formed along the channel hole.
In some embodiments, after the "ion implanting the stack layer", the method further comprises:
and adsorbing the surface of the substrate, which is far away from the stacked layer, so as to transfer the substrate and the stacked layer on the substrate to a position to be etched.
In some embodiments, after the "ion implanting the stack layer", the method further comprises:
binding an object to be bound on the surface of the stacked layers; wherein the object to be bound is electrically connected with the stack layer.
In a second aspect, the present application further provides an ion implantation apparatus. The ion implantation device comprises an ion implantation assembly and a bearing assembly, wherein the ion implantation assembly is provided with an ion injection hole, and the bearing assembly is provided with a bearing surface for bearing a target object;
the ion implantation device also comprises a shielding piece, wherein the shielding piece comprises a plurality of shielding strips which are arranged at intervals, and a gap is arranged between any two adjacent shielding strips; when the ion implantation device is in a first state, the shielding piece is positioned between the ion injection port and the bearing surface.
In some embodiments, the shielding strips are arranged along a first direction, and the shielding strips extend along a second direction, and the first direction and the second direction are arranged in a crossed manner.
In some embodiments, the shielding strip includes a plurality of flat portions and a plurality of protruding portions, the plurality of protruding portions protrude relative to the plurality of flat portions, the plurality of flat portions and the plurality of protruding portions are alternately disposed, and the plurality of flat portions and the plurality of protruding portions are all arranged along the second direction.
In some embodiments, the carrier assembly rotates relative to the ion implantation assembly, and when the ion implantation apparatus is in the first state, a plane on which the carrier surface is located is parallel to a plane on which an opening of the ion injection port is located; when the ion implantation device is in a second state, the plane where the bearing surface is located is intersected with the plane where the opening of the ion injection port is located.
In the embodiment of the present application, the ion implantation apparatus is provided with the shielding member, the shielding member is provided with a plurality of gaps arranged at intervals along the first direction, and each gap extends along the second direction, after the ion beam emitted from the ion injection port passes through the shielding member, the ions are implanted into the surface of the target object arranged at intervals along the first direction and extend along the second direction, so that the ions are only implanted into a partial region of the target object, the warping degree of the target object along a certain direction is improved, the difference of the warping degrees in different directions in the target object is reduced, and the flatness of the target object is improved.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart of a method for fabricating a three-dimensional memory provided herein;
FIGS. 2A-2D are schematic cross-sectional views of the process corresponding to the steps of FIG. 1 for fabricating a portion of the three-dimensional memory;
FIG. 3 is a schematic flow chart of step S150 shown in FIG. 1;
FIG. 4 is a top view of the shield of FIG. 2D;
fig. 5 is a schematic structural diagram of an ion implantation apparatus provided in the present application in a first state;
fig. 6 is a schematic view of the ion implantation apparatus shown in fig. 5 in a second state;
FIG. 7 is a schematic structural view of the load bearing assembly of FIG. 5 in a first state;
FIG. 8 is a schematic structural view of the load bearing assembly of FIG. 5 in a second state;
fig. 9 is a schematic diagram of a portion of the ion implantation apparatus of fig. 5 in a first position;
fig. 10 is a schematic diagram of a portion of the ion implantation apparatus of fig. 5 in a second position;
figure 11 is a top view of the shield of figure 9 in a first embodiment;
figure 12 is a top view of the shield of figure 9 in a second embodiment.
Detailed Description
Technical solutions in embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. In the present invention, the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Based on the defect of large warping degree of a stacked layer in a traditional three-dimensional memory preparation method, the scheme provides a three-dimensional memory preparation method, ion implantation is carried out on the surface of the stacked layer after a channel hole is formed, the ion implantation can break lattice valence bonds to release stress, the difference of the stress in different areas of the stacked layer is reduced, the warping degree (wafer bow) of the stacked layer is improved, the accuracy of the processes such as three-dimensional memory binding and the like is favorably improved, and therefore the reliability of the three-dimensional memory preparation method is favorably improved. In some cases, the warpage of the stacked layer is improved, and the error of the subsequent photoetching process of the stacked layer is reduced, so that the reliability of the three-dimensional memory is improved.
Please refer to fig. 1 and fig. 2A-2D together. FIG. 1 is a schematic flow chart of a method for fabricating a three-dimensional memory provided herein; fig. 2A-2D are schematic cross-sectional views of the process corresponding to the steps of fabricating the three-dimensional memory portion shown in fig. 1. The three-dimensional memory in this particular embodiment may be, but is not limited to, a 3D NAND memory.
The method for manufacturing the three-dimensional memory includes, but is not limited to, S110 to S170. S110 to S170 are described in detail as follows.
S110: a substrate 10 is provided.
It will be appreciated that the substrate 10 is used to support device structures thereon. The substrate 10 may be a Si substrate, a Ge substrate, a SiGe substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like. In the embodiment of the present application, the substrate 10 is described as a silicon substrate.
S120: a stack of layers 20 is formed on the substrate 10.
The stacked layer 20 includes a plurality of insulating layers 21 and sacrificial layers 22 alternately stacked. As shown in fig. 2A, a plurality of insulating layers 21 and a plurality of sacrificial layers 22 are alternately disposed on the substrate 10. The insulating layer 21 and the sacrificial layer 22 in the stack layer 20 are deposited. The deposition method may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), physical vapor deposition methods such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, or sputtering, among others. The material of the insulating layer 21 may be, but is not limited to, an oxide material, and the material of the sacrificial layer 22 may be, but is not limited to, a nitride material. Illustratively, the sacrificial layer 22 is replaced with a gate layer in subsequent process steps.
The number of the stacked layers 20 can be adjusted by those skilled in the art according to the actual process requirements or the limitations of the equipment, and the number of the stacked layers 20 is not limited in the present application. For example, the number of layers of the stacked layers 20 may be 32, 64, 96, 128, or the like. In general, the greater the number of stacked layers, the higher the integration of the three-dimensional memory. It is to be understood that the sizes or numbers of the insulating layer 21 and the sacrificial layer 22 in fig. 2A are merely examples.
S130: the stack of layers 20 is etched to form a trench hole 201 through the stack of layers 20.
The structure of the channel hole 201 in fig. 2B is merely an example, and the actual structure may be a cylinder, a cone, a ring, etc., and the present application is not limited thereto. In the process of forming the channel hole 201, the stack layer 20 is etched to the substrate 10 to expose the substrate 10. The process for etching the stack layer 20 to form the channel hole 201 includes, but is not limited to, a photolithography process, a plasma (plasma) etching process, and the like.
In one embodiment, etching the stack of layers 20 includes etching a portion of the layer structure of the stack of layers 20 before etching another portion of the layer structure of the stack of layers 20. That is, the trench holes 201 are formed in steps. In this embodiment, the step-by-step etching process for forming the channel holes 201 penetrating through the stack layer 20 not only reduces the difficulty of etching a machine and an etching process caused by etching the too deep channel holes 201 at one time, but also is beneficial to improving the uniformity of the plurality of channel holes 201 formed by etching the stack layer 20, thereby improving the reliability of the three-dimensional memory preparation method and improving the yield of the prepared three-dimensional memory.
In other embodiments, forming the stack layer 20 on the substrate includes first forming the first stack layer 20, and etching the first stack layer 20 to form the first channel hole 201; a second stacked layer 20 is formed on the first stacked layer 20, and the second stacked layer 20 is etched to form a second channel hole 201. Wherein the second channel hole 201 communicates with the first channel hole 201. In this embodiment, the trench holes 201 are also formed step by step, which reduces the difficulty of etching the machine and the etching process caused by etching the too deep trench holes 201 at one time, and improves the reliability of the three-dimensional memory preparation method.
It is to be understood that the present application is not limited to the process of forming the channel hole 201 on the stack layer 20, and those skilled in the art can adjust the process of forming the channel hole 201 according to the process requirements.
S140: the memory stem 30 is formed along the channel hole 201.
As shown in fig. 2C, the memory stem 30 is located inside the stacked layers 20. It is understood that the memory stem 30 is formed in the channel hole 201.
Wherein forming the memory stem 30 along the channel hole 201 comprises:
s141: an epitaxial structure 31 is formed on the substrate 10 along the channel hole 201.
The epitaxial structure 31 is formed by Selective Epitaxial Growth (SEG) on the substrate 10. The epitaxial structure 31 may be an epitaxially grown single crystal silicon, or may be other suitable semiconductor materials, which is not limited in this application.
S142: a channel structure 32 is formed on the epitaxial structure 31 along the channel hole 201.
As shown in fig. 2C, the channel structure 32 is located at an upper layer of the epitaxial structure 31. The channel structure 32 is formed along the axial direction of the channel hole 201, and the channel structure 32 fills the channel hole 201.
In one embodiment, the channel structure 32 includes a memory structure, a semiconductor structure, and an insulating dielectric layer disposed in this order. The storage structure is arranged around the outer side of the semiconductor structure, and the semiconductor structure surrounds the insulating medium layer. Forming the memory structure includes sequentially forming a barrier layer, a memory layer, and a tunneling layer along the trench 201. The barrier layer is located on the side of the memory layer adjacent to the stack 20. Wherein the memory layer stores electrons. Electrons of the storage layer can pass through the tunneling layer under pressure. Illustratively, the memory structure may be formed as an oxide-nitride-oxide (ONO) layered structure. Deposition processes may be used to form the barrier layer, the memory layer, and the tunnel layer.
S150: the surface of the stack 20 facing away from the substrate 10 is ion implanted.
Wherein the stacked layer 20 is ion implanted to improve the warpage (wafer bow) of the stacked layer 20. Warp is used to describe the degree of bending of a plane in space. Warp is defined numerically as the distance between two points of the warp plane that are the farthest away in the height direction. It can be understood that the warp of the absolute plane is 0. The greater the warpage of the stacked layer 20, the greater the degree to which the stacked layer 20 is warped. Based on the integration of the stack layer 20 and the substrate 10, the warpage of the stack layer 20 is improved, i.e., the warpage of the entire wafer is improved.
The present application does not limit the kind of ion implantation on the surface of the stacked layer 20, and those skilled in the art can select the kind of ion implantation according to the material used for the stacked layer 20. Illustratively, pentavalent phosphorus ions or trivalent boron ions are implanted into the surface of the stack 20.
In some embodiments, before the ion implantation into the stack layer 20, the method for manufacturing a three-dimensional memory further includes: and detecting the warping degree of the stacked layer 20, and when the warping degree of the stacked layer 20 is larger than or equal to a rated value, performing ion implantation on the stacked layer 20. It is understood that when the warp of the stacked layer 20 is detected to be less than the rated value, the ion implantation of the stacked layer 20 is not required. The rated value can be, but is not limited to, 0, and the application does not limit the magnitude of the rated value.
Ion implantation of the stack 20 is performed by an ion implantation process, for example, by using an ion implantation apparatus to implant ions into the surface of the stack 20. The present application is not limited to the type of implanted ions, and those skilled in the art will be able to select the implanted ions based on the actual material used for the stack 20. For example, the implanted ions may be, but are not limited to, pentavalent phosphorus or trivalent boron.
In the embodiment of the present application, the stacked layer 20 after the channel hole 201 is formed is subjected to ion implantation, and ions are implanted to break the valence bonds of crystal lattices in the stacked layer 20, so as to release stress between internal structures of the stacked layer 20, thereby reducing the warpage of the stacked layer 20, facilitating improvement of the accuracy of processes such as three-dimensional memory binding, and facilitating improvement of the reliability of the three-dimensional memory preparation method. In addition, in this embodiment, after the channel structure 30 is formed in the channel hole 201, the ion implantation is performed on the stacked layer 20, so as to prevent the ion from being implanted into the inside of the stacked layer 20 or the substrate through the channel hole 201, thereby preventing the ion from damaging the electrical property of the three-dimensional memory.
As shown in fig. 2D, in some embodiments, before the ion implantation into the stack layer 20, the method for preparing the three-dimensional memory further includes: a photo-resist (PR) 40 is formed on the surface of the stack layer 20.
In this embodiment, the photoresist 40 is disposed on the surface layer of the stack layer 20, and for the photoresist 40 on the surface layer after ion implantation in the stack layer 20, since the photoresist 40 is removed in the subsequent process, the ions implanted in the photoresist 40 can be finally removed, thereby avoiding or reducing the influence of the implanted ions on the electrical property of the three-dimensional memory.
The ion implantation adopts a mature process, and those skilled in the art can design the concentration, rate or time of the ion implantation according to the process requirements to control the amount of the ion implantation, thereby avoiding the influence of excessive ions on the stacked layer 20 on the electrical property of the final three-dimensional memory.
Referring to fig. 3, fig. 3 is a schematic flowchart of step S150 shown in fig. 1. In some embodiments, the stacked layer 20 is ion implanted:
s151: detecting a warp of the stacked layer 20 in a first direction and a warp in a second direction; wherein the first direction and the second direction are arranged crosswise.
In the embodiments of the present application, the description is given taking the case where the first direction is perpendicular to the second direction as an example. In other embodiments, the angle formed between the first direction and the second direction may also be an acute angle, which is not limited in this application.
In the process of manufacturing the three-dimensional memory, the warpage of the stacked layer 20 in the first direction may be the same as the warpage of the stacked layer 20 in the second direction, but the warpage of the stacked layer 20 in the first direction may also be different from the warpage of the stacked layer 20 in the second direction, and the surface of the stacked layer 20 is not flat, i.e. the surface of the stacked layer 20 has poor levelness. In the embodiment of the present application, warpage of the stacked layer 20 in different directions is detected, and the stacked layer 20 with poor flatness is determined in the process of manufacturing the three-dimensional memory, so as to facilitate improvement of the stacked layer 20 with poor flatness in the subsequent process.
S152: disposing a patterned shield 50 over the stack of layers 20; the patterned shielding member 50 includes a plurality of shielding bars 51 arranged at intervals, and a gap 52 is provided between any two adjacent shielding bars 51.
The shielding piece 50 and the surface of the stacked layer 20 are arranged at intervals, so that the shielding piece 50 and the surface of the stacked layer 20 are prevented from generating friction to influence the structure of the stacked layer 20, and the reliability of the three-dimensional memory preparation method is ensured. The shielding member 50 functions like a light shield for shielding a portion of the structure of the stack layer 20, and ions can pass through only a portion of the shielding member 50, so that ions can be implanted into a portion of the surface of the stack layer 20. The material of the shielding member 50 is not limited in the present application, and those skilled in the art can use a material capable of blocking ions from passing through as needed.
Continuing to refer to fig. 4, fig. 4 is a top view of the covering piece 50 shown in fig. 2D. In some embodiments, the plurality of shielding bars 51 are arranged in a first direction, and the shielding bars 51 extend in a second direction. As shown in fig. 4, in the first embodiment of the present application, a plurality of masking bars 51 are described as stripes, for example. In other embodiments, the shielding strip 51 can have other shapes, which is not limited in the present application. In the embodiment of the present application, the example is described in which the top view of the shade 51 is circular. In other embodiments, the top view of the shielding member 51 may be square or rectangular, which is not limited in the present application.
In this embodiment, the shielding member 50 is provided with a plurality of shielding bars 51 arranged along a first direction, and a gap 52 is provided between any two shielding bars 51, the shielding bars 51 can shield penetration of ions, and the ions can only penetrate through the gap 52 of the shielding member 50 to be injected into a part of the surface of the stacked layer 20, so as to improve warpage of the stacked layer 20 along a certain direction.
S153: ions pass through the patterned shutter 50 through the gaps 52 to implant into the stack 20; when the warping degree in the first direction is greater than the warping degree in the second direction, a plurality of shielding bars 51 are arranged at intervals along the second direction, and the gaps 52 extend along the first direction; when the warpage of the second direction is greater than the warpage of the first direction, the plurality of shielding bars 51 are disposed at intervals along the first direction, and the gap 52 extends along the second direction.
When the warp of stacked layer 20 in the first direction is greater than the warp in the second direction, the extending direction of gaps 52 in barrier 50 during ion implantation of stacked layer 20 is in the first direction, so that ions are implanted into the surface of stacked layer 20 at intervals in the second direction, and only the warp of stacked layer 20 in the first direction is reduced, or the warp of stacked layer 20 in the first direction is reduced by a greater amount than the warp in the second direction, so as to reduce the difference between the warp in the first direction and the warp in the second direction in stacked layer 20.
When the warp of stacked layer 20 in the second direction is greater than the warp in the first direction, the extending direction of gaps 52 in shutter 50 during ion implantation of stacked layer 20 is in the second direction, so that ions are implanted into the surface of stacked layer 20 at intervals in the first direction, and only the warp of stacked layer 20 in the second direction is reduced, or the warp of stacked layer 20 in the second direction is reduced by a greater amount than the warp in the first direction, so as to reduce the difference between the warp in the second direction and the warp in the first direction in stacked layer 20.
It can be understood that, if the ion implantation is performed on all the regions of the stacked layer 20, the lattice valence bonds in different regions of the stacked layer 20 can be broken at the same time, which not only improves the warpage of the stacked layer 20 along the first direction, but also improves the warpage of the stacked layer 20 along the second direction, and at this time, the warpage of different regions of the stacked layer 20 is reduced at the same time, which cannot reduce the difference between the warpage of the stacked layer 20 along the first direction and the warpage of the stacked layer 20 along the second direction, and is not beneficial to further improving the flatness of the stacked layer 20.
In this embodiment, before ion implantation into stack layer 20, patterned shield 50 is disposed over stack layer 20, so that ions are implanted into only a partial region of stack layer 20, the warpage of stack layer 20 in a certain direction is improved, the difference between the warpage in the first direction and the warpage in the second direction in stack layer 20 is reduced, and the flatness of stack layer 20 is improved. In other embodiments, the shielding member 50 can be omitted from the stacked layer 20 before the ion implantation of the stacked layer 20, so as to improve the warpage of the stacked layer 20 in different directions, which is not limited in the present application.
Before ion implantation is performed on the stacked layer 20, the carrier platform for carrying the three-dimensional memory can rotate, so that the directions of the warp degrees in different stacked layers 20 are different, the substrate and the stacked layer 20 can be rotated to make the direction of the warp degree larger the same as the extending direction of the shielding strip 51, and accordingly, the difference of the warp degrees in different directions in the stacked layer 20 is correspondingly reduced.
In some embodiments, when the warpage of the stacked layer 20 in the first direction is equal to the warpage in the second direction, the flatness of the surface of the stacked layer 20 is better, and it is not necessary to provide the shielding member 50 on the stacked layer 20 and then perform ion implantation on a portion of the stacked layer 20, or it is not necessary to perform ion implantation on the stacked layer 20, so as to simplify the process of manufacturing the three-dimensional memory.
S160: the surface of the substrate 10 facing away from the stack of layers 20 is attracted to transfer the substrate 10 and the stack of layers 20 on the substrate 10 to the location to be etched.
After the substrate 10 and the stack layer 20 on the substrate 10 are transferred to a position to be etched, the stack layer 20 may be etched to form a Gate Line Slit (GLS); or the stack of layers 20 is etched to form current paths, etc. It will be appreciated that the process of etching the stack of layers 20 includes vacuum-sucking the surface of the substrate 10 facing away from the stack of layers 20 to place the substrate 10 and the stack of layers 20 on the substrate 10 in a position to be etched. When the vacuum suction substrate 10 deviates from the stack layer 20, the suction member is provided with four different suction cups, and the four suction cups suck different positions on the bottom surface of the substrate 10, so as to stably suck the substrate 10 and the stack structure on the substrate 10.
In the embodiment of the present application, the substrate 10 and the stack layer 20 are an integral structure, when the stack layer 20 tilts, the substrate 10 tilts accordingly, at this time, the surface of the substrate 10 that deviates from the stack layer 20 is not flat, and when the four suction cups of the suction piece suck the bottom surface of the substrate 10, one or more suction cups are prone to fail to suck the substrate 10, so that the suction piece sucks the stack structures on the substrate 10 and the substrate 10 unstably, and the stack structures on the substrate 10 and the substrate 10 are prone to slide down from the suction accessory, thereby affecting the reliability of the three-dimensional memory manufacturing method.
In the embodiment of the present application, the patterned shielding member 50 is disposed above the stacked layer 20, and ions are only implanted into a partial region of the stacked layer 20, so as to improve warpage of different portions of the stacked layer 20 and the substrate 10, improve flatness of the stacked layer 20 and the substrate 10, and reduce a risk that the substrate 10 and the stacked layer 20 are separated from the adsorbing member in a process of transferring the substrate 10 and the stacked layer 20 by the bottom surface of the adsorbing member substrate 10, thereby not only improving reliability of a three-dimensional memory manufacturing method, but also facilitating improvement of accuracy of a photolithography process of the three-dimensional memory.
S170: binding the object to be bound on the surface of the stack layer 20; wherein the object to be bonded is electrically connected to the stack layer 20.
In some embodiments, the object to be bonded is the same as the wafer to be bonded. Illustratively, the binding process of the three-dimensional memory includes bonding two wafers to be bound together, a memory wafer and a control wafer. In other embodiments, the object to be bound may have other structures, which is not limited in this application.
It can be understood that when the flatness of the surface of the stacked layer 20 is poor, that is, the surface of the stacked layer 20 is not flat, the degree of conformance between the stacked layer 20 and the surface of the object to be bound is poor, thereby affecting the accuracy of binding the three-dimensional memory.
In the embodiment of the present application, the patterned shielding member 50 is disposed above the stacked layer 20, and ions are only injected into a partial region of the stacked layer 20, so as to improve the warping degree of different portions of the stacked layer 20, improve the flatness of the stacked layer 20, improve the accuracy of binding the to-be-bound object and the stacked layer 20, and facilitate improving the yield of the three-dimensional memory.
The steps necessary for the method for manufacturing the three-dimensional memory in the present application include S110, S120, S130, and S150. In other embodiments, steps S140, S160, and S170 may be replaced by other processes, or the process sequence of S140, S160, or S170 may be changed, which is not limited in this application. For example, in other embodiments, the step S140 may be performed after the step S150, and then a protective layer may be formed on the stacked layer 20 before the step S150 and cover the channel hole 201, where the protective layer can avoid ion implantation into the channel hole 201.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an ion implantation apparatus provided in the present application in a first state. The present application further provides an ion implantation apparatus 200. The ion implantation apparatus 200 can be used in, but is not limited to, the above-described method for fabricating a three-dimensional memory. The ion implantation apparatus 200 includes an ion implantation assembly 210 and a carrier assembly 220. The ion implantation assembly 210 is provided with an ion injection port 211. The bearing assembly 220 is provided with a bearing surface 221 for bearing the object. The ion beam is emitted from the ion injection port 211 and then can be projected onto a target on the support surface 221. The target may be, but is not limited to, a wafer. As shown in fig. 5, the shapes or positions of the ion implantation pattern 200, the ion implantation module 210 and the carrier module 220 are merely examples, and the present application is not limited thereto.
Referring to fig. 5 and 6, fig. 6 is a schematic structural diagram of the ion implantation apparatus shown in fig. 5 in a second state. In some embodiments, portions of the structure of the carrier assembly 220 rotate relative to the ion implantation assembly 210. As shown in fig. 6, when the ion implantation apparatus 200 is in the first state, the plane of the supporting surface 221 is parallel to the plane of the opening of the ion injection port 211. As shown in fig. 5, when the ion implantation apparatus 200 is in the second state, the plane of the supporting surface 221 intersects with the plane of the opening of the ion injection port 211. Illustratively, the plane of the supporting surface 221 is perpendicular to the plane of the opening of the ion injection port 211.
It is understood that the ion implantation apparatus 200 can adjust the angle of the carrier assembly 220 relative to the ion implantation assembly 210 through a set program. The rotation angle of the carrier assembly 220 with respect to the ion implantation assembly 210 is not limited in this application, and the rotation angle of the carrier assembly 220 with respect to the ion implantation assembly 210 may be, but is not limited to, 0 degree, 30 degrees, 45 degrees, 90 degrees, 120 degrees, or the like.
In this embodiment, by rotating the carrier assembly 220 relative to the ion implantation assembly 210, an angle that can be formed between a plane where the carrier surface 221 is located and a plane where the ion injection port 211 is located is adjusted to adjust an angle between the target object carried on the carrier surface 221 and the ion injection port 211, so that the ion implantation assembly 210 can perform ion implantation on different target objects, thereby realizing multiple functions of the ion implantation apparatus 200.
In the embodiment of the present invention, after the robot grips the target object, the target object is placed on the supporting surface 221, and the ion implantation apparatus 200 rotates the supporting assembly 220 through a set procedure, so that the target object on the supporting surface 221 reaches a target position relative to the ion injection opening 211, and at this time, the ion beam penetrates through the ion injection opening 211 and is driven into the target object.
With continued reference to fig. 7 and 8, fig. 7 is a schematic structural view of the carrier assembly shown in fig. 5 in a first state; fig. 8 is a schematic structural view of the load bearing assembly shown in fig. 5 in a second state. The carrier assembly 220 includes a carrier table 222. The carrying surface 221 is disposed on the carrying stage 222. The carrying platform 222 is used for carrying a target and driving the target to rotate relative to the ion injection port 211. In the present embodiment, the supporting stage 222 of the supporting assembly 220 rotates relative to the ion injection port 211 to adjust an angle between the target object supported on the supporting surface 221 and the ion injection port 211.
Referring to fig. 9 and 10 together, fig. 9 is a schematic structural diagram of a portion of the ion implantation apparatus 200 shown in fig. 5 when the structure is in a first position; fig. 10 is a schematic diagram of a portion of the ion implantation apparatus 200 shown in fig. 5 in a second position. The ion implantation apparatus 200 further comprises a shield 250, the shield 250 being mounted to the carrier assembly 220. When the shutter 250 covers the target 300, the shutter 250 can block part of the ions so that the ions are implanted only in a partial region of the target 300. Illustratively, the ion implantation apparatus 200 further comprises a connector 260. The connector 260 has one end connected to the carrier assembly 220 and the other end connected to the shroud 250. It will be appreciated that the shield 250 is mounted to the carriage assembly 220 by a connector 260.
In some embodiments, the connection member 260 rotates relative to the carrier assembly 220 to rotate the covering member 250 relative to the carrier assembly 220, so as to change the relative position of the covering member 250 to the bearing surface 221.
As shown in FIG. 9, when the cover 250 is in the first position relative to the carrier assembly 220, the cover 250 is disposed opposite the bearing surface 221, i.e., the projection of the cover 250 on the bearing surface 221 overlaps the projection of the object 300 on the bearing surface 221. As shown in FIG. 10, when the cover 250 is in the second position relative to the carrier assembly 220, the cover 250 is disposed at a position offset from the bearing surface 221, i.e., the projection of the cover 250 on the bearing surface 221 does not overlap with the projection of the object 300 on the bearing surface 221.
In the embodiment of the present application, the shielding member 250 rotates relative to the carrier assembly 220, and when ion implantation is performed on the target 300 without shielding a portion of ions, the projection of the shielding member 250 and the wafer do not overlap; when partial ion shielding is required for ion implantation of a target, ion implantation is performed on a partial region of the target 300 by rotating the shielding member 250 so that the shielding member 250 overlaps with the projection of the wafer.
Continuing to refer to fig. 11, fig. 11 is a top view of the covering piece 250 shown in fig. 9 in the first embodiment. The shielding member 250 includes a plurality of shielding bars 251 arranged at intervals, and a gap 252 is provided between any adjacent two shielding bars 251. Ions can pass through the shield 250 through the gap 252 and not through the shield strips 251.
Wherein, the cover 250 moves or rotates relative to the carrier assembly 220, and when the cover 250 is at the first position relative to the carrier assembly 220, the cover 250 covers part or all of the carrier surface 221; when the shielding member 250 is at the second position relative to the carrier assembly 220, the shielding member 250 is disposed in a staggered manner with respect to the bearing surface 221.
In the present embodiment, when the shielding member 250 is located at the first position relative to the carrier assembly 220, the shielding member 250 is located between the ion injection port 211 and the carrying surface 221, and the shielding member 250 covers at least a portion of the carrying surface 221, the ion beam emitted from the ion injection port 211 can only partially pass through the gap 252 to be injected into a partial region of the target. When the shielding member 250 is located at the second position relative to the carrier assembly 220, the projection of the shielding member 250 and the carrying surface 221 is disposed in a staggered manner, that is, the shielding member 250 does not shield the carrying surface 221, and the ion beam emitted from the ion injection port 211 is directly injected into the whole region of the target without passing through the shielding member 250.
In some embodiments, the plurality of shielding bars 251 are arranged in a first direction, and the shielding bars 251 extend in a second direction. The first direction and the second direction are arranged crosswise. Illustratively, the first direction is perpendicular to the second direction, and any two of the shutter bars 251 are parallel to each other. As shown in fig. 11, the shielding member 250 has a plurality of shielding bars 251 in a stripe shape. The plurality of shielding bars 251 are spaced apart from one another to form a plurality of spaced apart gaps 252.
In the embodiment of the present application, the ion implantation apparatus 200 is provided with the shielding member 250, the shielding member 250 is provided with a plurality of gaps 252 arranged at intervals along the first direction, each gap 252 extends along the second direction, and after the ion beam emitted from the ion injection port 211 passes through the shielding member 250, the ions are implanted into the surface of the target object arranged at intervals along the first direction and extend along the second direction, so that the ions are only implanted into a partial region of the target object, the warping degree of the target object along a certain direction is improved, the difference between the warping degree of the target object in the first direction and the warping degree of the target object in the second direction is reduced, and the flatness of the target object is improved.
In some cases, when the degree of warpage of the target in the first direction is greater than the degree of warpage in the second direction, the extending direction of the plurality of gaps 252 in the shutter 250 is along the first direction when the target is ion-implanted, so that ions are implanted into the surface of the target at intervals in the second direction, so that the target only reduces the degree of warpage in the first direction, or the degree of decrease in the degree of warpage in the first direction is greater than the degree of decrease in the degree of warpage in the second direction, so as to reduce the difference between the degree of warpage in the target in the first direction and the degree of warpage in the second direction.
In other cases, when the warpage of the target in the second direction is greater than the warpage in the first direction, the extending direction of the plurality of gaps 252 in the shutter 250 during ion implantation of the target is along the second direction, so that the ions are implanted into the surface of the target at intervals along the first direction, such that the target only reduces the warpage in the second direction, or the warpage in the second direction is reduced by a greater magnitude than the warpage in the first direction, so as to reduce the difference between the warpage in the target in the first direction and the warpage in the second direction.
In this embodiment, the direction in which the plurality of shielding bars 251 or the plurality of gaps 252 in the shielding member 250 are arranged with respect to the target is changed by rotating the shielding member 250, so that the shielding member 250 can adjust the extending direction of the gaps 252 according to the difference in the warping degree of each direction in the target, so that the ion implantation apparatus 200 can adapt to different targets.
Continuing to refer to fig. 12, fig. 12 is a top view of the covering piece 250 of fig. 9 in a second embodiment. The shielding bar 251 includes a plurality of flat portions 253 and a plurality of protruding portions 254, and the plurality of protruding portions 254 protrude relative to the plurality of flat portions 253. The plurality of flat portions 253 and the plurality of convex portions 254 are alternately arranged, and the plurality of flat portions 253 and the plurality of convex portions 254 are all arranged along the second direction. Illustratively, as shown in fig. 12, the shielding bar 251 is wavy. In other embodiments, the shield 250 can take on other shapes as well, and the application is not limited. For example, the masking strip 251 may have a square wave shape, an electrocardiogram shape, or the like.
In this embodiment, the shielding bar 251 is provided with a plurality of protrusions 254, that is, the gap 252 is provided with a plurality of protrusions in the first direction when extending along the second direction, so that when ions pass through the shielding bar 251, most ions are injected along the first direction of the target object, and a small part of ions are injected along the second direction of the target object.
It is to be understood that the present application does not limit the shape of the shielding bar 251, and those skilled in the art can design the shape of the shielding bar 251 according to actual needs.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the methods and their core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:
providing a substrate;
forming a stacking layer on the substrate, and etching the stacking layer to form a channel hole penetrating through the stacking layer;
and ion implantation is carried out on the surface of the stacked layer, which faces away from the substrate.
2. The method of claim 1, wherein the ion implanting the stack of layers comprises:
disposing a patterned shield over the stack of layers; the patterned shielding piece comprises a plurality of shielding strips arranged at intervals along the same direction, and a gap is formed between any two adjacent shielding strips;
ions are implanted into the stack of layers through the gap through the patterned shield.
3. The method of fabricating a three-dimensional memory according to claim 2, wherein prior to the "implanting ions into the stack" the method further comprises:
detecting the warping degree of the stacked layers along a first direction and the warping degree of the stacked layers along a second direction; wherein the first direction and the second direction are arranged crosswise;
when the warping degree in the first direction is larger than that in the second direction, a plurality of shielding strips are arranged at intervals along the second direction, and the gaps extend along the first direction;
when the warping degree of the second direction is larger than that of the first direction, a plurality of shielding strips are arranged at intervals along the first direction, and the gaps extend along the second direction.
4. The method of fabricating a three-dimensional memory according to claim 1, wherein prior to the "implanting ions into the stack" the method further comprises:
a memory stem is formed along the channel hole.
5. The method of fabricating a three-dimensional memory according to any one of claims 1 to 4, wherein after the "ion implanting the stack layer", the method further comprises:
and adsorbing the surface of the substrate, which is far away from the stacked layer, so as to transfer the substrate and the stacked layer on the substrate to a position to be etched.
6. The method of fabricating a three-dimensional memory according to any one of claims 1 to 4, wherein after the "ion implanting the stack layer", the method further comprises:
binding an object to be bound on the surface of the stacked layers; wherein the object to be bound is electrically connected with the stack layer.
7. An ion implantation device is characterized by comprising an ion implantation assembly and a bearing assembly, wherein the ion implantation assembly is provided with an ion injection hole, and the bearing assembly is provided with a bearing surface for bearing a target object;
the ion implantation device also comprises a shielding piece, wherein the shielding piece comprises a plurality of shielding strips which are arranged at intervals, and a gap is arranged between any two adjacent shielding strips; when the ion implantation device is in a first state, the shielding piece is positioned between the ion injection port and the bearing surface.
8. The ion implantation system of claim 7, wherein a plurality of said shielding bars are arranged along a first direction and said shielding bars extend along a second direction, said first direction being arranged crosswise to said second direction.
9. The ion implantation apparatus as claimed in claim 8, wherein the shielding strip comprises a plurality of flat portions and a plurality of protrusions, the plurality of protrusions are protruded with respect to the plurality of flat portions, the plurality of flat portions and the plurality of protrusions are alternately disposed, and the plurality of flat portions and the plurality of protrusions are arranged along the second direction.
10. The ion implantation device according to any of claims 7 to 9, wherein the carrier assembly rotates relative to the ion implantation assembly, and when the ion implantation device is in the first state, a plane of the carrier surface is parallel to a plane of the opening of the ion injection port; when the ion implantation device is in a second state, the plane where the bearing surface is located is intersected with the plane where the opening of the ion injection port is located.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951834A (en) * 2021-02-22 2021-06-11 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100084584A1 (en) * 2008-10-03 2010-04-08 Nissin Ion Equipment Co., Ltd. Ion implanting apparatus
US20100308236A1 (en) * 2009-06-08 2010-12-09 Varian Semiconductor Equipment Associates, Inc. Masking apparatus for an ion implanter
JP2011100860A (en) * 2009-11-06 2011-05-19 Sumitomo Electric Ind Ltd Ion-implanted group-iii nitride semiconductor substrate, bonding substrate for group-iii nitride semiconductor layer, and method for manufacturing group-iii nitride semiconductor device
CN109119334A (en) * 2018-08-24 2019-01-01 长江存储科技有限责任公司 The surface modification method of semiconductor structure and the manufacturing method of 3D memory device
CN109727852A (en) * 2018-12-29 2019-05-07 长江存储科技有限责任公司 A kind of method, apparatus and equipment improving silicon wafer warpage

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100084584A1 (en) * 2008-10-03 2010-04-08 Nissin Ion Equipment Co., Ltd. Ion implanting apparatus
US20100308236A1 (en) * 2009-06-08 2010-12-09 Varian Semiconductor Equipment Associates, Inc. Masking apparatus for an ion implanter
JP2011100860A (en) * 2009-11-06 2011-05-19 Sumitomo Electric Ind Ltd Ion-implanted group-iii nitride semiconductor substrate, bonding substrate for group-iii nitride semiconductor layer, and method for manufacturing group-iii nitride semiconductor device
CN109119334A (en) * 2018-08-24 2019-01-01 长江存储科技有限责任公司 The surface modification method of semiconductor structure and the manufacturing method of 3D memory device
CN109727852A (en) * 2018-12-29 2019-05-07 长江存储科技有限责任公司 A kind of method, apparatus and equipment improving silicon wafer warpage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951834A (en) * 2021-02-22 2021-06-11 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof

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