CN109037314B - Transistor and manufacturing method thereof - Google Patents
Transistor and manufacturing method thereof Download PDFInfo
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- CN109037314B CN109037314B CN201810927553.XA CN201810927553A CN109037314B CN 109037314 B CN109037314 B CN 109037314B CN 201810927553 A CN201810927553 A CN 201810927553A CN 109037314 B CN109037314 B CN 109037314B
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- 229910052787 antimony Inorganic materials 0.000 description 8
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 8
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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Abstract
The invention relates to a transistor and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate of a first conductivity type, and growing an epitaxial layer over the substrate; forming a trench in the epitaxial layer, the trench penetrating the epitaxial layer and being connected to the substrate, the trench extending in a non-linear shape in a direction parallel to the substrate surface; forming a side wall on the side wall of the groove; forming an emitter region of a second conductivity type within the trench; removing the side wall to form a base region trench; and forming a base region of the first conductivity type in the base region trench. The transistor formed by the method has low cost and high amplification factor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transistor and a manufacturing method thereof.
Background
Transistors have two basic structures: PNP type and NPN type. In the 3 layers of semiconductors, the middle layer is called a base region, and the outer two layers are called an emitter region and a collector region respectively. When a small amount of current is injected into the base region, a larger current is formed between the emitter region and the collector region, which is the amplifying effect of the transistor. However, in the prior art, if the transistor needs to adjust the saturated collector current of the device, the current can only be achieved by changing the numbers of the base region and the emitter region, which necessitates an additional increase in the area of the chip and a complicated process, which is very disadvantageous in terms of cost control.
Disclosure of Invention
The embodiment of the invention provides a transistor and a manufacturing method thereof, which can increase the current amplification factor on the premise of not increasing the area of a device, and has the advantages of low cost, simple process, high reliability and stable performance.
In a first aspect, the present invention provides a transistor, a substrate of a first conductivity type; an epitaxial layer of a second conductivity type grown over the substrate; an emitter region of a second conductivity type, the emitter region being connected to the substrate through the epitaxial layer, the emitter region extending in a non-linear shape in a direction parallel to the substrate surface; and a base region of the first conductivity type, the base region being connected to the substrate through the epitaxial layer, and the base region being located at one side of the emitter region and extending in a non-linear shape along the emitter region.
In a second aspect, the present invention provides a method for manufacturing a transistor, the method comprising: providing a substrate of a first conductivity type, and growing an epitaxial layer over the substrate; forming a trench in the epitaxial layer, the trench penetrating the epitaxial layer and being connected to the substrate, the trench extending in a non-linear shape in a direction parallel to the substrate surface; forming a side wall on the side wall of the groove; forming an emitter region of a second conductivity type within the trench; removing the side wall to form a base region trench; and forming a base region of the first conductivity type in the base region trench.
According to the embodiment of the invention, the tortuous grooves and the tortuous extending emitter regions and base regions are formed in the tortuous grooves, so that the contact area between the base regions and the emitter regions is increased, the saturated collector current of the device is increased on the premise of not increasing the area of the device and the process cost, and the amplification factor of the device is greatly increased.
Drawings
The invention will be further described with reference to the drawings and examples.
Fig. 1 is a flow chart of a method for fabricating a transistor according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure of a transistor according to an embodiment of the present invention;
fig. 3, fig. 4, fig. 5, fig. 7, fig. 8, fig. 9, fig. 10, fig. 12 and fig. 13 are schematic cross-sectional views of a method for fabricating a transistor according to an embodiment of the present invention;
fig. 6 and 11 are schematic top view structures of a method for fabricating a transistor according to an embodiment of the present invention;
reference numerals illustrate: 1. a substrate; 2. an epitaxial layer; 3. an emission region; 4. a base region; a1, grooves; a2, a base region trench; b1, a side wall; 51. a collector contact region; 51. a collector region; 6. a dielectric layer; 71. a collector electrode; 72. a base; 73. an emitter.
Detailed Description
In order to make the objects, technical solutions and advantageous technical effects of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or are directions or positional relationships conventionally put in use of the inventive product, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Referring to fig. 1 and 2, a method for fabricating a transistor includes:
step S01: providing a substrate 1 of a first conductivity type, and growing an epitaxial layer 2 of a second conductivity type over the substrate 1;
step S02: forming a groove a1 in the epitaxial layer 2, wherein the groove a1 penetrates through the epitaxial layer 2 and is connected with the substrate 1, and the groove a1 extends in a non-linear shape in a direction parallel to the surface of the substrate 1;
step S03: forming a side wall b1 on the side wall of the groove a 1;
step S04: forming an emitter region 3 of a second conductivity type within the trench a 1;
step S05: removing the side wall b1 to form a base region trench a2;
step S06: a base region 4 of the first conductivity type is formed in the base trench a 2.
It can be understood that by forming a meandering trench in the epitaxial layer 2, and forming the meandering emitter region 3 and the base region 4 in the trench, the contact area between the base region 4 and the emitter region 3 is further increased, so that the saturated collector current of the device is increased without increasing the area and the process cost of the device, and the amplification factor of the device is greatly increased.
The method of forming the transistor described above is described in detail below with reference to the accompanying drawings.
For convenience of the following description, specific details are set forth herein: the first conductivity type may be N-type, and the second conductivity type may be P-type, whereas the first conductivity type may be P-type, and the second conductivity type may be N-type. In the following embodiments, the first conductivity type is P-type and the second conductivity type is N-type are described as examples, but the present invention is not limited thereto.
Referring to fig. 3 and 4, step S01 is performed: providing a substrate 1 of a first conductivity type, growing an epitaxial layer over the substrate 1; specifically, the substrate 1 serves as a carrier of the transistor and mainly plays a supporting role. In this embodiment, the substrate 1 is made of a silicon substrate 1, and silicon is the most common, inexpensive and stable semiconductor material. In this embodiment, the substrate 1 is P-type lightly doped, the doping ion is boron ion, in other embodiments, indium or gallium ion may be used, in other embodiments, the substrate 1 may be N-type lightly doped, and the doping ion may be other pentavalent ions such as phosphorus, arsenic or antimony. The thickness and concentration of the epitaxial layer 2 are closely related to the withstand voltage of the device, typically with a resistivity of 5-50ohm cm and a thickness of between 5-10 um. Preferably, the epitaxial layer 2 is formed by homoepitaxy with a relatively simple process, i.e. the material of the epitaxial layer 2 is the same as the material of the substrate 1, and when the material of the substrate 1 is silicon, the material of the epitaxial layer 2 is also silicon. In other embodiments, the epitaxial layer 2 may also be formed by heteroepitaxy. The epitaxial layer 2 may be formed on the first surface of the substrate 1 by an epitaxial growth method, and the doping type of the epitaxial layer 2 is opposite to the doping type of the substrate 1, in this embodiment, the substrate 1 is P-type doped, the epitaxial layer 2 is N-type doped, and in other embodiments, if the substrate 1 is N-type doped, the epitaxial layer 2 is P-type doped. In this embodiment, the doping ions of the epitaxial layer 2 are specifically phosphorus ions, and in other embodiments, the doping ions of the epitaxial layer 2 may be other pentavalent ions such as arsenic or antimony. More specifically, the epitaxial growth method is preferably a chemical vapor deposition method (or vapor phase epitaxial growth method), which is a process of reacting a gaseous reaction raw material on the surface of a solid substrate and depositing a thin solid layer or film, is a relatively mature epitaxial growth method of a transistor, and sprays silicon and a doping element on the substrate 1, and has good uniformity, repeatability and step coverage.
Referring to fig. 5 and 6, step S02 is performed: forming a groove a1 in the epitaxial layer 2, wherein the groove a1 penetrates through the epitaxial layer 2 and is connected with the substrate 1, and the groove a1 extends in a non-linear shape in a direction parallel to the surface of the substrate 1; specifically, the process of forming the trench a1 may be: an etching barrier layer (not shown) is formed on the epitaxial layer 2, then a photoresist layer (not shown) is formed on the etching barrier layer, then the photoresist layer is exposed by using a mask plate with the pattern of the groove a1, and then development is carried out, so that the photoresist layer with the pattern of the groove a1 is obtained. And etching the etching barrier layer by using the photoresist layer with the pattern of the groove a1 as a mask and adopting etching methods such as a reactive ion etching method and the like to form a pattern opening (not shown) of the groove a1. And then removing the epitaxial layer 2 area which is not covered by the etching barrier layer by adopting wet etching or dry etching and other methods by taking the etching barrier layer with the pattern opening of the groove a1 as a mask, thereby forming the groove a1 in the epitaxial layer 2. Thereafter, chemical cleaning or the like may be used to remove the photoresist layer and the etch stop layer. In the above process, in order to secure exposure accuracy, an anti-reflection layer may be further formed between the photoresist layer and the etch stop layer. It should be noted that the non-linear shape extension means that the contact surfaces formed by the two sides of the trench and the epitaxial layer are non-planar, the trench a1 may extend in a curved manner or may extend in a broken line in a direction parallel to the surface of the substrate 1, and may even include a portion extending in a curved manner or may include a portion extending in a broken line, and the shape of the trench a1 may be regular or irregular. The extending shape of the groove a1 in the direction parallel to the surface of the substrate 1 has at least one corner, the shape of the corner can be a rounded corner, a right angle corner or an acute angle corner, in this embodiment, the number of the corners is 3, and the corner angle of the extending shape of the groove a1 in the direction parallel to the surface of the substrate 1 is preferably a right angle corner, and the use of the right angle corner makes the process simpler and easier to implement, and has the effect of enhancing the electric field strength. The width of the trench a1 may be changed or unchanged when extending in a non-linear shape in a direction parallel to the surface of the substrate 1, and in order to ensure the performance of the device, in this embodiment, the width of the trench a1 is always kept unchanged when extending, and the width of the trench a1 is preferably between 3 and 5 um.
Referring to fig. 7, step S03 is performed: forming a side wall b1 on the side wall of the groove a 1; specifically, the forming step of the side wall b1 specifically includes: depositing an insulating layer on the upper surface of the epitaxial layer 2 and the bottom surface and the side wall of the groove a 1; and etching the insulating layer back to form the side wall b1. More specifically, the thickness of the insulating layer (the width of the side wall) is consistent with the width of the base region, and the insulating layer (the side wall) is made of one or a combination of more than one of silicon dioxide, silicon nitride, aluminum oxide, silicon oxynitride and the like, and in this embodiment, the width of the side wall b1 is between 3000A and 5000A, and the material is silicon oxide. Since the trench a1 extends in a non-linear shape in a direction parallel to the surface of the substrate 1, the sidewall a1 thus formed also extends in a non-linear shape along the trench a1 in a direction parallel to the surface of the substrate 1.
Referring to fig. 8, step S04 is performed: forming an emitter region 3 of the second conductivity type within the trench a1, specifically, the step of forming the emitter region 3 of the second conductivity type within the trench a1 includes: filling polysilicon of a second conductivity type in the trench a1 by an epitaxial growth method; and forming the emitting region 3 by performing photoetching and etching processes of polysilicon. More specifically, polysilicon fills the trench a1 at other positions after the side wall is formed, in this embodiment, the doped ion of the emitter region 3 is a phosphorus ion, and in other embodiments, the doped ion of the emitter region 3 may also be other pentavalent ions such as arsenic or antimony. More specifically, the emitter region a1 is formed by spraying silicon and a doping element onto the substrate 1 by a chemical vapor deposition method, and the doping concentration thereof is 5E15-9E15/cm3. In order to prevent the formation of the emitter region 3 from affecting the upper surface of the epitaxial layer 2, a barrier layer (not shown) may be further formed on the upper surface of the epitaxial layer 2 of the second conductivity type before the step of forming the emitter region 3 after the formation of the sidewall b1. The barrier layer is formed by the following steps: firstly, depositing a layer of insulating material on the upper surface of the epitaxial layer 2 and one side of the side wall b1 far away from the epitaxial layer 2 and the bottom surface of the groove a1, removing the insulating material on the side surface of the side wall b1 far away from the epitaxial layer 2 and the bottom surface of the groove 2 through a dry etching process or a wet etching process, and reserving the insulating material on the upper surface of the epitaxial layer 2 so as to form the barrier layer. The material of the barrier layer can be one or a combination of more than one of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride and the like, and the material of the side wall and the material of the barrier layer can be the same or different. It can be understood that, by forming the emitter region 3 in an epitaxial manner, the ion concentration and thickness of the emitter region 3 can be controlled more precisely than those of the emitter region 3 in an ion implantation manner, so that the good performance of the transistor provided by the invention is further ensured. Since the trench a1 extends in a nonlinear shape in a direction parallel to the surface of the substrate 1, the emitter region 3 thus formed also extends in a nonlinear shape along the trench a1 in a direction parallel to the surface of the substrate 1.
Referring to fig. 9, step S05 is performed: removing the side wall to form a base region trench a2, wherein the base region trench a2 extends in a nonlinear shape in a direction parallel to the surface of the substrate 1; specifically, the side wall b1 is removed by etching, and the barrier layer is removed at the same time as the side wall b1, and it should be noted that the barrier layer may be removed simultaneously with the side wall b1, or may be removed separately. More specifically, the etching mode is wet etching, and the wet etching has strong adaptability to a dry method, good surface uniformity, less damage to a silicon wafer and simpler process.
Referring to fig. 10 and 11, step S06 is performed: forming a base region of a first conductivity type in the base region trench a2; similarly, the base region 4 extends in a non-linear shape along the base region trench a2 in a direction parallel to the substrate surface, and similarly, the base region 4 is formed in the base region trench a2 by an epitaxial growth method, and a process for forming the base region trench a2 is substantially similar to a process for forming the trench a1, which is not described in detail herein. Specifically, in this embodiment, the width of the base region 4 is 0.3-0.5um, in this embodiment, the first conductivity type is P-type, the doped ion of the base region 4 is a phosphorus ion, in other embodiments, the doped ion of the base region 4 may be other pentavalent ions such as arsenic or antimony, and the doping concentration of the base region 4 is 2E13-5E13/cm3. It can be understood that by forming the meandering trench a1 on the epitaxial layer 2, the contact area between the base region 4 and the emitter region 3 is further increased, so that the saturated collector current of the device can be increased without increasing the area of the device, and the amplification factor of the device is greatly increased. The width of the base region 4 is defined through the side wall b1, and the base region 4 is formed in an epitaxial mode, so that the width and the doping concentration of the base region 4 are accurately controlled, the transistor is further ensured to have a stable current amplification coefficient, and in addition, in the invention, the base region 4 is longitudinally arranged, and the contact surfaces of the base region 4 and the emitter region 3 are prevented from being influenced by processes such as ion implantation, high-temperature annealing and the like.
Further, after the step of forming the base region 4 of the first conductivity type in the base trench a2, the method further includes: and performing a rapid thermal annealing process of the emitter region 3, wherein the annealing temperature is 900-950 degrees, and the annealing time is 15-30s, so as to form a good interface state between the emitter region 3 and the base region 4.
Referring to fig. 12, further, after forming the base region 4, the method further includes: forming a collector contact region 51 of a second conductivity type in a region of the epitaxial layer 2 on a side away from the base region 4 through a first implantation, wherein a collector region 52 is a region of the epitaxial layer 2 between the collector contact region 51 and the base region 4; the collector contact region 51 has a higher doping concentration than the collector region 52; the collector region 52 is lightly doped, and the subsequent electrode is not in good contact with the lightly doped collector region 52, so the heavily doped collector contact region 51 is used here to improve the contact performance; specifically, the collector contact region 51 penetrates the epitaxial layer 2 and has one end in contact with the first surface of the substrate 1. More specifically, the first implanted ions are phosphorus ions, and the implantation concentration is between 8E15 and 1E16/cm 3. The collector region 52 is electrically connected between the base region 4 and the collector contact region 51, the breakdown voltage of the transistor being related to its doping concentration.
Referring to fig. 13, further, the method for manufacturing the transistor further includes: growing a dielectric layer 6 on the epitaxial layer 2 and the upper side and forming a collector 71, a base 72 and an emitter 73 on the dielectric layer 6; and electrically connecting the collector 71 with the collector contact region 51 through the dielectric layer 6, and electrically connecting the base 72 with the base region 4 through the dielectric layer 6; and electrically connecting the emitter 73 with the emitter region through the dielectric layer 6. Specifically, the dielectric layer 6 covers the upper surfaces of the base region 4, the emitter region 3, the collector region 52 and the collector contact region 51, and the dielectric layer 6 is formed with a collector contact hole, a base contact hole and an emitter contact hole; the collector 71 is electrically connected to the collector contact region 51 through the collector contact hole, the base 72 is electrically connected to the base region 4 through the base contact hole, and the emitter 73 is electrically connected to the emitter region through the emitter contact hole. In some embodiments of the present invention, the dielectric layer 6 is made of a material such as silicon dioxide, so that the purpose of forming the dielectric layer 6 is to isolate the device layers, and the collector contact hole, the base contact hole and the emitter contact hole are respectively located above the collector contact region 51, the base region 4 and the emitter region, and are formed by conventional processes such as photolithography and etching.
Further, in order to obtain a flat surface, before the step of growing the dielectric layer 6 over the epitaxial layer 2 and forming the collector 71, the base 72 and the emitter 73 on the dielectric layer 6, a planarization operation is further required for the upper surface of the epitaxial layer 2. The planarization operation is specifically performed by chemical mechanical polishing, which is a common method for those skilled in the art and will not be described herein.
It should be noted that the transistor formed according to the present method may have a single-sided structure or a double-sided structure, that is, the base region 4, the collector region 52, the collector contact region 51, the collector 71, the base 72, the collector contact hole and the base contact hole may be formed only on one side of the emitter region 3, or may be symmetrically formed on two opposite sides of the emitter region 3, that is, the base region 4, the collector region 52, the collector contact region 51, the collector 71, the base 72, the collector 71 contact hole or the base contact hole may be formed with a first portion located on one side of the emitter region 3 and a second portion formed on the other side of the emitter region 3, respectively, in this embodiment, the transistor has a double-sided structure.
Referring to fig. 2 again, a transistor is manufactured based on the above manufacturing method, and includes:
a substrate 1 of a first conductivity type; an epitaxial layer 2 of a second conductivity type grown over the substrate 1; an emitter region 3 of a second conductivity type, the emitter region 3 being connected to the substrate 1 through the epitaxial layer 2, the emitter region 3 extending in a non-linear shape in a direction parallel to the surface of the substrate 1; and a base region 4 of the first conductivity type, the base region 4 being connected to the substrate 1 through the epitaxial layer 2, and the base region 4 being located on one side of the emitter region 3 and extending in a non-linear shape along the emitter region 3 in a direction parallel to the surface of the substrate 1.
It can be understood that by forming the emitter region 3 and the base region 4 which are in contact with each other and extend in a non-linear shape in a direction parallel to the surface of the substrate 1, the contact area between the base region 4 and the emitter region 3 is further increased, and thus the saturated collector current of the device can be increased without increasing the area of the device and the process cost, and the amplification factor of the device is greatly increased.
Further, the substrate 1 serves as a carrier of the transistor and mainly plays a supporting role. In this embodiment, the substrate 1 is made of a silicon substrate 1, and silicon is the most common, inexpensive and stable semiconductor material. In this embodiment, the substrate 1 is P-type lightly doped, the doping ion is boron ion, in other embodiments, indium or gallium ion may be used, in other embodiments, the substrate 1 may be N-type lightly doped, and the doping ion may be other pentavalent ions such as phosphorus, arsenic or antimony.
Further, the thickness and concentration of the epitaxial layer 2 are closely related to the withstand voltage of the device, and the resistivity is usually 5-50ohm.cm, and the thickness is 5-10 um. Preferably, the epitaxial layer 2 is formed by homoepitaxy with a relatively simple process, i.e. the material of the epitaxial layer 2 is the same as the material of the substrate 1, and when the material of the substrate 1 is silicon, the material of the epitaxial layer 2 is also silicon. In other embodiments, the epitaxial layer 2 may also be formed by heteroepitaxy. The epitaxial layer 2 may be formed on the first surface of the substrate 1 by an epitaxial growth method, and the doping type of the epitaxial layer 2 is opposite to the doping type of the substrate 1, in this embodiment, the substrate 1 is P-type doped, the epitaxial layer 2 is N-type doped, and in other embodiments, if the substrate 1 is N-type doped, the epitaxial layer 2 is P-type doped. In this embodiment, the doping ions of the epitaxial layer 2 are specifically phosphorus ions, and in other embodiments, the doping ions of the epitaxial layer 2 may be other pentavalent ions such as arsenic or antimony. More specifically, the epitaxial growth method may be a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, a vacuum vapor deposition growth method, a high frequency sputtering growth method, a molecular beam epitaxial growth method, or the like, preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), which is a process of reacting a gaseous reaction raw material on a solid substrate surface and depositing a solid thin layer or film, is a relatively mature epitaxial growth method of a transistor, and sprays silicon and a doping element onto the substrate 1, and has good uniformity, repeatability, and step coverage.
Further, the material of the emitter region 3 is polysilicon, and the doped ions thereof are phosphorus ions, and in other embodiments, the doped ions of the emitter region 3 may be other pentavalent ions such as arsenic or antimony. More specifically, the emitter region 3 is formed by spraying silicon and a doping element onto the substrate 1 by a chemical vapor deposition method, and the doping concentration thereof is 5E15-9E15/cm3. It can be understood that, by forming the emitter region 3 in an epitaxial manner, the ion concentration and thickness of the emitter region 3 can be controlled more precisely than those of the emitter region 3 in an ion implantation manner, so that the good performance of the transistor provided by the invention is further ensured.
Further, the width of the base region 4 is 0.3-0.5um, which is formed by an epitaxial growth method, in this embodiment, the first conductivity type is P-type, the doped ion of the base region 4 is a phosphorus ion, in other embodiments, the doped ion of the base region 4 may be other pentavalent ions such as arsenic or antimony, and the doping concentration of the base region 4 is 2E13-5E13/cm3. It can be understood that by forming the meandering base region 4 and the emitter region 3 connected with the base region on the epitaxial layer 2, the contact area between the base region 4 and the emitter region 3 is increased, so that the saturated collector current of the device can be increased without increasing the device area and the manufacturing process, and the amplification factor of the device is greatly increased. The base region 4 is formed in an epitaxial mode, so that the width and the doping concentration of the base region 4 are accurately controlled, the transistor is further guaranteed to have a stable current amplification factor, and in addition, the base region 4 is longitudinally arranged, and the contact surfaces of the base region 4 and an emitter region are prevented from being influenced by processes such as ion implantation, high-temperature annealing and the like.
Further, the transistor further comprises a collector contact region 51 and a collector region 52, wherein the collector region 51 is located at a side of the base region 4 away from the emitter 3 region, and the collector contact region 51 is located at a side of the collector region 52 away from the base region 4. The collector contact region 51 has a higher doping concentration than the collector region 52; the collector region 52 is lightly doped, and the subsequent electrode is not in good contact with the lightly doped collector region 52, so the heavily doped collector contact region 51 is used here to improve the contact performance; specifically, the collector contact region 51 penetrates the epitaxial layer 2 and has one end in contact with the first surface of the substrate 1. More specifically, the first implanted ions are phosphorus ions, and the implantation concentration is between 8E15 and 1E16/cm 3. The collector region 52 is electrically connected between the base region 4 and the collector contact region 51, the breakdown voltage of the transistor being related to its doping concentration.
Further, the transistor further includes: a dielectric layer 6 grown on the epitaxial layer 2, and a collector 71, a base 72 and an emitter 73 grown on the dielectric layer 6, wherein the collector 71 is electrically connected to the collector contact region 51 through the dielectric layer 6, and the base 72 is electrically connected to the base region 4 through the dielectric layer 6; and electrically connecting the emitter 73 with the emitter region through the dielectric layer 6. Specifically, the dielectric layer 6 covers the upper surfaces of the base region 4, the emitter region 3, the collector region 52 and the collector contact region 51, and the dielectric layer 6 is formed with a collector contact hole, a base contact hole and an emitter contact hole; the collector 71 is electrically connected to the collector contact region 51 through the collector contact hole, the base 72 is electrically connected to the base region 4 through the base contact hole, and the emitter 73 is electrically connected to the emitter region through the emitter contact hole. In some embodiments of the present invention, the dielectric layer 6 may be made of silicon dioxide, etc., and the purpose of forming the dielectric layer 6 is to isolate the device layers, where the collector contact hole, the base contact hole, and the emitter contact hole are located above the collector contact region 51, the base region 4, and the emitter region, respectively, and are formed by conventional processes such as photolithography and etching.
It should be noted that the transistor formed according to the present method may have a single-sided structure or a double-sided structure, that is, the base region 4, the collector region 52, the collector contact region 51, the collector 71, the base 72, the collector contact hole and the base contact hole may be formed only on one side of the emitter region 3, or may be symmetrically formed on two opposite sides of the emitter region 3, that is, the base region 4, the collector region 52, the collector contact region 51, the collector 71, the base 72, the collector 71 contact hole or the base contact hole may be formed with a first portion located on one side of the emitter region 3 and a second portion formed on the other side of the emitter region 3, respectively, in this embodiment, the transistor has a double-sided structure.
Claims (6)
1. A method of fabricating a transistor, the method comprising:
providing a substrate of a first conductivity type, and growing an epitaxial layer of a second conductivity type over the substrate;
forming a trench in the epitaxial layer, the trench penetrating the epitaxial layer and being connected to the substrate, the trench extending in a non-linear shape in a direction parallel to the substrate surface;
forming a side wall on the side wall of the groove;
forming an emitter region of a second conductivity type within the trench;
removing the side wall to form a base region trench;
forming a base region of a first conductivity type in the base region trench;
forming a collector contact region of a second conductivity type in a region of the epitaxial layer, which is far away from one side of the base region, through first injection, wherein a collector region is formed in the epitaxial layer region between the collector contact region and the base region;
growing a dielectric layer above the epitaxial layer, forming a collector electrode, a base electrode and an emitter electrode on the dielectric layer, electrically connecting the collector electrode with the collector electrode contact region through the dielectric layer, and electrically connecting the base electrode with the base region through the dielectric layer; and electrically connecting the emitter with the emitter region through the dielectric layer.
2. The method of claim 1, wherein after the step of forming a sidewall on the trench sidewall, before the step of forming an emitter of a second conductivity type within the trench, the method further comprising: forming a barrier layer over the epitaxial layer;
the step of removing the side wall further comprises: and removing the barrier layer.
3. The method of claim 1, wherein forming an emitter region of a second conductivity type within the trench comprises:
filling polysilicon of a second conductivity type in the trench by an epitaxial growth method;
and performing photoetching and etching processes of polysilicon to form the emitting region.
4. A method according to claim 3, characterized in that after the step of forming a base region of the first conductivity type in the base trench, the method further comprises: and performing a rapid thermal annealing process of the emitter region, wherein the annealing temperature is 900-950 ℃ and the annealing time is 15-30 s.
5. The method of claim 1, wherein a planarization operation is performed on an upper surface of the epitaxial layer prior to the steps of growing a dielectric layer over the epitaxial layer and forming a collector, base, and emitter on the dielectric layer.
6. A transistor manufactured by the method of manufacturing a transistor according to any one of claims 1 to 5, characterized in that the transistor comprises:
a substrate of a first conductivity type;
an epitaxial layer of a second conductivity type grown over the substrate;
an emitter region of a second conductivity type, the emitter region being connected to the substrate through the epitaxial layer, the emitter region extending in a non-linear shape in a direction parallel to the substrate surface; and
A base region of the first conductivity type, the base region being connected to the substrate through the epitaxial layer, and the base region being located on one side of the emitter region and extending in a non-linear shape along the emitter region in a direction parallel to the substrate surface;
the transistor also comprises a collector region and a collector contact region, wherein the collector region is positioned at one side of the base region away from the emitter region, and the collector contact region is positioned at one side of the collector region away from the base region;
the transistor further comprises a dielectric layer grown above the epitaxial layer, and a collector electrode, a base electrode and an emitter electrode which are formed on the dielectric layer, wherein the collector electrode penetrates through the dielectric layer to be electrically connected with the collector electrode contact region, and the base electrode penetrates through the dielectric layer to be electrically connected with the base region; the emitter penetrates through the dielectric layer and is electrically connected with the emitter.
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| JPH06333932A (en) * | 1993-05-19 | 1994-12-02 | Rohm Co Ltd | Transistor |
| JPH07302799A (en) * | 1994-04-28 | 1995-11-14 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
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| EP1094523A3 (en) * | 1999-10-21 | 2003-06-11 | Matsushita Electric Industrial Co., Ltd. | Lateral heterojunction bipolar transistor and method of fabricating the same |
| KR20170050652A (en) * | 2015-10-30 | 2017-05-11 | 주식회사 동부하이텍 | Bipolar junction transistor and method of manufacturing the same |
| IT201600108699A1 (en) * | 2016-10-27 | 2018-04-27 | St Microelectronics Srl | SEMICONDUCTOR DEVICE FOR VERTICAL CHANNEL WITH REDUCED TENSION OF SATURATION |
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|---|---|---|---|---|
| US4258380A (en) * | 1978-02-21 | 1981-03-24 | U.S. Philips Corporation | Bipolar transistor having an integrated resistive emitter zone |
| JPH06333932A (en) * | 1993-05-19 | 1994-12-02 | Rohm Co Ltd | Transistor |
| JPH07302799A (en) * | 1994-04-28 | 1995-11-14 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
| CN104518012A (en) * | 2013-09-30 | 2015-04-15 | 天钰科技股份有限公司 | Triode |
| CN208904023U (en) * | 2018-08-15 | 2019-05-24 | 深圳市金誉半导体有限公司 | A kind of transistor |
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