CN109119469B - Transistor and manufacturing method thereof - Google Patents
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- CN109119469B CN109119469B CN201810927537.0A CN201810927537A CN109119469B CN 109119469 B CN109119469 B CN 109119469B CN 201810927537 A CN201810927537 A CN 201810927537A CN 109119469 B CN109119469 B CN 109119469B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 238000002955 isolation Methods 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims description 79
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 230000003321 amplification Effects 0.000 abstract description 9
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 description 22
- 239000000463 material Substances 0.000 description 18
- 238000005530 etching Methods 0.000 description 17
- 238000002513 implantation Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- -1 boron ions Chemical class 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000012808 vapor phase Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
Abstract
The present invention relates to a transistor and a method of manufacturing the same, the transistor comprising: a substrate of a first conductivity type; an epitaxial layer of a second conductivity type grown on the first surface of the substrate; the first conductive type base region penetrates through the epitaxial layer, and one end of the first conductive type base region is connected with the substrate, so that the epitaxial layer forms an emitter region and a collector region; the emitter region comprises a first isolation layer, an emitter layer and a second isolation layer which are sequentially formed on the first surface of the substrate; and forming a collector region in an epitaxial layer region on one side of the base region, which is far away from the emitter region. The transistor provided by the invention has the advantages of simple structure and stable amplification factor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transistor and a manufacturing method thereof.
Background
In the prior art, the base region is formed by adopting an annealing process after an injection process, the junction depth and the junction appearance of the base region are greatly influenced by the annealing process, and the polycrystalline emitter process is formed by injecting a large amount of polycrystalline silicon and then carrying out high-temperature rapid thermal annealing so that impurities are diffused into the base region to form an emitter junction. On the surfaces of the base region and the emitter region, a large number of processes such as implantation, etching, metallization and the like are performed, so that a large number of defects are brought to the surfaces of the base region and the emitter region, and finally, the amplification factor of the device is very unstable.
Disclosure of Invention
In view of the above, the present invention provides a transistor including: a substrate of a first conductivity type; an epitaxial layer of a second conductivity type grown on the first surface of the substrate; the first conductive type base region penetrates through the epitaxial layer, and one end of the first conductive type base region is connected with the substrate; the emitter region is formed in the epitaxial layer region on one side of the base region; the emitter region comprises a first isolation layer, an emitter layer and a second isolation layer which are sequentially formed on the first surface of the substrate; and the collector region is formed in the epitaxial layer region on the other side of the base region.
It can be understood that, by adopting a three-layer epitaxial structure, the emitter layer is positioned between the first isolation layer and the second isolation layer, and the emitter layer is in longitudinal contact with the base region, so that a contact interface between the emitter layer and the base region does not need to undergo process flows such as ion implantation in the following manufacturing process, and the emitter interface is not damaged and is kept good, so that the transistor provided by the invention has a stable current amplification coefficient.
The invention also provides a manufacturing method of the transistor, which comprises the following steps: providing a substrate of a first conductivity type; growing an epitaxial layer with a second conductivity type on the first surface of the substrate, wherein the epitaxial layer comprises a first layer, a second layer and a third layer which are sequentially formed on the first surface of the substrate; forming a base region of a first conductive type in the epitaxial layer region, wherein the base region penetrates through the epitaxial layer and one end of the base region is connected with the substrate, so that the epitaxial layer forms an emitter region, and the emitter region comprises a first isolation layer, an emitter layer and a second isolation layer which are sequentially formed on the first surface of the substrate; and forming a collector region in an epitaxial layer region on one side of the base region, which is far away from the emitter region.
It can be understood that the emitter layer is positioned between the first isolation layer and the second isolation layer by adopting a method of forming three-layer epitaxy, and the emitter layer is in longitudinal contact with the base region, so that a contact interface of the emitter layer and the base region does not need to be subjected to process flows such as ion implantation in the following manufacturing process, and the emitter interface is not damaged and is kept good, so that the transistor provided by the invention has a stable current amplification coefficient.
Drawings
The invention is further illustrated with reference to the following figures and examples.
Fig. 1 is a schematic flow chart of a method of manufacturing a transistor of a first embodiment of the present invention;
FIG. 2 is a cross-sectional structural diagram of a transistor according to a second embodiment of the present invention;
fig. 3 to 7 are schematic structural views of a method of manufacturing a transistor according to a first embodiment of the present invention;
in the figure: 1. a substrate; 2. an epitaxial layer; 21. a first layer; 22. a second layer; 23. a third layer; 3. a base region; 4. an emission region; 41. a first isolation layer; 42. an emitter layer; 43. a second isolation layer; 5. a collector region; 51. a collector contact region; 6. a dielectric layer; 71. a collector electrode; 72. a base electrode; 73. an emitter;
the following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
In order to make the objects, technical solutions and advantageous technical effects of the present invention more clearly and completely apparent, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The first embodiment is as follows:
referring to fig. 1 and fig. 2, a method for fabricating a transistor includes:
step S01: providing a substrate 1 of a first conductivity type;
step S02: growing an epitaxial layer 2 with a second conductivity type on the first surface of the substrate 1, wherein the epitaxial layer 2 comprises a first layer 21, a second layer 22 and a third layer 23 which are sequentially formed on the first surface of the substrate 1;
step S03: forming a first conductive type base region 3 on the epitaxial layer 2, wherein the base region 3 penetrates through the epitaxial layer 2 and one end of the base region is connected with the substrate 1, so that the epitaxial layer 2 forms an emitter region 4; the emitter region 4 comprises an emitter layer 42 formed in the region of the second layer 22, a first spacer layer 41 formed in the region of the first layer 21 and a second spacer layer 43 formed in the region of the third layer 23;
and step S04, forming a collector region 5 in the epitaxial layer 2 region on the side of the base region 3 far away from the emitter region 4.
It can be understood that by adopting a three-layer epitaxy method, the contact interface between the emitter layer 42 and the base region 3 does not need to undergo process flows such as ion implantation in the following manufacturing process, so that the emitter interface is not damaged and remains good, and the transistor provided by the invention has a stable current amplification coefficient; and the transistor provided by the invention obtains better breakdown voltage by arranging the first isolation layer and the second isolation layer.
The method of forming the transistor described above will be described in detail below with reference to the accompanying drawings.
For convenience of the following description, it is specifically noted that: the transistor may be an NPN type or a PNP type, and when the transistor is the NPN type, the first conductivity type is a P type, and the second conductivity type is an N type, and when the transistor is the PNP type, the first conductivity type is the N type, and the second conductivity type is the P type. In other words, the transistor may include the emitter region 4 doped with N, the base region 3 doped with P, the collector region 5 doped with N, the substrate 1 doped with P and the epitaxial layer 2 doped with N, or conversely, the transistor may include the emitter region 4 doped with P, the base region 3 doped with N, the collector region 5 doped with P, the substrate 1 doped with N and the epitaxial layer 2 doped with P. In the following embodiments, the transistor is an NPN type, but the invention is not limited thereto.
Referring to fig. 3, step S01 is performed by providing a substrate 1 of a first conductivity type; specifically, the substrate 1 serves as a carrier of the transistor, and mainly plays a role of supporting. The material of the substrate 1 may be a silicon substrate, a germanium-silicon substrate, or the like, and in this embodiment, the material of the substrate 1 is preferably a silicon substrate, and silicon is the most common, inexpensive, and stable-performance semiconductor material. The first conductivity type is P-type, and in some embodiments of the present invention, the dopant ions of the substrate 1 are boron ions, and in other embodiments, other trivalent ions such as indium and gallium may also be used.
Referring to fig. 4, step S02 is executed: growing an epitaxial layer 2 with a second conductivity type on the first surface of the substrate 1, wherein the epitaxial layer 2 comprises a first layer 21, a second layer 22 and a third layer 23 which are sequentially formed on the first surface of the substrate 1; preferably, the epitaxial layer 2 is formed by homoepitaxy with a simple process, that is, the material of the epitaxial layer 2 is the same as that of the substrate 1, and when the material of the substrate 1 is silicon, the material of the epitaxial layer 2 is also silicon. In other embodiments, the epitaxial layer may also be formed by heteroepitaxy, and the material of the epitaxial layer 2 may also be a semiconductor material such as germanium, selenium, or the like. The epitaxial layer 2 may be formed on the first surface of the substrate 1 by using an epitaxial growth method, the epitaxial layer 2 is generally a single crystal structure, and a doping type of the epitaxial layer 2 is opposite to a doping type of the substrate 1, in this embodiment, the substrate 1 is doped P-type, the epitaxial layer 2 is doped N-type, and in other embodiments, if the substrate 1 is doped N-type, the epitaxial layer 2 is doped P-type. The doping ions of the epitaxial layer 1 may be other pentavalent ions such as phosphorus, arsenic, or antimony, and in this embodiment, the doping ions of the epitaxial layer 2 are specifically phosphorus ions. The second layer 22 has a doping concentration higher than that of the first layer 21 and the third layer 23, and more specifically, the second layer 22 has an ion concentration of 1E15-5E15/cm3The ion concentration of the first layer 21 and the third layer 23 is 5E13-7E13/cm3. More specifically, the epitaxial growth method may be a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, a vacuum evaporation growth method, a high frequency sputtering growth method, a molecular beam epitaxial growth method, or the like, and preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method) is used, which is a process of reacting a gaseous reaction material on a surface of a solid substrate and depositing the reaction material into a solid thin layer or a thin film, and is an epitaxial growth method for a relatively mature transistor. The method comprises mixing silicon with doping elementsAnd spraying the solution on the substrate 21 to sequentially form the first layer 21, the second layer 22 and the third layer 23, wherein after the first layer 21 is formed, the equipment does not need to stop during the process of manufacturing the second layer 22 and the third layer 23, and the content of the doping element in the manufactured second layer 22 and third layer 23 can be changed by only adjusting the amount of the doping element sprayed by the equipment.
Referring to fig. 5, step S03 is executed: forming a first conductive type base region 3 on the epitaxial layer 2, wherein the base region 3 penetrates through the epitaxial layer 2 and has one end connected to the substrate 1, so that the epitaxial layer 2 forms an emitter region 4, the emitter region 4 comprises a first isolation layer 41, an emitter layer 42 and a second isolation layer 43 which are sequentially formed on the first surface of the substrate 1, wherein the emitter layer 42 is formed in the region of the second layer 22, the first isolation layer 41 is formed in the region of the first layer 21, and the second isolation layer 43 is formed in the region of the third layer 23; specifically, one end of the base region 3 may be connected to the substrate 1 in a manner that one end of the base region extends into the substrate 1, or may only contact the first surface of the substrate 1.
Specifically, the forming step of the base region 3 specifically includes: forming a base groove (not shown) in the epitaxial layer 1, wherein the base groove penetrates through the epitaxial layer and has one end extending to be connected with the substrate 1, and forming a base region 3 of a first conductivity type in the base groove by an epitaxial growth method, specifically, the connection mode between one end of the base groove and the substrate 1 may be that one end of the base groove extends into the substrate 1, or may only contact with the first surface of the substrate 1. Specifically, the process of forming the base region trench may be: forming an etching barrier layer (not shown) on the epitaxial layer 1, then forming a photoresist layer (not shown) on the etching barrier layer, then exposing the photoresist layer by using a mask with the base region groove pattern, and then developing to obtain the photoresist layer with the base region groove pattern. And etching the etching barrier layer by using the photoresist layer with the base region groove pattern as a mask and adopting an etching method such as a reactive ion etching method and the like to form a pattern opening (not shown) of the base region groove. Then with toolsAnd removing the epitaxial layer 2 which is not covered by the etching barrier layer by using the etching barrier layer with the base region groove pattern opening as a mask by adopting methods such as wet etching or dry etching, and forming the base region groove in the epitaxial layer 2. The photoresist layer and the etch stop layer may be removed thereafter by chemical cleaning or the like. In the above process, an anti-reflection layer (not shown) may be further formed between the photoresist layer and the etch stopper layer in order to ensure the exposure accuracy. Specifically, the epitaxial growth method is preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), and is consistent with the formation method of the epitaxial layer 2, and the specific method and the beneficial effects thereof are not described in detail. More specifically, the shape of the base region trench is a strip structure, and more specifically, the width of the base region trench is determined according to the width of the subsequent base region 3, and is generally between 0.3 um and 0.8 um. More specifically, the doping concentration of the base region is 2E13-5E13/cm3In the meantime. It can be understood that the width of the base region 3 can be defined by the photolithography process to accurately control the width of the base region 3, and thus, the amplification factor of the transistor can be accurately controlled.
Specifically, the emitter region 4 is an epitaxial layer region on one side of the base region 3, and the emitter region 4 includes an emitter layer 42 formed in the second layer 22 region, a first isolation layer 41 formed in the first layer 21 region, and a second isolation layer 43 formed in the third layer 23 region; since the emitter layer 42, the first isolation layer 41 and the second isolation layer 43 are partial regions of the second layer 23, the first layer 21 and the third layer 23, respectively, it can be deduced that the first isolation layer 41 is formed between the first surface of the emitter layer 42 and the substrate 1, the second isolation layer 43 is formed on the second surface of the emitter layer 42 opposite to the first surface of the emitter layer 42, the first isolation layer 41 and the second isolation layer 43 are doped with N-type phosphorus element, and the ion doping concentration of the emitter layer 42 is 1E15-5E15/cm3The ion doping concentration of the first isolation layer 41 and the second isolation layer 43 is also 5E13-7E13/cm3. More specifically, the first isolation layer 41 and the second isolation layer 43 may be used to isolate and protect the plantThe emitter layer 42, since the first isolation layer 41 and the second isolation layer 42 pull up the resistance of the emitter region 4, the first isolation layer 41 and the second isolation layer 42 can also make the transistor have a higher breakdown voltage. It can be understood that, by forming the emitter region in an epitaxial manner, the ion concentration and thickness of the emitter region can be more accurately controlled compared with an ion implantation manner, and the good performance of the transistor provided by the invention is further ensured.
Referring to fig. 6, step S04 is performed to form collector region 5 in the region of epitaxial layer 2 on the side of base region 3 away from emitter region 4. Specifically, before forming the collector region 5, the method further includes forming a second conductivity type collector contact region 51 in a region of the epitaxial layer 2 on the side away from the base region 3 by first implantation, where a doping concentration of the collector contact region 51 is higher than that of the collector region 5; the collector region is lightly doped, and since the contact between the subsequent electrode and the lightly doped collector region 5 is not good enough, the heavily doped collector contact region 51 is used here instead to improve the contact performance; the forming step of the collector region 5 specifically comprises the steps of performing second injection in the region of the epitaxial layer 2 between the collector contact region 51 and the base region 3 to form the collector region 5; specifically, the collector region 5 and the collector contact region 51 both penetrate through the epitaxial layer 2 and have one end in contact with the first surface of the substrate 1. More specifically, the first implantation and the second implantation have the same ion conductivity type, the first implantation is phosphorus ions with implantation concentration between 8E15-1E16, and the second implantation is phosphorus ions with implantation concentration determined according to the requirement of Breakdown Voltage (BVCBO) of the device. The second implantation is used for reducing the doping concentration of the epitaxial layer 2 between the base region 3 and the collector contact region 51, and the collector region 5 electrically connected with the base region 3 and the collector contact region 51 is formed, so that the transistor can reach the required breakdown voltage, and the collector junction capacitance of the base region-collector region is effectively reduced.
Referring to fig. 7, further, the method for manufacturing the transistor further includes: growing a dielectric layer 6 above the epitaxial layer and forming a collector 71, a base 71 and an emitter 73 on the dielectric layer 6; the collector 71 is electrically connected with the collector contact region 51 through the dielectric layer 6, and the base 71 is electrically connected with the base region 3 through the dielectric layer 6; and electrically connecting the emitter electrode 73 to the emitter electrode layer 42 through the dielectric layer 6 and the second isolation layer 43 in this order. Specifically, the dielectric layer 6 covers the upper surfaces of the base region 3, the emitter region 4, the collector region 5 and the collector contact region 51, a collector contact hole and a base contact hole are formed in the dielectric layer 6, and an emitter contact hole is formed in the dielectric layer 6 and the second isolation layer 43; the collector contact hole and the base contact hole both penetrate through the dielectric layer 6, the emitter contact hole penetrates through the dielectric layer 6 and the second isolation layer 43, the collector 71 is electrically connected with the highly doped collector region 51 through the collector contact hole on the dielectric layer 6, the base 72 is electrically connected with the base region 3 through the base contact hole on the dielectric layer 6, and the emitter 73 is electrically connected with the highly doped emitter layer 42 through the emitter contact hole on the dielectric layer 6. In some embodiments of the present invention, the dielectric layer 6 may be silicon oxide, silicon nitride, silicon oxynitride, doped silicate glass, or a low dielectric constant material, which may be doped silicon carbide, etc., and is formed for the purpose of isolating the device layers. The collector contact hole, the base contact hole and the emitter contact hole are respectively located above the collector contact region 51, the base region 3 and the emitter layer 42, and are formed by conventional processes such as photolithography and etching.
More specifically, after forming the base region of the first conductivity type, the method further includes: the upper surface of the epitaxial layer 2 is subjected to a planarization operation. It should be noted that, in the manufacturing process, in order to completely fill the base region trench and obtain a flat surface, after the base region 3 is formed, a planarization operation is usually performed on the upper surface of the epitaxial layer 2, specifically, a chemical mechanical polishing manner is adopted, and the chemical mechanical polishing is a conventional means for those skilled in the art, and is not described herein again.
It should be noted that the transistor may have a single-sided structure or a double-sided structure, that is, the base region 3, the collector region 5, the collector contact region 51, the collector 71, the base 71, the collector contact hole, and the base contact hole may be formed only on one side of the emitter region, or may be symmetrically formed on two opposite sides of the emitter region 4, that is, the base region 3, the collector region 5, the collector contact region 51, the collector 71, the base 71, the collector contact hole, or the base contact hole may be formed with a first portion located on one side of the emitter region and a second portion formed on the other side of the emitter region 4, respectively.
It can be understood that, in the transistor formed by the above method, the contact interface between the emitter layer 42 and the base region 3 does not need to undergo a process flow such as ion implantation in the following manufacturing process, so that the emitter interface is not damaged and remains good, and the transistor provided by the present invention has a stable amplification factor; by arranging the first isolation layer 41 and the second isolation layer 43, the transistor provided by the invention can obtain better breakdown voltage.
Example two:
referring to fig. 2, a transistor manufactured according to the manufacturing method of the first embodiment includes: a substrate 1 of a first conductivity type; an epitaxial layer 2 of a second conductivity type grown on a first surface of the substrate 1; a first conductive type base region 3 penetrating the epitaxial layer 2 and having one end connected to the substrate 1; an emitter region 4 formed in an epitaxial layer region on one side of the base region, the emitter region 4 including a first spacer layer 41, an emitter layer 42, and a second spacer layer 43 formed in this order on a first surface of the substrate 1; and a collector region 5 formed in the epitaxial layer 2 region on the other side of the base region 3.
It can be understood that by adopting a three-layer epitaxial structure, the contact interface between the emitter layer 42 and the base region 3 does not need to undergo process flows such as high-temperature rapid annealing and ion implantation in the following manufacturing process, so that the emitter interface is not damaged and remains good, and the transistor provided by the invention has a stable amplification factor; and the transistor provided by the invention obtains better breakdown voltage by arranging the first isolation layer 42 and the second isolation layer 43.
Specifically, one end of the base region 3 may be connected to the substrate 1 in a manner that one end of the base region extends into the substrate 1, or may only contact the first surface of the substrate 1.
Further, the substrate 1 serves as a carrier of the transistor, and mainly plays a role of support. The material of the substrate 1 may be a silicon substrate, a germanium-silicon substrate, or the like, and in this embodiment, the material of the substrate 1 is preferably a silicon substrate, and silicon is the most common, inexpensive, and stable-performance semiconductor material. The first conductivity type is P-type, and in some embodiments of the present invention, the dopant ions of the substrate 1 are boron ions, and in other embodiments, other trivalent ions such as indium and gallium may also be used.
Further, the material of the epitaxial layer 2 is the same as that of the substrate, when the material of the substrate 1 is silicon, the material of the epitaxial layer 2 is also silicon, the epitaxial layer 2 may be formed on the first surface of the substrate 1 by using an epitaxial growth method, the epitaxial layer 2 is generally of a single crystal structure, and the doping type of the epitaxial layer 2 is opposite to that of the substrate 1, in this embodiment, the substrate 1 is P-type doped, the epitaxial layer 2 is N-type doped, and in other embodiments, if the substrate 1 is N-type doped, the epitaxial layer 2 is P-type doped. The doping ions of the epitaxial layer 1 may be other pentavalent ions such as phosphorus, arsenic, or antimony, and in this embodiment, the doping ions of the epitaxial layer 2 are specifically phosphorus ions. The second layer 22 has a doping concentration higher than that of the first layer 21 and the third layer 23, and more specifically, the second layer 22 has an ion concentration of 1E15-5E15/cm3The ion concentration of the first layer 21 and the third layer 23 is 5E13-7E13/cm3. More specifically, the epitaxial growth method may be a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, a vacuum evaporation growth method, a high frequency sputtering growth method, a molecular beam epitaxial growth method, or the like, and preferably a chemical vapor deposition method (or called vapor phase epitaxial growth method), a chemical vapor deposition method, or the like is employedThe epitaxial growth method is a process for reacting and depositing a solid thin layer or a thin film on the surface of a solid substrate by using gaseous reaction raw materials, and is a mature epitaxial growth method of a transistor. According to the method, silicon and doping elements are sprayed on the substrate 21 to form the first layer 21, the second layer 22 and the third layer 23 in sequence, after the first layer 21 is formed, equipment does not need to stop in the process of manufacturing the second layer 22 and the third layer 23, and the content of the doping elements in the manufactured second layer 22 and third layer 23 can be changed only by adjusting the amount of the doping elements sprayed by the equipment.
Further, the forming method of the base region 3 comprises the following steps of: forming a base groove (not shown) in the epitaxial layer 1, wherein the base groove penetrates through the epitaxial layer and has one end extending to be connected with the substrate 1, and forming a base region 3 of a first conductivity type in the base groove by an epitaxial growth method, specifically, the connection mode between one end of the base groove and the substrate 1 may be that one end of the base groove extends into the substrate 1, or may only contact with the first surface of the substrate 1. Specifically, the process of forming the base region trench may be: forming an etching barrier layer (not shown) on the epitaxial layer 1, then forming a photoresist layer (not shown) on the etching barrier layer, then exposing the photoresist layer by using a mask with the base region groove pattern, and then developing to obtain the photoresist layer with the base region groove pattern. And etching the etching barrier layer by using the photoresist layer with the base region groove pattern as a mask and adopting an etching method such as a reactive ion etching method and the like to form a pattern opening (not shown) of the base region groove. And then removing the epitaxial layer 2 which is not covered by the etching barrier layer by using the etching barrier layer with the base region groove pattern opening as a mask and adopting methods such as wet etching or dry etching and the like, and forming the base region groove in the epitaxial layer 2. The photoresist layer and the etch stop layer may be removed thereafter by chemical cleaning or the like. In the above process, an anti-reflection layer (not shown) may be further formed between the photoresist layer and the etch stopper layer in order to ensure the exposure accuracy. Specifically, the epitaxial growth method is preferably a chemical vapor deposition method (or vapor phase deposition method)Epitaxial growth method), which is consistent with the formation method of the epitaxial layer 2, and the specific method and beneficial effects thereof are not described in detail. More specifically, the shape of the base region trench is a bar-shaped structure, and more specifically, the width of the base region trench is determined according to the width of the subsequent base region 3, which is generally between 0.3 um and 0.8 um. More specifically, the doping concentration of the base region is 2E13-5E13/cm3In the meantime. It can be understood that the width of the base region 3 can be defined by the photolithography process to accurately control the width of the base region 3, and thus, the amplification factor of the transistor can be accurately controlled.
It should be noted that, in the manufacturing process, in order to completely fill the base trench and obtain a flat surface, a planarization operation is usually performed on the upper surface of the epitaxial layer 2, specifically, a chemical mechanical polishing manner is adopted. Such chemical mechanical polishing is a conventional method for those skilled in the art and will not be described herein.
Further, the emitter region is an epitaxial layer region on one side of the base region 3, and the emitter region 4 includes an emitter layer 42 formed in the second layer 22 region, a first isolation layer 41 formed in the first layer 21 region, and a second isolation layer 43 formed in the third layer 23 region; since the emitter layer 42, the first isolation layer 41 and the second isolation layer 43 are partial regions of the second layer 22, the first layer 21 and the third layer 23, respectively, it can be concluded that the first isolation layer 41 is formed between the first surface of the emitter layer 42 and the substrate 1, the second isolation layer 44 is formed on the second surface of the emitter layer 42 opposite to the first surface of the emitter layer 42, the first isolation layer 41 and the second isolation layer 44 are doped with N-type phosphorus element, and the ion doping concentration of the emitter layer 42 is 1E15-5E15/cm3The ion doping concentration of the first layer 21 and the third layer 23 is also 5E13-7E13/cm3. More specifically, the first isolation layer 41 and the second isolation layer 43 may serve to isolate and protect the emitter layer 42, since the first isolation layer 41 and the second isolation layer 43 pull up the emitter layer 42The resistance of region 4, and thus the first isolation layer 41 and the second isolation layer 43, may also provide the transistor with a higher breakdown voltage.
Further, specifically, the transistor further includes a second conductivity type collector contact region 51 formed by first implantation in a region of the epitaxial layer 2 on the side away from the base region 3, where a doping concentration of the collector contact region 51 is higher than that of the collector region 5; the collector region is lightly doped, and since the contact between the subsequent electrode and the lightly doped collector region 5 is not good enough, the heavily doped collector contact region 51 is used here instead to improve the contact performance; forming the collector region 5 by performing second implantation in the region of the epitaxial layer 2 between the collector contact region 51 and the base region 3 to form the collector region 5; specifically, the collector region 5 and the collector contact region 51 both penetrate through the epitaxial layer 2 and have one end in contact with the first surface of the substrate 1. More specifically, the first implantation and the second implantation have the same ion conductivity type, the first implantation is phosphorus ion, and the implantation concentration is in
8E15-1E16, the second implanted ions are phosphorus ions, and the implantation concentration is determined according to the requirement of the Breakdown Voltage (BVCBO) of the device. The second implantation is used for reducing the doping concentration of the epitaxial layer 2 between the base region 3 and the collector contact region 51, and the collector region 5 electrically connected with the base region 3 and the collector contact region 51 is formed, so that the transistor can reach the required breakdown voltage, and the collector junction capacitance of the base region-collector region is effectively reduced.
Further, the transistor further comprises a dielectric layer 6 growing above the epitaxial layer 2, and a collector 71, a base 71 and an emitter 73 formed on the dielectric layer 6, wherein the collector 71 is electrically connected with the collector contact region 51 through the dielectric layer 6, and the base 71 is electrically connected with the base 3 through the dielectric layer 6; the emitter electrode 73 is electrically connected to the emitter electrode layer 42 through the dielectric layer 6 and the second isolation layer 43 in this order. Specifically, the dielectric layer 6 covers the upper surfaces of the base region 3, the emitter region 4, the collector region 5, and the collector contact region 51, and a collector contact hole (not shown) and a base contact hole (not shown) are formed, and an emitter contact hole (not shown) is formed on the dielectric layer 6 and the second isolation layer 43; the collector contact hole and the base contact hole both penetrate through the dielectric layer 6, the emitter contact hole penetrates through the dielectric layer 6 and the second isolation layer 43, the collector 71 is electrically connected with the highly doped collector region 51 through the collector contact hole on the dielectric layer 6, the base 72 is electrically connected with the base region 3 through the base contact hole on the dielectric layer 6, and the emitter 73 is electrically connected with the highly doped emitter layer 42 through the emitter contact hole on the dielectric layer 6. In some embodiments of the present invention, the dielectric layer 6 may be silicon oxide, silicon nitride, silicon oxynitride, doped silicate glass, or a low dielectric constant material, which may be doped silicon carbide, etc., and is formed for the purpose of isolating the device layers. The collector contact hole, the base contact hole and the emitter contact hole are respectively located above the collector contact region 51, the base region 3 and the emitter layer 42, and are formed by conventional processes such as photolithography and etching.
It should be noted that the transistor may have a single-sided structure or a double-sided structure, that is, the base region 3, the collector region 5, the collector contact region 51, the collector 71, the base 71, the collector contact hole, and the base contact hole may be formed only on one side of the emitter region 4, or may be symmetrically formed on two opposite sides of the emitter region 4, that is, the base region 3, the collector region 5, the collector contact region 51, the collector 71, the base 71, the collector contact hole, or the base contact hole may be formed with a first portion located on one side of the emitter region and a second portion formed on the other side of the emitter region 4, respectively.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A transistor, comprising:
a substrate of a first conductivity type;
an epitaxial layer of a second conductivity type grown on the first surface of the substrate;
the first conductive type base region penetrates through the epitaxial layer, and one end of the first conductive type base region is connected with the substrate;
the emitter region of the second conduction type is formed in the epitaxial layer region on one side of the base region; the emitter region comprises a first isolation layer, an emitter layer and a second isolation layer which are sequentially formed on the first surface of the substrate; and
the collector region of the second conduction type is formed in the epitaxial layer region on the other side of the base region;
the doping concentration of the emitter layer is higher than that of the first isolation layer and the second isolation layer; the transistor also comprises a dielectric layer growing above the epitaxial layer, and a collector, a base and an emitter which are formed on the dielectric layer, wherein the collector penetrates through the dielectric layer and is electrically connected with the collector contact region, and the base penetrates through the dielectric layer and is electrically connected with the base region; the emitter penetrates through the dielectric layer and the second isolation layer in sequence and is electrically connected with the emitter layer.
2. The transistor of claim 1, further comprising a collector contact region of the second conductivity type on a side of the collector region remote from the base region, the collector contact region being doped with a higher concentration than the collector region, the collector contact region being configured to improve contact performance of the collector region.
3. A method for fabricating a transistor, the method comprising:
providing a substrate of a first conductivity type;
growing an epitaxial layer with a second conductivity type on the first surface of the substrate, wherein the epitaxial layer comprises a first layer, a second layer and a third layer which are sequentially formed on the first surface of the substrate;
forming a base region of a first conductive type in the epitaxial layer region, wherein the base region penetrates through the epitaxial layer and one end of the base region is connected with the substrate, so that the epitaxial layer forms an emitter region, and the emitter region comprises a first isolation layer, an emitter layer and a second isolation layer which are sequentially formed on the first surface of the substrate;
forming a collector region of a second conductive type in an epitaxial layer region of one side of the base region, which is far away from the emitter region;
prior to the step of forming the collector region, the method further comprises:
forming a second conductive type collector contact region in a region of the epitaxial layer, which is far away from one side of the base region, through first injection; the doping concentration of the collector contact region is higher than that of the collector region, and the collector contact region is used for improving the contact performance of the collector region;
the step of forming the collector region includes: performing second injection in the epitaxial layer region between the collector contact region and the base region to form a collector region; after forming a collector region of a second conductivity type within the epitaxial layer region, the method further comprises: growing a dielectric layer above the epitaxial layer, forming a collector, a base and an emitter on the dielectric layer, electrically connecting the collector with the collector contact region through the dielectric layer, and electrically connecting the base with the base region through the dielectric layer; and electrically connecting the emitter with the emitter layer sequentially through the dielectric layer and the second isolation layer.
4. The method for manufacturing a transistor according to claim 3, wherein the base region forming step comprises:
forming a base region groove in the epitaxial layer, wherein the base region groove penetrates through the epitaxial layer and one end of the base region groove extends to be connected with the substrate;
and forming a base region of the first conductive type in the base region groove.
5. The method of manufacturing a transistor according to claim 4, wherein after the base region of the first conductivity type is formed, a planarization operation is performed on an upper surface of the epitaxial layer.
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| CN107104041A (en) * | 2016-02-23 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and radio frequency triode of radio frequency triode |
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| CN107104041A (en) * | 2016-02-23 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and radio frequency triode of radio frequency triode |
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