CN111883476A - Method for forming deep trench isolation structure and method for forming semiconductor device - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
The invention provides a method for forming a deep trench isolation structure and a method for forming a semiconductor device, wherein the method for forming the deep trench isolation structure comprises the following steps: executing a first etching process to remove a part of the thickness of the structural layer so as to form at least one isolation groove in the structural layer; executing a second etching process to remove the structural layer with the residual thickness at the bottom of the isolation groove so as to enable the isolation groove to penetrate through the structural layer in the thickness direction; and filling a dielectric layer in the isolation trench to form a deep trench isolation structure. When the second etching process is performed, a byproduct generated during the first etching process may be removed, and thus, contamination of the byproduct may be prevented; furthermore, in the manufacturing method of the semiconductor device, the deep trench isolation structure is formed by adopting the forming method of the deep trench isolation structure provided by the invention, and in the forming method of the semiconductor device, the formed semiconductor device can obtain better electrical connection.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a method for forming a deep trench isolation structure and a method for forming a semiconductor device.
Background
As the integration of the internal components of an integrated circuit is increased, the distance between adjacent components is shortened, and the possibility of electrical interference between adjacent components is increased, therefore, an appropriate isolation structure is required to avoid the mutual interference between the components. Trenches with a depth above 3 μm are commonly referred to as deep trenches. Deep trench isolation structures are widely used in present day semiconductor technology, and have good isolation, so that various high and low voltage devices such as analog, digital, high voltage, and EE can be integrated together without causing interference of EMI (electromagnetic interference). For example, deep trench isolation structures can be used as isolation structures to isolate electronic devices of different operating voltages.
The existing method for forming the deep trench isolation structure generally comprises the following steps: firstly, providing a semiconductor substrate; then, forming a process layer on the semiconductor substrate; and then, etching the process layer to form a deep groove in the process layer, and then filling a dielectric layer in the formed deep groove to form a deep groove isolation structure. However, in the above steps, particularly when the process layer is etched, since the formed deep trench has a certain depth, the etching amount of the process layer is relatively large, during the process of etching the process layer, a large amount of byproducts are formed, so as to block the etching of the deep trench, and the formed byproducts may contaminate the semiconductor substrate in the subsequent process, and may even affect the electrical connection of the semiconductor device (e.g., the connection between the contact structure and the semiconductor substrate).
Disclosure of Invention
The invention aims to provide a method for forming a deep trench isolation structure and a method for forming a semiconductor device, which aim to solve the problems that a plurality of byproducts are generated in the process of forming the deep trench isolation structure, and the electrical connection of the semiconductor device is influenced by the pollution and the byproducts.
In order to solve the above technical problem, the present invention provides a method for forming a deep trench isolation structure, comprising: providing a semiconductor substrate, wherein a structural layer is formed on the semiconductor substrate;
executing a first etching process to remove a part of the thickness of the structural layer so as to form at least one isolation trench in the structural layer;
executing a second etching process to remove the structural layer with the residual thickness at the bottom of the isolation groove so as to enable the isolation groove to penetrate through the structural layer in the thickness direction;
and filling a dielectric layer in the isolation groove to form a deep groove isolation structure, wherein the top surface of the deep groove isolation structure is flush with the top surface of the structural layer.
Optionally, in the method for forming the deep trench isolation structure, the first etching process is dry etching; the etching gas adopted by the first etching process is at least one of chlorine gas, carbon gas, hydrogen gas and fluorine-containing gas, and the etching time is 100-150 s.
Optionally, in the method for forming the deep trench isolation structure, the second etching process is wet etching; wherein the etching solution adopted by the second etching process is an acidic solution or hydrogen peroxide, and the etching time is 110-160 s.
Optionally, in the method for forming the deep trench isolation structure, the method for filling the dielectric layer in the isolation trench includes:
forming a dielectric material layer, wherein the dielectric material layer fills the isolation groove and extends to cover the top surface of the structural layer;
and flattening the dielectric material layer to the top surface of the structural layer to form the dielectric layer.
Optionally, in the method for forming the deep trench isolation structure, a first etching process is performed to remove a portion of the structural layer, so that after at least one isolation trench is formed in the structural layer, the thickness of the structural layer with the remaining thickness at the bottom of the isolation trench is 200 angstroms to 500 angstroms.
Optionally, in the method for forming the deep trench isolation structure, the structure layer includes a first oxide layer, a top silicon layer, a second oxide layer, and a nitride layer, which are stacked in sequence, and the first oxide layer covers the surface of the semiconductor substrate.
Optionally, in the method for forming the deep trench isolation structure, when the first etching process is performed, the nitride layer, the second oxide layer, the top silicon layer, and a part of the first oxide layer are sequentially etched, so as to form the isolation trench in the nitride layer, the second oxide layer, the top silicon layer, and the first oxide layer.
Based on the same inventive concept, the invention also provides a method for forming a semiconductor device, which comprises the following steps: and forming the deep trench isolation structure by adopting the method for forming the deep trench isolation structure.
Optionally, in the method for forming a semiconductor device, after forming the deep trench isolation structure, the method for forming a semiconductor device further includes:
forming an interlayer film layer, wherein the interlayer film layer covers the structural layer and the deep trench isolation structure;
forming a first contact structure in the interlayer film layer and the deep trench isolation structure, wherein the first contact structure penetrates through the interlayer film layer and the deep trench isolation structure in the thickness direction; and the number of the first and second groups,
and forming a second contact structure in the interlayer film layer and the nitride layer of the structural layer, wherein the second contact structure penetrates through the interlayer film layer and the nitride layer in the thickness direction.
Optionally, in the method for forming a semiconductor device, a space exists between the first contact structure and the second contact structure.
In the method for forming the deep trench isolation structure and the method for forming the semiconductor device, a first etching process is performed to remove a part of the structural layer with a thickness so as to form at least one isolation trench in the structural layer, and the structural layer with a large part of the thickness can be removed by the first etching process; then, executing a second etching process to remove the structural layer with the residual thickness at the bottom of the isolation trench so as to enable the isolation trench to penetrate through the structural layer in the thickness direction; by the second etching process, a by-product formed during the first etching process can be removed, and thus, contamination of the by-product can be prevented; furthermore, by-products formed in the first etching process are removed, so that the by-products can be prevented from blocking etching compared with the prior art, and the structural layer with the residual thickness at the bottom of the isolation trench can be removed easily. And filling a dielectric layer in the isolation trench to form a deep trench isolation structure, wherein the top surface of the deep trench isolation structure is flush with the top surface of the structural layer. Furthermore, in the method for forming the semiconductor device, the deep trench isolation structure is formed by adopting the method for forming the deep trench isolation structure provided by the invention, and in the method for forming the semiconductor device, the formed semiconductor device can obtain better electrical connection, such as the connection between the contact structure and the semiconductor substrate.
Drawings
FIG. 1 is a schematic flow chart diagram illustrating a method for forming a deep trench isolation structure according to an embodiment of the present invention;
FIGS. 2-6 are schematic structural diagrams formed in a method for forming a deep trench isolation structure according to an embodiment of the present invention;
fig. 7 to 9 are schematic structural views formed in a method of forming a semiconductor device according to an embodiment of the present invention;
wherein the reference numerals are as follows:
100-a semiconductor substrate; 110-a structural layer; 111-a first oxide layer; 112-top silicon; 113-a second oxide layer; 114-a nitride layer; 120-isolation trenches; 130-a layer of dielectric material; 131-a dielectric layer; 140-an interlayer film layer; 150-a first contact structure; 160-second contact structure.
Detailed Description
The following describes a method for forming a deep trench isolation structure and a method for forming a semiconductor device in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Please refer to fig. 1, which illustrates a method for forming a deep trench isolation structure according to an embodiment of the present invention. As shown in fig. 1, the present invention provides a method for forming a deep trench isolation structure, comprising:
step S1: providing a semiconductor substrate, wherein a structural layer is formed on the semiconductor substrate;
step S2: executing a first etching process to remove a part of the thickness of the structural layer so as to form at least one isolation trench in the structural layer;
step S3: executing a second etching process to remove the structural layer with the residual thickness at the bottom of the isolation groove so as to enable the isolation groove to penetrate through the structural layer in the thickness direction;
step S4: and filling a dielectric layer in the isolation groove to form a deep groove isolation structure, wherein the top surface of the deep groove isolation structure is flush with the top surface of the structural layer.
Next, the above steps will be described in more detail with reference to FIGS. 2 to 6; fig. 2 to 6 are schematic structural diagrams formed in the method for forming a deep trench isolation structure according to the embodiment of the present invention.
First, step S1 is executed: as shown in fig. 2, a semiconductor substrate 100 is provided, wherein a structural layer 110 is formed on the semiconductor substrate 100; the semiconductor substrate 100 may be silicon, silicon-on-insulator (SOI), stacked-silicon-on-insulator (SSOI), or the like. The structure layer 110 includes a first oxide layer 111, a top silicon layer 112, a second oxide layer 113, and a nitride layer 114, which are sequentially stacked, wherein the first oxide layer 111 covers the surface of the semiconductor substrate 100.
Then, execution is at step S2: as shown in fig. 3, a first etching process is performed to remove a portion of the thickness of the structural layer 110, so as to form at least one isolation trench 120 in the structural layer 110, for example, two, three, or four isolation trenches may be formed, which is taken as an example in this embodiment. An active region of the semiconductor substrate 100 is defined between two adjacent isolation trenches 120, and the bottom of the isolation trench 120 exposes the remaining thickness of the structural layer 110. Specifically, when the first etching process is performed, the nitride layer 114, the second oxide layer 113, the top-layer silicon 112, and a part of the first oxide layer 111 are sequentially etched, so as to form the isolation trench 120 in the nitride layer 114, the second oxide layer 113, the top-layer silicon 112, and the first oxide layer 111, and the bottom of the isolation trench 120 is exposed out of the first oxide layer 111 with the remaining thickness. That is, when the first etching process is performed, a portion of the thickness of the structural layer 110 remains at the bottom of the isolation trench 120, and more specifically, a portion of the thickness of the first oxide layer 111 remains at the bottom of the isolation trench 120. The thickness of the structural layer 110 with the remaining thickness at the bottom of the isolation trench 120 is 200 angstroms to 500 angstroms, that is, the thickness of the first oxide layer 111 with the remaining thickness at the bottom of the isolation trench 120 is 200 angstroms to 500 angstroms. Through the first etching process, the structural layer 110 may be removed to a large thickness. Preferably, the first etching process is dry etching; the etching gas adopted by the first etching process is at least one of chlorine gas, carbon gas, hydrogen gas and fluorine-containing gas, and the etching time is 100 s-150 s, for example, 100s, 110s, 120s, 130s or 140 s. If the etching time is too long, byproducts generated during the etching process may be increased, and the first oxide layer 111 with the remaining thickness at the bottom of the isolation trench 120 may be contaminated, and if the etching time is too short, the purpose of removing the structural layer 110 with most thickness may not be achieved, so the etching time preferably used in this embodiment is 100s to 150 s.
More specifically, the method for performing the first etching process includes: first, a patterned photoresist layer is formed on the nitride layer 114, wherein the patterned photoresist layer exposes a portion of the nitride layer 114 to define the location of the isolation trench 120. Then, etching gas containing elements such as carbon, hydrogen, chlorine, and fluorine is used to sequentially etch the nitride layer 114, the second oxide layer 113, the top silicon 112, and a portion of the first oxide layer 111 to form the isolation trench 120 in the nitride layer 114, the second oxide layer 113, the top silicon 112, and the first oxide layer 111, and finally, the patterned photoresist layer is removed.
In particular, the patterned photoresist layer forms a larger amount of polymer in combination with the etching gas and the etching products (e.g., byproducts) during the first etching process, and the amount of polymer generated during the etching of the nitride layer 114 is larger than the amount of byproducts generated during the etching of the second oxide layer 113 and the first oxide layer 111, and correspondingly, the amount of byproducts generated during the etching of the nitride layer 114 is larger than the amount of byproducts generated during the etching of the second oxide layer 113 and the first oxide layer 111. The polymer is attached to the formed trench sidewalls, and the polymer layer typically contains elements such as carbon, fluorine, and chlorine.
The etching gas used in the first etching process may include, for example, monofluoromethane (CH)3F) Difluoromethane (CH)2F2) Or trifluoromethane (CHF)3) One or more of; alternatively, the etching gas used in the first dry etching process may be monofluoromethane (CH)3F) Difluoromethane (CH)2F2) Or trifluoromethane (CHF)3) With tetrafluoromethane (CF)4) A combination of (1); alternatively, the etching gas used in the first etching process may be a combination of tetrafluoromethane (CF4) and other hydrogen-containing gas (e.g., hydrobromic acid, HBr) or chlorine-containing gas. Further, the etching gas of the first etching process may also be a gas with a large atomic number of hydrogen, such as monofluoromethane (CH)3F) And difluoromethane (CH)2F2) So that the amount of polymer formed is greater and more easily adheres to the sidewalls of the isolated trench 120. The resulting polymer may protect the sidewalls of the isolation trench 120 during a subsequent second etch process.
In addition, in other embodiments of the present invention, during the first etching process, the rf power may be continuously and constantly applied, i.e., continuously applied, and byproducts generated during the etching process may be discharged.
Next, step S3 is executed: as shown in fig. 4, a second etching process is performed to remove the remaining thickness of the structural layer 110 at the bottom of the isolation trench 120, so that the isolation trench 120 penetrates through the structural layer 110 in the thickness direction. Preferably, the second etching process is wet etching; the etching solution adopted by the second etching process is an acidic solution or hydrogen peroxide, the acidic solution can be hydrofluoric acid, phosphoric acid, nitric acid, phosphate or acetic acid and combination thereof, and the like, and the etching time is 100-150 s, so that the etching solution can be effectively dissolved with the polymer and the by-products generated in the first etching process and removed.
In addition, the etching solution adopted by the second etching process has a larger etching selectivity ratio for the first oxide layer 111 with the remaining thickness at the bottom of the isolation trench 120, and when the second etching process is performed, the influence on the sidewall (e.g., the structural layer 110) of the isolation trench 120 can be avoided.
Further, since the second etching process is wet etching, which is different from the first etching process, no by-product is formed during the second etching process, and the by-product can be prevented from being generated again, and the polymer and the by-product generated during the first etching process can be removed by the etching solution, thereby preventing the semiconductor substrate 100 from being contaminated. Further, by removing the by-product formed in the first etching process, compared with the prior art, the by-product blocking etching can be avoided, so that the structural layer 110 with the residual thickness at the bottom of the isolation trench can be removed more easily. In addition, after the first etching process is performed and before the second etching process is performed, a cleaning process may be performed on the semiconductor substrate 100 to remove a portion of the by-products generated during the first etching process, and the cleaning process may employ, for example, a dry cleaning and a wet cleaning, in which the semiconductor substrate 100 is first subjected to the dry cleaning, and then subjected to the wet cleaning, so that the by-products generated during the first etching process may be easily and completely removed when the second etching process is performed subsequently.
Next, step S4 is executed: referring to fig. 5 and 6, a dielectric layer 131 is filled in the isolation trench to form a deep trench isolation structure, wherein a top surface of the deep trench isolation structure is flush with a top surface of the structural layer 110. Specifically, as shown in fig. 5, the method for filling the dielectric layer 131 in the isolation trench includes: a dielectric material layer 130 is formed, and the dielectric material layer 130 fills the isolation trench 120 and extends to cover the top surface of the structure layer 110 (or the top surface of the nitride layer 114). The dielectric material layer 130 can be formed by a deposition method, such as chemical vapor deposition, and the dielectric material layer 130 includes an oxide layer, such as silicon oxide. Since the byproducts and polymers in the isolation trench 120 are completely removed by the second etching process, the dielectric material layer 130 is formed to have better contact with the isolation trench 120. In particular, the dielectric material layer 130 has a better contact property with the semiconductor substrate 100 at the bottom of the isolation trench 120, so that after a deep trench isolation structure is formed subsequently, the semiconductor substrate 100 and the deep trench isolation structure have a better contact property, and compared with the prior art, the isolation performance of the deep trench isolation structure can be improved.
Next, as shown in fig. 6, the dielectric material layer 130 is planarized to the top surface of the structural layer 110 to form a dielectric layer 131, that is, the dielectric material layer 130 remaining in the isolation trench 120 constitutes the dielectric layer 131, and the isolation trench 120 and the dielectric layer 131 constitute the deep trench isolation structure. Preferably, a chemical mechanical polishing process may be used to planarize the dielectric material layer 130 to the top surface of the structural layer 110, so as to form a relatively flat surface of the dielectric layer 131.
Based on the same inventive concept, the invention also provides a method for forming a semiconductor device, which comprises the following steps: the deep trench isolation structure is formed by adopting the forming method of the deep trench isolation structure provided by the invention.
Referring to fig. 7 to 9, fig. 7 to 9 are schematic structural diagrams formed in a method of forming a semiconductor device according to an embodiment of the present invention.
As shown in fig. 7, an interlayer film 140 is formed, wherein the interlayer film 140 covers the structural layer 110 and the deep trench isolation structure, and in particular, the interlayer film covers the nitride layer 114 in the structural layer 110. Then, as shown in fig. 8, a first contact structure 150 is formed in the interlayer film layer 140 and the deep trench isolation structure, and the contact structure penetrates through the interlayer film layer 140 and the deep trench isolation structure in the thickness direction; and, as shown in fig. 9, forming a second contact structure 160 in the interlayer film 140 and the nitride layer 114 of the structure layer 110, the second contact structure 160 penetrating the interlayer film 140 and the nitride layer 114 in a thickness direction. Wherein a space exists between the first contact structure 150 and the second contact structure 160.
The interlayer film 140 may be made of silicon oxide, the first contact structure 150 is used for grounding the semiconductor substrate 100, and the second contact structure 160 is used for connecting the top layer silicon 112 to an external circuit, or connecting a semiconductor device to an external circuit. Because the deep trench isolation structure formed by the method for forming the deep trench isolation structure provided by the invention can completely remove byproducts in the etching process, the semiconductor substrate and the deep trench isolation structure can have better contact, and therefore, the first contact structure 150 formed in the interlayer film layer and the deep trench isolation structure has better electrical connectivity compared with the prior art. The forming method of the first contact structure 150 and the second contact structure 160 is the prior art, and is not described herein again.
In summary, in the methods for forming a deep trench isolation structure and a semiconductor device provided in the embodiments of the present invention, a first etching process is performed to remove a portion of the structural layer to form at least one isolation trench in the structural layer, and the structural layer with the remaining thickness is exposed at the bottom of the isolation trench; then, executing a second etching process to remove the structural layer with the residual thickness at the bottom of the isolation trench so as to enable the isolation trench to penetrate through the structural layer in the thickness direction; when the second etching process is performed, a byproduct formed during the first etching process may be removed, and thus, contamination of the byproduct may be prevented; furthermore, by-products formed in the first etching process are removed, so that the by-products can be prevented from blocking etching compared with the prior art, and the structural layer with the residual thickness at the bottom of the isolation trench can be removed easily. Furthermore, in the manufacturing method of the semiconductor device, the deep trench isolation structure is formed by adopting the forming method of the deep trench isolation structure provided by the invention, and in the forming method of the semiconductor device, the formed semiconductor device can obtain better electrical connection, such as the connection between the contact structure and the semiconductor substrate.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for forming a deep trench isolation structure, comprising:
providing a semiconductor substrate, wherein a structural layer is formed on the semiconductor substrate;
executing a first etching process to remove a part of the thickness of the structural layer so as to form at least one isolation trench in the structural layer;
executing a second etching process to remove the structural layer with the residual thickness at the bottom of the isolation groove so as to enable the isolation groove to penetrate through the structural layer in the thickness direction;
and filling a dielectric layer in the isolation groove to form a deep groove isolation structure, wherein the top surface of the deep groove isolation structure is flush with the top surface of the structural layer.
2. The method of forming a deep trench isolation structure of claim 1, wherein the first etching process is a dry etch; the etching gas adopted by the first etching process is at least one of chlorine gas, carbon gas, hydrogen gas and fluorine-containing gas, and the etching time is 100-150 s.
3. The method of forming a deep trench isolation structure of claim 1, wherein the second etch process is a wet etch; the etching solution adopted by the second etching process is an acidic solution, and the etching time is 110-160 s.
4. The method of forming a deep trench isolation structure of claim 1, wherein filling a dielectric layer in the isolation trench comprises:
forming a dielectric material layer, wherein the dielectric material layer fills the isolation groove and extends to cover the top surface of the structural layer;
and flattening the dielectric material layer to the top surface of the structural layer to form the dielectric layer.
5. The method of claim 1, wherein a first etching process is performed to remove a portion of the thickness of the structural layer, such that after at least one isolation trench is formed in the structural layer, the remaining thickness of the structural layer at the bottom of the isolation trench is 200-500 angstroms.
6. The method of forming a deep trench isolation structure of claim 1, wherein the structure layer comprises a first oxide layer, a top silicon layer, a second oxide layer, and a nitride layer stacked in sequence, the first oxide layer covering the surface of the semiconductor substrate.
7. The method of claim 6, wherein the nitride layer, the second oxide layer, the top silicon layer and a portion of the thickness of the first oxide layer are sequentially etched while performing the first etching process to form the isolation trench in the nitride layer, the second oxide layer, the top silicon layer and the first oxide layer.
8. A method of forming a semiconductor device, comprising: the formation method of the deep trench isolation structure as claimed in any one of claims 1 to 7 is adopted to form the deep trench isolation structure.
9. The method of forming a semiconductor device of claim 8, wherein after forming the deep trench isolation structure, the method of forming the semiconductor device further comprises:
forming an interlayer film layer, wherein the interlayer film layer covers the structural layer and the deep trench isolation structure;
forming a first contact structure in the interlayer film layer and the deep trench isolation structure, wherein the first contact structure penetrates through the interlayer film layer and the deep trench isolation structure in the thickness direction; and the number of the first and second groups,
and forming a second contact structure in the interlayer film layer and the nitride layer of the structural layer, wherein the second contact structure penetrates through the interlayer film layer and the nitride layer in the thickness direction.
10. The method of forming a semiconductor device according to claim 9, wherein a space exists between the first contact structure and the second contact structure.
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| CN112786524A (en) * | 2021-01-22 | 2021-05-11 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
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