CN111883034B - Screen detection circuit and display panel - Google Patents
Screen detection circuit and display panel Download PDFInfo
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- CN111883034B CN111883034B CN202010753886.2A CN202010753886A CN111883034B CN 111883034 B CN111883034 B CN 111883034B CN 202010753886 A CN202010753886 A CN 202010753886A CN 111883034 B CN111883034 B CN 111883034B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The embodiment of the invention relates to the technical field of display, and discloses a screen detection circuit, which comprises: the screen signal control branch is used for controlling the lightening of the pixel units in the display area of the array substrate; the first routing part and the second routing part are respectively positioned at two ends of the screen signal control branch; and a third routing portion; one end of each of the first routing part, the second routing part and the third routing part is electrically connected with the screen signal control branch circuit, and the other end of each of the first routing part, the second routing part and the third routing part is used for accessing a level signal, wherein the connecting position of the third routing part and the screen signal control branch circuit is located between the connecting position of the first routing part and the screen signal control branch circuit and the connecting position of the second routing part and the screen signal control branch circuit. The screen detection circuit and the display panel provided by the embodiment can reduce the current difference of different areas of the detected display panel during screen detection, and improve the accuracy of screen detection.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a screen detection circuit and a display panel.
Background
The existing display panel is usually designed with a Cell test (screen detection, or dot screen detection) related circuit, which can detect the defects of pixel units in the display panel before the display module is put into operation, thereby reducing the consumption of the display panel with defects on the display module resources, and further reducing unnecessary production cost.
However, the inventors found that at least the following problems exist in the prior art: the screen signal control branch circuit for carrying out screen detection on the display panel provides level signals through the bonding pads arranged on two sides of the display panel, and the voltage close to the level signal power supply position area is higher than the voltage far away from the level signal power supply position, so that the current difference of different areas of the display panel can be caused during screen detection, and the accuracy of screen detection is influenced.
Disclosure of Invention
The invention aims to provide a screen detection circuit and a display panel, which can reduce the current difference of different areas of the display panel to be detected during screen detection and improve the accuracy of screen detection.
To solve the above technical problem, an embodiment of the present invention provides a screen detection circuit, including: the screen signal control branch circuit is used for controlling the lightening of the pixel units in the display area; the first routing part and the second routing part are respectively positioned at two ends of the screen signal control branch circuit; and a third routing portion; the first routing part, the second routing part and the third routing part have the same routing direction and are different from the extending direction of the screen signal control branch circuit; one end of the first wiring part is electrically connected with the screen signal control branch circuit, and the other end of the first wiring part is used for accessing a first level signal; one end of the second wiring part is electrically connected with the screen signal control branch circuit, and the other end of the second wiring part is used for accessing a second level signal; one end of the third wiring part is electrically connected with the screen signal control branch circuit, and the other end of the third wiring part is used for accessing a third level signal, wherein the connecting position of the third wiring part and the screen signal control branch circuit is positioned between the connecting position of the first wiring part and the screen signal control branch circuit and the connecting position of the second wiring part and the screen signal control branch circuit.
In addition, a first distance is reserved between the connecting position of the first routing part and the screen signal control branch circuit and the connecting position of the third routing part and the screen signal control branch circuit; a second distance is reserved between the connecting position of the second routing part and the screen signal control branch circuit and the connecting position of the third routing part and the screen signal control branch circuit; the ratio of the first distance to the second distance is between 3/7 and 7/3; preferably, the first distance and the second distance are the same.
In addition, the method also comprises the following steps: a connecting portion; the other end of the third routing part is connected with the first routing part and/or the second routing part through the connecting part.
In addition, the other end of the first routing part is electrically connected with a first bonding pad of a non-display area of the array substrate, and the other end of the second routing part is electrically connected with a second bonding pad of the non-display area of the array substrate; the other end of the third wire routing part is also electrically connected with a third bonding pad of the array substrate non-display area; wherein the third pad is located between the first pad and the second pad.
In addition, the other end of the first wire routing part is electrically connected with a first bonding pad of a non-display area of the array substrate, and the other end of the second wire routing part is electrically connected with a second bonding pad of the non-display area of the array substrate; the other end of the third wire routing part is electrically connected with a third bonding pad of the array substrate non-display area, wherein the third bonding pad is positioned between the first bonding pad and the second bonding pad.
Preferably, the other end of the third wire routing part is further electrically connected to a fourth pad of the non-display area of the array substrate; wherein the fourth pad is located between the first pad and the second pad.
In addition, the third routing portion is provided with a plurality of.
In addition, the method also comprises the following steps: a connecting portion; the other ends of the plurality of third routing parts are electrically connected to the first routing parts and/or the second routing parts through the same connecting part.
In addition, the other end of the first wire routing part is electrically connected with a first bonding pad of a non-display area of the array substrate, and the other end of the second wire routing part is electrically connected with a second bonding pad of the non-display area of the array substrate; the other end of at least part of the third routing parts is also electrically connected with a fifth pad of the non-display area of the array substrate, wherein each third routing part in at least part of the third routing parts is correspondingly connected with one fifth pad, and the fifth pads are positioned between the first pads and the second pads.
In addition, the screen signal control branch includes: a plurality of thin film transistors for controlling the lighting of the pixel units; the first, second, and third routing portions all include: a data signal line and a gate signal line.
The embodiment of the invention also provides a display panel which comprises the screen detection circuit.
Compared with the prior art, the embodiment of the invention provides the screen detection circuit, the first wire walking part and the second wire walking part for providing the level signal are arranged at two ends of the screen signal control branch, and the first wire walking part and the second wire walking part input the first level signal and the second level signal to two ends of the screen signal control branch so as to control the lighting of the pixel units in the display area. Because the internal load of the screen signal control branch is large, the voltage close to the two ends of the screen signal control branch is much higher than the voltage at the middle position of the screen signal control branch, and the current difference of different areas of a detected display panel can be caused during screen detection, so that the accuracy of the screen detection is influenced; the present embodiment further includes: the third wire routing part is positioned between the connecting position of the first wire routing part and the screen signal control branch and the connecting position of the second wire routing part and the screen signal control branch, namely, a third level signal is input from the middle part of the screen signal control branch, so that the difference value between the voltage at two ends of the screen signal control branch and the voltage at the middle part of the screen signal control branch can be reduced, the uniformity of the voltages of different areas of the detected display panel during screen detection is improved, the current difference of different areas of the detected display panel during screen detection is reduced, and the accuracy of screen detection is improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a screen detection circuit according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of an internal structure of a screen signal control branch according to a first embodiment of the present invention;
fig. 3 is another internal structure diagram of the screen signal control branch circuit according to the first embodiment of the present invention;
FIG. 4 is another schematic diagram of a screen detecting circuit according to the first embodiment of the present invention;
FIG. 5 is a schematic diagram of a screen detection circuit according to a second embodiment of the present invention;
FIG. 6 is another schematic diagram of a screen detecting circuit according to a second embodiment of the present invention;
FIG. 7 is a schematic diagram of a screen detecting circuit according to a third embodiment of the present invention;
FIG. 8 is another schematic diagram of a screen detecting circuit according to a third embodiment of the present invention;
FIG. 9 is a schematic diagram of another structure of a screen detecting circuit according to a third embodiment of the present invention;
FIG. 10 is a schematic diagram of a screen detecting circuit according to a fourth embodiment of the present invention;
fig. 11 is another configuration diagram of a screen detecting circuit according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
The first embodiment of the present invention relates to a screen detection circuit, and the structural schematic diagram of the screen detection circuit in this embodiment is shown in fig. 1: the method comprises the following steps: the screen signal control branch 10 is positioned in the non-display area 02 of the array substrate, and the screen signal control branch 10 is used for controlling the lightening of the pixel units in the display area 01 of the array substrate; the first wire routing part 11 and the second wire routing part 12 are respectively positioned at two ends of the screen signal control branch 10; a third routing portion 13 is also included. The first routing part 11, the second routing part 12 and the third routing part 13 have the same routing direction and are different from the extending direction of the screen signal control branch 10; one end of the first wire walking part 11 is electrically connected with the screen signal control branch 10, and the other end is used for accessing a first level signal; one end of the second wire walking part 12 is electrically connected to the screen signal control branch 10, and the other end is used for accessing a second level signal.
Specifically, a first wire portion 11 and a second wire portion 12 for providing a level signal are disposed at two ends of the screen signal control branch 10, and the first wire portion 11 and the second wire portion 12 input the first level signal and the second level signal to the two ends of the screen signal control branch 10, so as to control the lighting of the pixel units of the display area 01. Because the load in the screen signal control branch 10 is relatively large, the voltage near the two ends of the screen signal control branch 10 is much higher than the voltage at the middle position of the screen signal control branch 10, which may cause the current difference in different areas of the display panel to be detected during the screen detection, and affect the accuracy of the screen detection.
One end of the third wire part 13 is electrically connected to the screen signal control branch 10, and the other end is used for accessing a third level signal, wherein a connection position of the third wire part 13 and the screen signal control branch 10 is located between a connection position of the first wire part 11 and the screen signal control branch 10 and a connection position of the second wire part 12 and the screen signal control branch 10.
The present embodiment further includes: since the connection position of the third wire portion 13 and the screen signal control branch 10 is located between the connection position of the first wire portion 11 and the screen signal control branch 10 and the connection position of the second wire portion 12 and the screen signal control branch 10, that is, a third level signal is input from the middle part of the screen signal control branch 10, the difference between the voltage at the two ends of the screen signal control branch 10 and the voltage at the middle part of the screen signal control branch 10 can be reduced, the uniformity of the voltage of different areas of the detected display panel during screen detection is improved, the current difference of different areas of the detected display panel during screen detection is reduced, and the accuracy of screen detection is improved. In the prior art, the wiring inside the screen signal control branch 10 is set to be wider, and the switch device is set to be larger so as to reduce the internal load of the screen signal control branch 10, thereby reducing the current difference of different areas of the detected display panel during screen detection, but the frame of the detected display panel is easily wider due to the mode; in the embodiment, the current difference of different areas of the display panel to be detected during screen detection is reduced, and the narrow frame design of the display panel to be detected is facilitated.
It should be noted that, in the present embodiment, a partial structural schematic diagram of the screen signal control branch 10 is shown in fig. 2 or 3, and fig. 2 is a structural schematic diagram of the screen signal control branch for a currently common RGBG pixel arrangement; fig. 3 is a schematic diagram of a screen signal control branch structure for a conventional RGB pixel arrangement structure. The screen signal control branch circuit 10 includes: a plurality of thin film transistors for controlling the pixel units to be lit; the thin film transistor includes: a red pixel switching device T1, a blue pixel switching device T2, and a green pixel switching device T3. The screen signal control branch 10 further includes: a grid connecting wire SW1 for connecting a plurality of T1 grids, a grid connecting wire SW2 for connecting a plurality of T2 grids, and a grid connecting wire SW3 for connecting a plurality of T3 grids; further comprising: the source connecting line Data1 is connected with a plurality of T1 sources, the source connecting line Data2 is connected with a plurality of T2 sources, and the source connecting line Data3 is connected with a plurality of T3 sources. When the screen detection is carried out, level signals are provided for the source connecting lines Data1, data1 and Data3, and the level signals are selectively provided for the SW1, the SW2 and the SW3, so that the display panel to be detected is controlled to display different colors or patterns.
The first routing portion 11, the second routing portion 12, and the third routing portion 13 each include: a data signal line and a gate signal line. That is, the first routing portion 11, the second routing portion 12, and the third routing portion 13 each include: six wires, three data signal lines (red pixel data signal line, blue pixel data signal line, green pixel data signal line), and three gate signal lines (red pixel gate signal line connected to SW1, blue pixel gate signal line connected to SW2, green pixel gate signal line connected to SW 3). The first wire routing part 11, the second wire routing part 12, the third wire routing part 13 and the screen signal control branch 10 are in one-to-one correspondence to ensure normal screen detection. In the drawings of the present embodiment, the 4 traces in the first trace portion 11, the second trace portion 12, and the third trace portion 13 are illustrated for convenience, and should not be limited thereto.
Preferably, a first distance is kept between the connection position of the first wire part 11 and the screen signal control branch 10 and the connection position of the third wire part 13 and the screen signal control branch 10; the connecting position of the second wire walking part 12 and the screen signal control branch 10 and the connecting position of the third wire walking part 13 and the screen signal control branch 10 are separated by a second distance; the ratio of the first distance to the second distance is between 3/7 and 7/3. That is, the third wire portion 13 is substantially connected to the middle portion of the screen signal control branch 10, so that the third level signal is input to the screen signal control branch 10 from the middle portion of the screen signal control branch 10, the voltage at the two ends of the screen signal control branch 10 is substantially the same as the voltage at the middle portion, the difference between the voltage at the two ends of the screen signal control branch 10 and the voltage at the middle portion of the screen signal control branch 10 is further reduced, and the uniformity of the voltages at different areas of the display panel to be detected during the screen detection is improved.
Preferably, the first distance and the second distance are the same. The third wire walking part 13 is connected to the middle position of the screen signal control branch 10, and when the first level signal and the second level signal are the same in magnitude, the position of the maximum voltage drop of the screen signal control branch 10 is approximately at the 1/2 position when the third wire walking part 13 is not arranged; when the third wire routing part 13 is connected to the middle position of the screen signal control branch 10, the position of the maximum voltage drop of the screen signal control branch 10 is approximately at 1/4 position, and the voltage difference value of different parts of the screen signal control branch 10 is further reduced.
Preferably, the screen detecting circuit further includes: a connecting portion 14; the other end of the third wire trace portion 13 is connected to the first wire trace portion 11 and/or the second wire trace portion 12 via a connecting portion 14.
Specifically, the connection portion 14 also includes six wirings, three data signal lines (a red pixel data signal line, a blue pixel data signal line, and a green pixel data signal line), and three gate signal lines (a red pixel gate signal line connected to SW1, a blue pixel gate signal line connected to SW2, and a green pixel gate signal line connected to SW 3). The connecting parts 14 and the connecting lines among the first wire routing parts 11, the second wire routing parts 12 and the third wire routing parts 13 are in one-to-one correspondence so as to ensure the normal operation of screen detection. In the drawings of the present embodiment, the number of the traces of the connection portion 14 is 4 for convenience, and the present embodiment should not be limited thereto.
In one implementation, the other end of the third wire walking part 13 is connected to the first wire walking part 11 through the connecting part 14, and a first level signal accessed by the first wire walking part 11 is shunted to the third wire walking part 13 to provide a third level signal for the third wire walking part 13. At this time, the third level signal is half of the first level signal.
In another implementation manner, the other end of the third routing portion 13 is connected to the second routing portion 12 through the connecting portion 14, and a second level signal accessed by the second routing portion 12 is shunted into the third routing portion 13 to provide a third level signal for the third routing portion 13. At this time, the third level signal is half of the second level signal.
In still another implementation manner, as shown in fig. 1, the other end of the third routing portion 13 is connected to the first routing portion 11 and the second routing portion 12 through a connecting portion 14, and a first level signal accessed by the first routing portion 11 is shunted into the third routing portion 13 to provide a third level signal for the third routing portion 13; the second level signal accessed by the second wire portion 12 is shunted into the third wire portion 13, and a third level signal is provided for the third wire portion 13, and at this time, the third level signal is half of the first level signal and half of the second level signal. In this way, when the first level signal and the second level signal are the same in magnitude, the third level signal is shunted at the middle part of the screen signal control branch 10, and therefore, the magnitude of the current input into the screen signal control branch 10 after the third level signal is shunted is close to the magnitude of the current shunted into the screen signal control branch 10 from the first routing portion 11 and the second routing portion 12, so that the current difference of different areas of the display panel to be detected during screen detection can be further reduced, and the accuracy of screen detection is improved.
Further, as shown in fig. 4, the other end of the first wire portion 11 is electrically connected to the first pad 21 of the non-display area 02 of the array substrate, and the other end of the second wire portion 12 is electrically connected to the second pad 22 of the non-display area 02 of the array substrate; the other end of the third wire portion 13 is also electrically connected to a third pad 23 of the array substrate non-display area 02, wherein the third pad 23 is located between the first pad 21 and the second pad 22.
Specifically, the array substrate includes an FPC pad area 03 located at the non-display area 02. The first pad 21, the second pad 22, and the third pad 23 are provided by pads of the FPC pad region 03. Wherein the first pad 21, the second pad 22, and the third pad 23 each include: data signal pads (red pixel data signal pad, blue pixel data signal pad, green pixel data signal pad), and gate signal pads (red pixel gate signal pad, blue pixel gate signal pad, green pixel gate signal pad). The data signal pad is used for providing a level signal for a data signal line of each pixel unit, and the grid signal pad is used for providing a level signal for a grid signal routing of each pixel unit. The first routing parts 11, the second routing parts 12, the third routing parts 13 and the connecting lines between the first pads 21, the second pads 22 and the third pads 23 are in one-to-one correspondence so as to ensure the normal operation of screen detection. The number of the first pad 21, the second pad 22, and the third pad 23 shown in the figures of the present embodiment is 4 for convenience of illustration only, and should not be limited thereto.
The other end of the first wire part 11 is electrically connected with the first pad 21, and the other end of the second wire part 12 is electrically connected with the second pad 22; the other end of the third wire portion 13 is also connected to a third pad 23, and the third pad 23 is located between the first pad 21 and the second pad 22. The first pad 21, the second pad 22 and the third pad 23 are used for switching in level signals, so as to provide the level signals for the first wire walking part 11, the second wire walking part 12 and the third wire walking part 13 respectively. In this embodiment, the third wire portion 13 is configured to receive not only the first level signal of the first wire portion 11 and/or the second level signal of the second wire portion 12, but also an electrical signal from the third pad 23, and the electrical signal of the third pad 23 can compensate for a current loss after the level signal is shunted in the third wire portion 13.
It should be noted that, in the present embodiment, the screen signal control branch 10 includes traces and a switch device therein, the load is relatively large, and the first trace 11, the second trace 12 and the third trace 13 are pure trace structures, so that the voltage drop caused by the resistances of the first trace 11, the second trace 12 and the third trace 13 can be ignored compared with the voltage drop caused by the load of the screen signal control branch 10, and the present embodiment mainly provides an improvement scheme for the problem of the voltage drop caused by the large load of the screen signal control branch 10.
Compared with the prior art, the embodiment of the invention provides a screen detection circuit, a first wire walking part 11 and a second wire walking part 12 for providing level signals are arranged at two ends of a screen signal control branch 10, and the first wire walking part 11 and the second wire walking part 12 input the first level signal and the second level signal to the two ends of the screen signal control branch 10, so as to control the lighting of pixel units in a display area 01. Because the load in the screen signal control branch 10 is large, the voltage near the two ends of the screen signal control branch 10 is much higher than the voltage at the middle position of the screen signal control branch 10, which may cause the current difference in different areas of the display panel to be detected during the screen detection and affect the accuracy of the screen detection; the present embodiment further includes: since the connection position of the third wire walking part 13 and the screen signal control branch 10 is located between the connection position of the first wire walking part 11 and the screen signal control branch 10 and the connection position of the second wire walking part 12 and the screen signal control branch 10, that is, a third level signal is input from the middle part of the screen signal control branch 10, the difference between the voltage at the two ends of the screen signal control branch 10 and the voltage at the middle part of the screen signal control branch 10 can be reduced, the uniformity of the voltage of different areas of the detected display panel during screen detection is improved, the current difference of different areas of the detected display panel during screen detection is reduced, and the accuracy of screen detection is improved.
A second embodiment of the present invention relates to a screen inspection circuit, and a schematic configuration diagram of the present embodiment is shown in fig. 5, and the second embodiment is substantially the same as the first embodiment except that the other end of the third routing portion 13 is directly electrically connected to the third pad 23 in the present embodiment, and another configuration pattern in which the third routing portion 13 is connected is given.
The other end of the first wire part 11 is electrically connected with a first bonding pad 21 of the array substrate non-display area 02, and the other end of the second wire part 12 is electrically connected with a second bonding pad 22 of the array substrate non-display area 02; the other end of the third wire part 13 is electrically connected with a third bonding pad 23 of the array substrate non-display area 02, and the third bonding pad 23 is positioned between the first bonding pad 21 and the second bonding pad 22; wherein the third pad 23 is located between the first pad 21 and the second pad 22.
Specifically, the array substrate includes an FPC pad area 03 located at the non-display area 02. The first pad 21, the second pad 22, and the third pad 23 are provided by pads of the FPC pad region 03. Wherein, the first pad 21, the second pad 22, and the third pad 23 all include: data signal pads (red pixel data signal pad, blue pixel data signal pad, green pixel data signal pad), and gate signal pads (red pixel gate signal pad, blue pixel gate signal pad, green pixel gate signal pad). The data signal bonding pad is used for providing level signals for data signal lines of all the pixel units, and the grid signal bonding pad is used for providing level signals for grid signal routing of all the pixel units. The first wire routing part 11, the second wire routing part 12, the third wire routing part 13 and the connecting lines between the first pad 21, the second pad 22 and the third pad 23 are in one-to-one correspondence so as to ensure the normal operation of screen detection. The number of the first pad 21, the second pad 22, and the third pad 23 shown in the figures of the present embodiment is 4 for convenience of illustration only, and should not be limited thereto.
In the scheme, the other end of the first wire part 11 is directly and electrically connected with the first bonding pad 21, and the other end of the second wire part 12 is directly and electrically connected with the second bonding pad 22; the other end of the third wire portion 13 is directly electrically connected to the third pad 23. Another design of the third routing portion 13 is given.
Preferably, as shown in fig. 6, the other end of the third wire portion 13 is further electrically connected to a fourth pad 24 of the array substrate non-display area 02, wherein the fourth pad 24 is located between the first pad 21 and the second pad 22.
Specifically, the fourth pad 24 is provided by a pad of the FPC pad region 03, and the fourth pad 24 is located between the first pad 21 and the second pad 22. The fourth pad 24 is used for accessing a level signal to provide the level signal for the third wire portion 13. In the scheme, the other end of the third wire routing part 13 is electrically connected with not only the third pad 23 but also the fourth pad 24, so that when the level signals provided by the first pad 21, the second pad 22, the third pad 23 and the fourth pad 24 are the same in magnitude, the third wire routing part 13 inputs the current of the screen signal control branch 10 after being shunted, and the current is close to the current respectively input into the screen signal control branch 10 by the first wire routing part 11 and the second wire routing part 12, thereby further reducing the current difference of different areas of the detected display panel during screen detection and improving the accuracy of screen detection. Wherein the fourth pad 24 also includes: data signal pads (red pixel data signal pad, blue pixel data signal pad, green pixel data signal pad), and gate signal pads (red pixel gate signal pad, blue pixel gate signal pad, green pixel gate signal pad). The fourth pads 24 are connected with the connection lines of the third wire routing parts 13 in a one-to-one correspondence manner, so as to ensure normal screen detection. The number of the fourth pads 24 shown as 4 in the drawings of the present embodiment is merely for convenience of illustration, and should not be limited thereto.
Preferably, in this scheme, the lengths of the traces from the third pad 23 to the third trace 13 are the same as the lengths of the traces from the fourth pad 24 to the third trace 13, so as to avoid the problem that the magnitudes of the currents input into the third trace 13 by the third pad 23 and the fourth pad 24 are different due to the difference in trace resistances, and further ensure that the magnitudes of the currents input into the third trace 13 by the third pad 23 and the fourth pad 24 are the same.
Compared with the prior art, the screen detection circuit provided by the embodiment of the invention has the advantages that the other end of the third wire routing part 13 is directly electrically connected with the third bonding pad 23, and another structural mode that the third wire routing part 13 is connected is provided.
A third embodiment of the present invention relates to a screen detection circuit, and a schematic configuration diagram of the screen detection circuit in the present embodiment is shown in fig. 7, and the third embodiment is substantially the same as the first embodiment except that a plurality of third routing portions 13 are provided.
The third wire portions 13 are provided in a plurality, the third wire portions 13 can be uniformly connected to the screen signal control branch 10, and level signals are provided for the screen signal control branch 10 from a plurality of parts of the screen signal control branch 10, so that the voltage difference between the parts of the screen signal control branch 10 can be further reduced, and the voltage uniformity of different regions of the detected display panel during screen detection is improved.
Preferably, the screen detection circuit further includes: a connecting portion 14; the other ends of the plurality of third routing portions 13 are electrically connected to the first routing portions 11 and/or the second routing portions 12 through the same connecting portion 14.
Specifically, the first routing portion 11, the second routing portion 12, the third routing portion 13, and the connecting portion 14 each include six routing lines: three data signal lines (a red pixel data signal line, a blue pixel data signal line, a green pixel data signal line) and three gate signal lines (a red pixel gate signal line connected to SW1, a blue pixel gate signal line connected to SW2, a green pixel gate signal line connected to SW 3). The connecting parts 14 and the connecting lines among the first wire routing parts 11, the second wire routing parts 12 and the third wire routing parts 13 are in one-to-one correspondence so as to ensure the normal operation of screen detection. In the drawings of the present embodiment, the number of the traces in the first trace portion 11, the second trace portion 12, the third trace portion 13, and the connection portion 14 is 4 for convenience, and the present embodiment is not limited thereto.
In one implementation, the other ends of the plurality of third routing portions 13 are connected to the first routing portion 11 through the connecting portion 14, and a first level signal accessed by the first routing portion 11 is shunted to the plurality of third routing portions 13, so as to provide a third level signal for the plurality of third routing portions 13.
In another implementation manner, the other ends of the plurality of third wire routing portions 13 are connected to the second wire routing portion 12 through the connecting portion 14, and a second level signal accessed by the second wire routing portion 12 is shunted to the plurality of third wire routing portions 13 to provide a third level signal for the plurality of third wire routing portions 13.
In still another implementation, as shown in fig. 8, the other ends of the plurality of third wire traces 13 are connected to the first wire trace 11 and the second wire trace 12 through a connection portion 14, and a first level signal accessed by the first wire trace 11 is shunted into the plurality of third wire traces 13 to provide a third level signal for the plurality of third wire traces 13; the second level signal accessed by the second wire walking part 12 is shunted into the plurality of third wire walking parts 13, and a third level signal is provided for the plurality of third wire walking parts 13, and at this time, the third level signal is half of the first level signal and half of the second level signal. In the present embodiment, three structural patterns in which the plurality of third routing portions 13 are connected are given.
Further, the other end of the first wire portion 11 is electrically connected to the first pad 21 of the non-display area 02 of the array substrate, and the other end of the second wire portion 12 is electrically connected to the second pad 22 of the non-display area 02 of the array substrate; the other end of at least part of the third routing parts 13 is further connected with a fifth bonding pad 25 of the array substrate non-display area 02, wherein each third routing part 13 in at least part of the third routing parts 13 is correspondingly connected with a fifth bonding pad 25, and the fifth bonding pad 25 is positioned between the first bonding pad 21 and the second bonding pad 22.
Specifically, the first pad 21, the second pad 22, and the plurality of fifth pads 25 are provided by pads of the FPC pad region 03, the other end of the first routing portion 11 is electrically connected to the first pad 21, and the other end of the second routing portion 12 is electrically connected to the second pad 22; the other end of at least part of the third wire routing parts 13 is also electrically connected with a fifth pad 25, wherein each third wire routing part 13 in at least part of the third wire routing parts 13 is correspondingly connected with a fifth pad 25. In this embodiment, at least a part of the third wire portion 13 receives not only the first level signal of the first wire portion 11 and/or the second level signal of the second wire portion 12, but also the level signal from the fifth pad 25, and the level signal of the fifth pad 25 can compensate the current loss after the level signal is shunted in the third wire portion 13. Wherein the fifth pad 25 also includes: data signal pads (red pixel data signal pad, blue pixel data signal pad, green pixel data signal pad), and gate signal pads (red pixel gate signal pad, blue pixel gate signal pad, green pixel gate signal pad). The fifth pads 25 are connected with the connection lines of the third wire routing parts 13 in a one-to-one correspondence manner, so as to ensure normal screen detection. The number of the fifth pads 254 shown as 4 in the drawings of the present embodiment is merely for convenience of illustration, and should not be limited thereto.
Realistically, as shown in fig. 9, the other end of each third wire portion 13 in the plurality of third wire portions 13 is connected with a fifth pad 25, and another structure pattern of the connection of the third wire portions 13 is given.
Compared with the prior art, the embodiment of the invention provides the screen detection circuit, the plurality of third wire routing parts 13 are arranged, the plurality of third wire routing parts 13 can be uniformly connected to the screen signal control branch 10, level signals are provided for the screen signal control branch 10 from a plurality of parts of the screen signal control branch 10, the voltage difference among the parts of the screen signal control branch 10 can be further reduced, and the voltage uniformity of different areas of the detected display panel during screen detection is improved.
A fourth embodiment of the present invention relates to a screen detection circuit, and a schematic configuration diagram of the screen detection circuit in the present embodiment is shown in fig. 10, and the fourth embodiment is substantially the same as the first embodiment except that another realizable solution is given.
The screen signal control branch 10 in the present embodiment includes: the first part 101 and the second part 102 are adjacently arranged in the extending direction of the screen signal control branch 10, one end of the first wire walking part 11 is electrically connected with one end of the first part 101, which is far away from the second part 102, and the other end is used for accessing a first level signal; one end of the second wire walking part 12 is electrically connected with one end of the second part 102 far away from the first part 101, and the other end is used for accessing a second level signal.
The screen detecting circuit further includes: the third wire walking part 13 and the fourth wire walking part 15, one end of the third wire walking part 13 is electrically connected with one end of the first part 101 close to the second part 102, and the other end is used for accessing a third level signal; one end of the fourth wire walking part 15 is electrically connected with one end of the second part 102 close to the first part 101, and the other end is used for accessing a fourth level signal.
Specifically, in the present embodiment, the screen signal control branch 10 is divided into the first portion 101 and the second portion 102 in the extending direction, and the first portion 101 and the second portion 102 are not electrically connected. The first and third routing portions 11, 13 provide level signals for the first part 101 alone and the second and fourth routing portions 12, 15 provide level signals for the second part 102 alone, which gives an implementation solution.
Preferably, as shown in fig. 11, the array substrate includes an FPC pad area 03 located in the non-display area 02, and the first, second, third, and sixth pads 21, 22, 23, and 26 are provided by pads of the FPC pad area 03. The other end of the first wire portion 11 is electrically connected to the first pad 21, the other end of the second wire portion 12 is electrically connected to the second pad 22, the other end of the third wire portion 13 is further connected to the third pad 23, and the other end of the fourth wire portion 15 is electrically connected to the sixth pad 26.
The first pad 21, the second pad 22, the third pad 23 and the sixth pad 26 are used for switching in level signals, so as to provide the level signals for the first wire portion 11, the second wire portion 12, the third wire portion 13 and the fourth wire portion 15, respectively. In the scheme, the first bonding pad 21 and the third bonding pad 23 provide level signals for the first part 101 of the screen signal control branch 10 independently, the second bonding pad 22 and the sixth bonding pad 26 provide level signals for the second part 102 of the screen signal control branch 10 independently, independent power supply of the first part 101 and the second part 102 of the screen signal control branch 10 is achieved, the level signals are provided for the screen signal control branch 10 from multiple parts of the screen signal control branch 10, voltage difference among the parts of the screen signal control branch 10 can be further reduced, and uniformity of voltages of different areas of a detected display panel during screen detection is improved. Wherein, the fourth routing portion 15 includes: six wires, three data signal lines (a red pixel data signal line, a blue pixel data signal line, a green pixel data signal line), and three gate signal lines (a red pixel gate signal line connected to SW1, a blue pixel gate signal line connected to SW2, and a green pixel gate signal line connected to SW 3). The sixth pad 26 includes: data signal pads (red pixel data signal pad, blue pixel data signal pad, green pixel data signal pad), and gate signal pads (red pixel gate signal pad, blue pixel gate signal pad, green pixel gate signal pad). The sixth pads 26 are connected with the connection lines of the fourth wire traces 15 in a one-to-one correspondence manner, so as to ensure normal screen detection. In the drawings of the present embodiment, the number of pads of the sixth pad 26 is shown as 4, and the number of traces of the fourth trace portion 15 is shown as 4 for convenience, which should not be construed as a limitation.
Compared with the prior art, the embodiment of the invention provides the screen detection circuit, the screen signal control branch 10 is divided into the first part 101 and the second part 102 in the extending direction, and the first part 101 and the second part 102 are not electrically connected. The first and third wire routing portions 11, 13 provide level signals to the first portion 101 alone and the second and fourth wire routing portions 12, 15 provide level signals to the second portion 102 alone, giving an implementation.
A fifth embodiment of the present invention relates to a display panel including the screen detection circuit according to any one of the first to fourth embodiments.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (12)
1. A screen detection circuit, comprising:
the screen signal control branch circuit is used for controlling the lightening of the pixel units in the display area of the array substrate;
the first routing part and the second routing part are respectively positioned at two ends of the screen signal control branch circuit; and
a third routing portion;
the first routing part, the second routing part and the third routing part have the same routing direction and are different from the extending direction of the screen signal control branch circuit;
one end of the first wiring part is electrically connected with the screen signal control branch circuit, and the other end of the first wiring part is used for accessing a first level signal;
one end of the second wiring part is electrically connected with the screen signal control branch circuit, and the other end of the second wiring part is used for accessing a second level signal;
one end of the third wiring part is electrically connected with the screen signal control branch, the other end of the third wiring part is used for accessing a third level signal, the third wiring part and the connection position of the screen signal control branch are located between the connection position of the first wiring part and the screen signal control branch and between the connection position of the second wiring part and the screen signal control branch, and the first wiring part, the second wiring part and the third wiring part are all electrically connected with at least one same signal line in the screen signal control branch.
2. The screen detection circuit of claim 1, wherein a first distance is provided between a connection position of the first wire portion and the screen signal control branch and a connection position of the third wire portion and the screen signal control branch;
a second distance is reserved between the connecting position of the second routing part and the screen signal control branch circuit and the connecting position of the third routing part and the screen signal control branch circuit;
the ratio of the first distance to the second distance is between 3/7 and 7/3.
3. The screen detect circuit of claim 2, wherein the first distance and the second distance are the same.
4. The screen detection circuit of claim 1, further comprising: a connecting portion; the other end of the third wire routing part is connected with the first wire routing part and/or the second wire routing part through the connecting part.
5. The screen detection circuit of claim 4, wherein the other end of the first wire portion is electrically connected to a first pad of a non-display area of the array substrate, and the other end of the second wire portion is electrically connected to a second pad of the non-display area of the array substrate;
the other end of the third routing part is also electrically connected with a third bonding pad of the non-display area of the array substrate; wherein the third pad is located between the first pad and the second pad.
6. The screen detection circuit of claim 1, wherein the other end of the first wire portion is electrically connected to a first pad of a non-display area of the array substrate, and the other end of the second wire portion is electrically connected to a second pad of the non-display area of the array substrate; the other end of the third wire routing part is electrically connected with a third bonding pad of the array substrate non-display area; wherein the third pad is located between the first pad and the second pad.
7. The screen detection circuit of claim 6, wherein the other end of the third wire portion is further electrically connected to a fourth pad of the non-display area of the array substrate; wherein the fourth pad is located between the first pad and the second pad.
8. The screen detecting circuit according to claim 1, wherein a plurality of the third wire portions are provided.
9. The screen detection circuit of claim 8, further comprising: a connecting portion; the other ends of the plurality of third wire routing parts are electrically connected to the first wire routing parts and/or the second wire routing parts through the same connecting part.
10. The screen detection circuit according to claim 9, wherein the other end of the first wire portion is electrically connected to a first pad of a non-display region of the array substrate, and the other end of the second wire portion is electrically connected to a second pad of the non-display region of the array substrate;
the other end of at least part of the third routing parts is also electrically connected with a fifth pad of the non-display area of the array substrate, wherein each third routing part in at least part of the third routing parts is correspondingly connected with one fifth pad, and the fifth pads are positioned between the first pads and the second pads.
11. The screen detecting circuit according to claim 1, wherein the screen signal control branch comprises: a plurality of thin film transistors for controlling the pixel units to be lit;
the first, second, and third routing portions all include: a data signal line and a gate signal line.
12. A display panel comprising the screen detecting circuit of any one of the above claims 1 to 11.
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| CN202010753886.2A CN111883034B (en) | 2020-07-30 | 2020-07-30 | Screen detection circuit and display panel |
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| CN202010753886.2A CN111883034B (en) | 2020-07-30 | 2020-07-30 | Screen detection circuit and display panel |
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| CN111883034B true CN111883034B (en) | 2022-10-25 |
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| TW582011B (en) * | 2000-01-06 | 2004-04-01 | Toshiba Corp | Array substrate and method of inspecting the same |
| CN107329298A (en) * | 2017-08-31 | 2017-11-07 | 京东方科技集团股份有限公司 | Lighting test circuit, array base palte and preparation method thereof, display device |
| CN109949729A (en) * | 2019-04-29 | 2019-06-28 | 武汉华星光电半导体显示技术有限公司 | AMOLED panel is at box detection circuit and its method of repair data line |
| CN110286536B (en) * | 2019-06-28 | 2022-04-15 | 京东方科技集团股份有限公司 | Screen detection circuit, array substrate and display panel |
| CN111081750B (en) * | 2019-12-31 | 2022-05-17 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111369895B (en) * | 2020-04-23 | 2022-05-13 | 上海中航光电子有限公司 | Display panel and display device |
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