CN111881636B - RISC-V chip based simulation debugging method and device - Google Patents

RISC-V chip based simulation debugging method and device Download PDF

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CN111881636B
CN111881636B CN202010644008.7A CN202010644008A CN111881636B CN 111881636 B CN111881636 B CN 111881636B CN 202010644008 A CN202010644008 A CN 202010644008A CN 111881636 B CN111881636 B CN 111881636B
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debugged
read
write
state
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CN111881636A (en
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王锐
陆思茗
李建军
莫军
王亚波
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Unicmicro Guangzhou Co ltd
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Abstract

The invention discloses a simulation debugging method and a device based on a RISC-V chip, wherein the simulation debugging method comprises the following steps: initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged; and after the initialization is finished, performing read-write operation on the system memory according to the debugging signal, and judging whether the read-write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion state of the read-write operation. The invention provides a simulation debugging method and device based on a RISC-V chip, which can effectively improve the debugging efficiency and accurately find the incorrect design problem of logic processing in a JTAG module, thereby successfully carrying out IP function verification on later-stage application and being beneficial to accelerating the progress of projects.

Description

RISC-V chip based simulation debugging method and device
Technical Field
The invention relates to the technical field of system chips, in particular to a simulation debugging method and device based on a RISC-V chip.
Background
Currently, in the field of mobile devices, the ARM architecture occupies 90% of the chip market due to its characteristics of small size, low power consumption, high performance, compatibility, and the like. The use of the ARM architecture adopts an authorization mode, and enterprises need to pay an expensive authorization fee to the ARM when designing products based on the ARM architecture, so that a plurality of chip enterprises lose the capability of developing own chip architectures from scratch. RISC-V (reduced instruction set (RISC) principle-based open Instruction Set Architecture (ISA)) developed in recent years is a simple, open-source and free instruction set architecture, has the technical advantages of simplicity, low power consumption, modularization, expandability and the like, and is very suitable for the fields of Internet of things and edge computing. The RISC-V architecture used by chip enterprises can obviously reduce the cost of chip development, get rid of the phenomenon of foreign monopoly and realize the domestic autonomy of the processor kernel. However, because the RISC-V has a short birth time, the related compiler, software development environment, module debugging scheme and the like are still developing, and a debugging tool which can be used by a chip design enterprise when debugging the CPU module of the RISC-V architecture has a certain gap compared with the ARM architecture. Because the ARM architecture JTAG protocol standard is different from RISC-V, no debug solution can be found when the SOC verifies the JTAG module function of the RISC-V architecture kernel.
The existing RISC-V architecture kernel does not have a RISC-V CPU JTAG debugging scheme which can be used, the function of a JTAG module in a CPU can not be simulated and verified on an SOC level, the prior art can only carry out direct debugging through a certain hardware RISC-V JTAG debugger, but the efficiency of the simulation debugging method based on the RISC-V chip is low, when the design of the JTAG module has problems, the hardware can hardly find the design problem, the IP function verification can not be carried out on the later system application, and the project progress is greatly delayed.
Disclosure of Invention
The invention provides a simulation debugging method based on a RISC-V chip, which aims to solve the technical problem of lower debugging efficiency of a JTAG module in the prior art.
The first embodiment of the present invention provides a simulation debugging method based on RISC-V chip, including:
initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged;
and after the initialization is finished, performing read-write operation on the system memory according to the debugging signal, and judging whether the read-write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion state of the read-write operation.
Further, the initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged specifically include:
initializing a system of a chip to be debugged through a simulation environment, and calibrating a high-speed clock of the chip to be debugged to an expected value;
resetting the state of the JTAG module of the chip to be debugged according to the debugging signal, and reading the equipment ID number of the chip to be debugged;
after successfully reading the equipment ID number of the chip to be debugged, carrying out hard reset on the DTM of the JTAG module, and canceling all DMI transmission in the JTAG module; clearing error identification bits in the JTAG module to enable the DTM to execute new transmission; and executing Hart reset and debugging module reset in the JTAG module.
Further, the writing operation is performed on the system memory according to the debugging signal, and whether the read-write operation of the JTAG module of the chip to be debugged is normal is determined by reading the completion state of the writing operation, specifically:
and changing the state of the JTAG state machine according to the debugging signal, correspondingly writing write-in data into a write-in memory address of the system memory by sending a write-in instruction according to the state change of the JTAG state machine, and judging whether the write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion condition of the write-in instruction after the write-in instruction is executed.
Further, by reading the completion status of the write instruction, whether the write operation of the JTAG module of the chip to be debugged is normal is determined, specifically:
reading the completion state of the write-in instruction, and if the completion state is a busy state, continuing waiting;
if the completion state is an error state, judging that the write operation of the JTAG module of the chip to be debugged is abnormal;
and if the completion state is an error-free state, judging that the write operation of the JTAG module of the chip to be debugged is normal.
Further, the performing read-write operation on the system memory according to the debug signal, and determining whether the read-write operation of the JTAG module of the chip to be debugged is normal by reading the completion state of the read-write operation, further includes:
and changing the state of the JTAG state machine according to the debugging signal, reading the write-in data corresponding to the write-in memory address in the system memory through a read instruction according to the state change of the JTAG state machine, and judging whether the read operation of the JTAG module is normal or not through reading the completion condition of the read instruction after the read instruction is executed.
Further, the determining whether the read operation of the JTAG module is normal by reading the completion status of the read instruction includes:
reading the completion state of the reading instruction, and if the completion state is a busy state, continuing waiting;
if the completion state is an error state, judging that the read operation of the JTAG module of the chip to be debugged is abnormal;
and if the completion state is an error-free state, judging that the write operation of the JTAG module of the chip to be debugged is normal.
Further, after the write operation of the JTAG module of the chip to be debugged is judged to be normal, the read data of the read operation is read, and if the read data is consistent with the write data, the read-write debugging of the chip to be debugged is judged to be finished.
Further, the system memory includes one or more of a system register, an SRAM memory area, and an EFLASH memory.
Further, the debug signal includes one or more of a TCK signal, a TMS signal, a TDO signal, and a TDI signal.
Another embodiment of the present invention provides a simulation debugging apparatus based on RISC-V chip, including:
the initialization module is used for initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged;
and the judging module is used for performing read-write operation on the system memory according to the debugging signal after the initialization is completed, and judging whether the read-write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion state of the read-write operation.
The invention provides a simulation debugging method and a device based on RISC-V chip, which ensure the stability of a system clock by initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged, ensure the normal and stable operation of the system and be beneficial to improving the debugging reliability of the JTAG module; and after the initialization of the chip to be debugged is completed, the embodiment of the invention carries out read-write operation on the system memory according to the debugging signal, judges whether the read-write operation of the chip to be debugged is normal or not by reading the completion state of the read-write operation, and can accurately find the design problem of incorrect logic processing in the JTAG module, thereby effectively improving the debugging efficiency, smoothly carrying out IP function verification on later application and being beneficial to accelerating the progress of projects.
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FIG. 1 is a schematic flowchart of a simulation debugging method based on RISC-V chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an initialization process of a chip to be debugged according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a JTAG module write operation flow provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a read operation flow of a JTAG module according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an emulation debugging apparatus based on RISC-V chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1-4, a first embodiment of the present invention provides a simulation debugging method based on RISC-V chip shown in fig. 1, including:
s1, initializing a system of the chip to be debugged and a JTAG module in the chip to be debugged;
and S2, after the initialization is completed, performing read-write operation on the system memory according to the debugging signal, and judging whether the read-write operation of the JTAG module of the chip to be debugged is normal or not according to the completion state of the read-write operation.
The embodiment of the invention initializes the system of the chip to be debugged and the JTAG module in the chip to be debugged, ensures the stability of the system clock, enables the system to normally and stably run, and is beneficial to improving the debugging reliability of the JTAG module; and after the initialization of the chip to be debugged is completed, the embodiment of the invention carries out read-write operation on the system memory according to the debugging signal, judges whether the read-write operation of the chip to be debugged is normal or not by reading the completion state of the read-write operation, and can accurately find the design problem of incorrect logic processing, thereby effectively improving the debugging efficiency, smoothly carrying out IP function verification on later application and being beneficial to accelerating the progress of a project.
As a specific implementation manner of the embodiment of the present invention, initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged specifically includes:
initializing a system of a chip to be debugged through a simulation environment, and calibrating a high-speed clock of the chip to be debugged to an expected value;
referring to fig. 2, an initialization process of a chip to be debugged according to an embodiment of the present invention is schematically illustrated. It should be noted that, after the system of the chip to be debugged is initialized in the simulation environment, the high-speed clock of the chip to be debugged is calibrated to reach the expected value, so that the stability of the system clock can be effectively ensured, the system can normally operate, and the reliability of debugging is improved.
Resetting the state of a JTAG module of the chip to be debugged according to the debugging signal, and reading the equipment ID number of the chip to be debugged;
after the initialization of the system is completed, in order to verify whether the processing logic part of the IDCODE instruction by the JTAG module of the chip to be debugged is correct, the embodiment of the present invention is implemented by reading and verifying the device ID number of the chip to be debugged, specifically: according to the requirement that the RISC-V JTAG clock is required to be 12 times smaller than the system clock, frequency division is carried out on the system clock, and a TCK signal is output to a JTAG module of a chip to be debugged; resetting the JTAG module state of a chip to be debugged, pulling up a TMS signal and maintaining for a period of time, and enabling the JTAG module to enter a Test _ Logic _ Reset state according to the description of the JTAG protocol state machine principle; and continuously operating the TMS signal to enable the JTAG state to sequentially enter a Run _ Test/Idle- > Select DR _ Scan- > Select IR _ Scan- > Capture IR- > Shift IR state, and sending an IDCODE instruction by using the TDI signal to read the equipment ID number of the chip to be debugged. Based on the above technical solution, in order to validate the transmitted IDCODE instruction, the TMS signal needs to be continuously operated, so that the JTAG state sequentially enters the Exit1 IR — > Pause IR — > Exit2 IR — > Update IR — > Run _ Test/Idle state to complete one scan operation. Because the JTAG module outputs the equipment ID number in the next Capture _ DR state after receiving the IDCODE instruction, the TMS signal is continuously operated, so that the JTAG module sequentially enters a Run _ Test/Idle — > Select DR _ Scan — > Capture DR — > Shift DR state, and the equipment ID number is read by using the TDO signal. And after reading, operating the TMS signal, returning to a Run _ Test/Idle state, and waiting for the next operation. When the read device ID number is verified to be correct, the processing logic of the JTAG module for the IDCODE instruction is correct.
After successfully reading the equipment ID number of the chip to be debugged, carrying out hard reset on the DTM of the JTAG module, and canceling all DMI transmission in the JTAG module; clearing error identification bits in the JTAG module to enable the DTM to execute new transmission; and executing Hart reset in the JTAG module and debugging module reset. And after the reset operation is completed, enabling the DM module, reading the information of the register in the JTAG module, suspending Hart and starting JTAG debugging.
In the embodiment of the invention, after the device ID number of the chip to be debugged is successfully read, part of the functional modules of the JTAG module are initialized, which is favorable for improving the accuracy of the read-write debugging of the chip to be debugged.
Optionally, the initialization of the partial function module of the JTAG module needs to be completed by performing write operation on the DTMCS register and the DMI _ ACCESS register, and the principle is the same as reading the device ID number of the chip to be debugged, specifically: after bringing the JTAG module into the Shift IR state, a DTMCS command is sent using the TDI signal, and in the next Shift DR state, the TDI signal sends the contents to be written into the register, and the JTAG module validates the write operation after the status changes by Exit1 DR- > Pause DR- > Exit2 DR- > Update DR. It should be noted that the operation of the DMI _ ACCESS register is similar, but since the DMI _ ACCESS register has a plurality of registers, in the Shift DR state, the register address, the read/write direction, and the content to be written or read need to be transmitted to the JTAG module through the TDI signal.
As a specific implementation manner of the embodiment of the present invention, a system memory is subjected to a write operation according to a debug signal, and whether a read-write operation of a JTAG module of a chip to be debugged is normal is determined by reading a completion state of the write operation, which specifically includes:
and changing the state of the JTAG state machine according to the debugging signal, correspondingly writing the write-in data into a write-in memory address of a system memory by sending a write-in instruction according to the state change of the JTAG state machine, and judging whether the write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion condition of the write-in instruction after the write-in instruction is executed.
In the embodiment of the invention, the system memory is read through the JTAG module to verify whether the JTAG module functional logic of the chip to be debugged is correct. Wherein the system memory includes one or more of a system register, an SRAM memory area, and an EFLASH memory. Optionally, in the embodiment of the present invention, the operation of reading and writing the SRAM memory area is taken as an example, to verify whether the JTAG module function logic of the chip to be debugged is correct.
Please refer to fig. 3, which is a schematic diagram illustrating a write operation flow of a JTAG module according to an embodiment of the present invention. As a specific embodiment, the JTAG module debug writes the memory region with the memory address 0x20000024 to the data 0x 12345678: firstly, operating a TMS signal to enable a JTAG state to enter a Run _ Test/Idle- > Select DR _ Scan- > Select IR _ Scan- > Capture IR- > Shift IR state in sequence, and sending a DMI _ ACCESS instruction through a TDI signal to enable the operation of a DM (debug Module) register; continuing to operate the TMS signal, enabling the JTAG state to enter an Exit1 IR- (Pause IR) -Exit 2 IR- (Update IR) -Run _ Test/Idle- (Select DR _ Scan) -Capture DR- (Shift DR) -state in sequence, and putting the written address information into a DATA1 register in a DM register, namely writing 41-bit DATA, wherein the written direction information comprises 2-bit writing direction information, 7-bit address value is the address of a DATA1 register, and the 32-bit DATA is 0x 20000024; and continuously entering a next shift _ DR state, enabling the last written instruction to take effect and starting to write the next instruction. After the above operation is completed, the DATA0 register in the DM register needs to be written with the value expected to be written into the memory: sending 41bit DATA via TDI signals, including op write direction, DATA0 register address and DATA 0x 12345678; operating the instruction register of the DM, telling the JTAG module to write the DATA stored to DATA0 to the address written within DATA 1: continuing to enter the next shift _ DR state, sending 41bit data through TDI signals, waiting for a period of time after executing the instruction, completing the memory writing operation, or reading the content of the DM register ABSTRACTCS to obtain the completion state of the current instruction, and if the instruction is in a busy state, continuing to wait; if the status is error-free, the write operation is finished; and if the completion state is an error state, judging that the write operation of the JTAG module of the chip to be debugged is wrong.
As a specific implementation manner of the embodiment of the present invention, performing read-write operation on a system memory according to a debug signal, and determining whether read-write operation of a JTAG module of a chip to be debugged is normal by reading a completion state of the read-write operation, further includes:
and changing the state of the JTAG state machine according to the debugging signal, reading write-in data corresponding to the write-in memory address in the system memory through the read instruction according to the state change of the JTAG state machine, and judging whether the read operation of the JTAG module is normal or not through the completion condition of the read instruction after the read instruction is executed.
Please refer to fig. 4, which is a schematic diagram of a read operation flow of a JTAG module according to an embodiment of the present invention. As a specific embodiment, the JTAG module debug is similar to the write operation for the read memory address 0x 20000024: firstly, operating a TMS signal to enable a JTAG state to enter a Run _ Test/Idle- > Select DR _ Scan- > Select IR _ Scan- > Capture IR- > Shift IR state in sequence, and transmitting a DMI _ ACCESS instruction through a TDI signal to enable the operation of a DM register; continuing to operate the TMS signal, and enabling the JTAG state to sequentially enter an Exit1 IR-Pause IR-Exit 2 IR-Update IR-Run-Test/Idle-Select DR-Scan-Capture DR-Shift DR state; in order to put the address information to be written into the DATA1 register in the DM (debug Module) register, 41-bit DATA is written, wherein the op including information such as the read-write direction of 2 bits is the write direction, the address value of 7 bits is the address of the DATA1 register, and the DATA of 32 bits is 0x 20000024; operating the instruction register of the DM, telling the JTAG module to read the contents of the address written in DATA 1: continuing to enter the next shift _ DR state, sending 41bit data through TDI signals, waiting for a period of time after the instruction is executed, so that the memory reading operation is completed, or reading the content of the DM register ABSTRACTCS to obtain the completion state of the current instruction, and if the instruction is in a busy state, continuing to wait; if the status is error-free, the read operation is completed.
As a specific implementation manner of the embodiment of the present invention, after the write operation of the JTAG module of the chip to be debugged is determined to be normal, read data of the read operation is read, and if the read data is consistent with the write data, it is determined that the read-write debugging of the chip to be debugged is completed.
In the embodiment of the invention, after the read operation is completed, the read DATA is obtained by reading the DM register DATA0, the 41-bit DATA including the op as the read direction, the DATA0 register address and the 32-bit DATA is written, after entering the next Shift _ DR state, the 41-bit DATA is read and the required content is extracted, if the read DATA is consistent with the write DATA by 0x12345678, the read-write debugging of the JTAG module is successful.
As a specific implementation of the embodiment of the present invention, the debug signal includes one or more of a TCK signal, a TMS signal, a TDO signal, and a TDI signal.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention initializes the system of the chip to be debugged and the JTAG module in the chip to be debugged, ensures the stability of the system clock, enables the system to normally and stably run, and is beneficial to improving the debugging reliability of the JTAG module; after the initialization of the chip to be debugged is completed, the embodiment of the invention carries out read-write operation on a plurality of system memories according to debugging signals, wherein the system memories comprise a system register, an SRAM memory area and an EFLASH memory area; whether the read-write operation of the chip to be debugged is normal or not is judged by reading the completion state of the read-write operation, and the design problem of incorrect logic processing can be accurately found, so that the debugging efficiency can be effectively improved, IP function verification can be smoothly carried out on later application, and the progress of a project can be accelerated.
Referring to fig. 5, a second embodiment of the present invention provides an emulation debugging apparatus based on RISC-V chip as shown in fig. 5, including:
the initialization module 10 is used for initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged;
the judging module 20 is configured to perform read-write operation on the system memory according to the debug signal after the initialization is completed, and judge whether the read-write operation of the JTAG module of the chip to be debugged is normal by reading the completion state of the read-write operation.
In the embodiment of the invention, the initialization module 10 initializes the system of the chip to be debugged and the JTAG module in the chip to be debugged, thereby ensuring the stability of the system clock, enabling the system to normally and stably run and being beneficial to improving the debugging reliability of the JTAG module; after the initialization of the chip to be debugged is completed, the judging module 20 of the embodiment of the invention performs read-write operation on the system memory according to the debugging signal, judges whether the read-write operation of the chip to be debugged is normal or not by reading the completion state of the read-write operation, and can accurately find the design problem with incorrect logic processing, thereby effectively improving the debugging efficiency, smoothly performing IP function verification on later-stage application, and being beneficial to accelerating the progress of a project.
As a specific implementation manner of the embodiment of the present invention, the initialization module 10 is specifically configured to:
initializing a system of a chip to be debugged through a simulation environment, and calibrating a high-speed clock of the chip to be debugged to an expected value;
referring to fig. 2, an initialization process of a chip to be debugged according to an embodiment of the present invention is schematically illustrated. It should be noted that, after the initialization of the system of the chip to be debugged is completed through the simulation environment, the initialization module 10 calibrates the high-speed clock of the chip to be debugged to reach an expected value, and can effectively ensure the stability of the system clock, so that the system can normally operate, and the reliability of the debugging is improved.
Resetting the state of a JTAG module of the chip to be debugged according to the debugging signal, and reading the equipment ID number of the chip to be debugged;
after the system is initialized, in order to verify whether the processing logic part of the IDCODE instruction by the JTAG module of the chip to be debugged is correct, the initialization module 10 in the embodiment of the present invention is implemented by reading and verifying the device ID number of the chip to be debugged, specifically: according to the requirement that the RISC-V JTAG clock is required to be 12 times smaller than the system clock, frequency division is carried out on the system clock, and a TCK signal is output to a JTAG module of a chip to be debugged; resetting the JTAG module state of a chip to be debugged, pulling up a TMS signal and maintaining for a period of time, and enabling the JTAG module to enter a Test _ Logic _ Reset state according to the description of the JTAG protocol state machine principle; and continuously operating the TMS signal to enable the JTAG state to sequentially enter a Run _ Test/Idle- > Select DR _ Scan- > Select IR _ Scan- > Capture IR- > Shift IR state, and sending an IDCODE instruction by using the TDI signal to read the equipment ID number of the chip to be debugged. Based on the above technical solution, in order to validate the transmitted IDCODE instruction, the TMS signal needs to be continuously operated, so that the JTAG state sequentially enters the Exit1 IR — > Pause IR — > Exit2 IR — > Update IR — > Run _ Test/Idle state to complete one scan operation. Because the JTAG module outputs the equipment ID number in the next Capture _ DR state after receiving the IDCODE instruction, the TMS signal is continuously operated, so that the JTAG module sequentially enters a Run _ Test/Idle — > Select DR _ Scan — > Capture DR — > Shift DR state, and the equipment ID number is read by using the TDO signal. And after reading, operating the TMS signal, returning to a Run _ Test/Idle state, and waiting for the next operation. When the read device ID number is verified to be correct, the processing logic of the JTAG module for the IDCODE instruction is correct.
After successfully reading the equipment ID number of the chip to be debugged, carrying out hard reset on the DTM of the JTAG module, and canceling all DMI transmission in the JTAG module; clearing error identification bits in the JTAG module to enable the DTM to execute new transmission; and executing Hart reset in the JTAG module and debugging module reset. And after the reset operation is completed, enabling the DM module, reading the information of the register in the JTAG module, suspending Hart and starting JTAG debugging.
In the embodiment of the present invention, the initialization module 10 initializes part of the function modules of the JTAG module after successfully reading the device ID number of the chip to be debugged, which is beneficial to improving the accuracy of read-write debugging of the chip to be debugged.
Optionally, the initialization of the partial function module of the JTAG module needs to be completed by performing write operation on the DTMCS register and the DMI _ ACCESS register, and the principle is the same as reading the device ID number of the chip to be debugged, specifically: after bringing the JTAG module into the Shift IR state, a DTMCS command is sent using the TDI signal, and in the next Shift DR state, the TDI signal sends the contents to be written into the register, and the JTAG module validates the write operation after the status changes by Exit1 DR- > Pause DR- > Exit2 DR- > Update DR. It should be noted that the operation of the DMI _ ACCESS register is similar, but since the DMI _ ACCESS register has a plurality of registers, in the Shift DR state, the register address, the read/write direction, and the content to be written or read need to be transmitted to the JTAG module through the TDI signal.
As a specific implementation manner of the embodiment of the present invention, the determining module 20 specifically includes:
and changing the state of the JTAG state machine according to the debugging signal, correspondingly writing the write-in data into a write-in memory address of a system memory by sending a write-in instruction according to the state change of the JTAG state machine, and judging whether the write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion condition of the write-in instruction after the write-in instruction is executed.
In the embodiment of the present invention, the determining module 20 reads the system memory through the JTAG module to verify whether the JTAG module function logic of the chip to be debugged is correct. Wherein the system memory includes one or more of a system register, an SRAM memory area, and an EFLASH memory. Optionally, in the embodiment of the present invention, the operation of reading and writing the SRAM memory area is taken as an example, to verify whether the JTAG module function logic of the chip to be debugged is correct.
Please refer to fig. 3, which is a schematic diagram illustrating a write operation flow of a JTAG module according to an embodiment of the present invention. As a specific embodiment, the JTAG module debug writes the memory region with the memory address 0x20000024 to the data 0x 12345678: firstly, operating a TMS signal to enable a JTAG state to enter a Run _ Test/Idle- > Select DR _ Scan- > Select IR _ Scan- > Capture IR- > Shift IR state in sequence, and sending a DMI _ ACCESS instruction through a TDI signal to enable the operation of a DM (debug Module) register; continuing to operate the TMS signal, enabling the JTAG state to enter an Exit1 IR- (Pause IR) -Exit 2 IR- (Update IR) -Run _ Test/Idle- (Select DR _ Scan) -Capture DR- (Shift DR) -state in sequence, and putting the written address information into a DATA1 register in a DM register, namely writing 41-bit DATA, wherein the written direction information comprises 2-bit writing direction information, 7-bit address value is the address of a DATA1 register, and the 32-bit DATA is 0x 20000024; and continuously entering a next shift _ DR state, enabling the last written instruction to take effect and starting to write the next instruction. After the above operation is completed, the DATA0 register in the DM register needs to be written with the value expected to be written into the memory: sending 41bit DATA via TDI signals, including op write direction, DATA0 register address and DATA 0x 12345678; operating the instruction register of the DM, telling the JTAG module to write the DATA stored to DATA0 to the address written within DATA 1: continuing to enter the next shift _ DR state, sending 41bit data through TDI signals, waiting for a period of time after executing the instruction, completing the memory writing operation, or reading the content of the DM register ABSTRACTCS to obtain the completion state of the current instruction, and if the instruction is in a busy state, continuing to wait; if the status is error-free, the write operation is finished; and if the completion state is an error state, judging that the write operation of the JTAG module of the chip to be debugged is wrong.
As a specific implementation manner of the embodiment of the present invention, the determining module 20 is further configured to:
and changing the state of the JTAG state machine according to the debugging signal, reading write-in data corresponding to the write-in memory address in the system memory through the read instruction according to the state change of the JTAG state machine, and judging whether the read operation of the JTAG module is normal or not through the completion condition of the read instruction after the read instruction is executed.
Please refer to fig. 4, which is a schematic diagram of a read operation flow of a JTAG module according to an embodiment of the present invention. As a specific embodiment, the JTAG module debug is similar to the write operation for the read memory address 0x 20000024: firstly, operating a TMS signal to enable a JTAG state to enter a Run _ Test/Idle- > Select DR _ Scan- > Select IR _ Scan- > Capture IR- > Shift IR state in sequence, and transmitting a DMI _ ACCESS instruction through a TDI signal to enable the operation of a DM register; continuing to operate the TMS signal, and enabling the JTAG state to sequentially enter an Exit1 IR-Pause IR-Exit 2 IR-Update IR-Run-Test/Idle-Select DR-Scan-Capture DR-Shift DR state; in order to put the address information to be written into the DATA1 register in the DM (debug Module) register, 41-bit DATA is written, wherein the op including information such as the read-write direction of 2 bits is the write direction, the address value of 7 bits is the address of the DATA1 register, and the DATA of 32 bits is 0x 20000024; operating the instruction register of the DM, telling the JTAG module to read the contents of the address written in DATA 1: continuing to enter the next shift _ DR state, sending 41bit data through TDI signals, waiting for a period of time after the instruction is executed, so that the memory reading operation is completed, or reading the content of the DM register ABSTRACTCS to obtain the completion state of the current instruction, and if the instruction is in a busy state, continuing to wait; if the status is error-free, the read operation is completed.
As a specific implementation manner of the embodiment of the present invention, after the write operation of the JTAG module of the chip to be debugged is determined to be normal, read data of the read operation is read, and if the read data is consistent with the write data, it is determined that the read-write debugging of the chip to be debugged is completed.
In the embodiment of the invention, after the read operation is completed, the read DATA is obtained by reading the DM register DATA0, the 41-bit DATA including the op as the read direction, the DATA0 register address and the 32-bit DATA is written, after entering the next Shift _ DR state, the 41-bit DATA is read and the required content is extracted, if the read DATA is consistent with the write DATA by 0x12345678, the read-write debugging of the JTAG module is successful.
As a specific implementation of the embodiment of the present invention, the debug signal includes one or more of a TCK signal, a TMS signal, a TDO signal, and a TDI signal.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the system of the chip to be debugged and the JTAG module in the chip to be debugged are initialized by the initialization module, so that the stability of a system clock is ensured, the system can normally and stably run, and the reliability of debugging the JTAG module is improved; after the initialization of the chip to be debugged is completed, the determining module 20 of the embodiment of the present invention performs read-write operations on a plurality of system memories including a system register, an SRAM memory area and an EFLASH memory area according to the debugging signal; whether the read-write operation of the chip to be debugged is normal or not is judged by reading the completion state of the read-write operation, and the design problem of incorrect logic processing can be accurately found, so that the debugging efficiency can be effectively improved, IP function verification can be smoothly carried out on later application, and the progress of a project can be accelerated.
The foregoing is a preferred embodiment of the present invention, and it should be noted that it would be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the principles of the invention, and such modifications and enhancements are also considered to be within the scope of the invention.

Claims (9)

1. A simulation debugging method based on RISC-V chip is characterized by comprising the following steps:
initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged;
after the initialization is completed, performing read-write operation on a system memory according to a debugging signal, and judging whether the read-write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion state of the read-write operation, specifically: and changing the state of the JTAG state machine according to the debugging signal, correspondingly writing write-in data into a write-in memory address of the system memory by sending a write-in instruction according to the state change of the JTAG state machine, and judging whether the write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion condition of the write-in instruction after the write-in instruction is executed.
2. The RISC-V chip-based emulation debugging method of claim 1, wherein initializing the system of the chip to be debugged and the JTAG module in the chip to be debugged specifically are:
initializing a system of a chip to be debugged through a simulation environment, and calibrating a high-speed clock of the chip to be debugged to an expected value;
resetting the state of the JTAG module of the chip to be debugged according to the debugging signal, and reading the equipment ID number of the chip to be debugged;
after successfully reading the equipment ID number of the chip to be debugged, carrying out hard reset on the DTM of the JTAG module, and canceling all DMI transmission in the JTAG module; clearing error identification bits in the JTAG module to enable the DTM to execute new transmission; and executing Hart reset and debugging module reset in the JTAG module.
3. The RISC-V chip-based emulation debugging method of claim 1, wherein the completion status of the write instruction is read to determine whether the write operation of the JTAG module of the chip to be debugged is normal, specifically:
reading the completion state of the write-in instruction, and if the completion state is a busy state, continuing waiting;
if the completion state is an error state, judging that the write operation of the JTAG module of the chip to be debugged is abnormal;
and if the completion state is an error-free state, judging that the write operation of the JTAG module of the chip to be debugged is normal.
4. The RISC-V chip-based emulation debugging method of claim 1, wherein said performing read-write operations on a system memory according to a debugging signal and determining whether read-write operations of a JTAG module of said chip to be debugged are normal by reading a completion status of said read-write operations, further comprising:
and changing the state of the JTAG state machine according to the debugging signal, reading the write-in data corresponding to the write-in memory address in the system memory through a read instruction according to the state change of the JTAG state machine, and judging whether the read operation of the JTAG module is normal or not through reading the completion condition of the read instruction after the read instruction is executed.
5. The RISC-V chip-based emulation debugging method of claim 4, wherein said determining whether the read operation of the JTAG module is normal by reading the completion status of the read instruction is specifically:
reading the completion state of the reading instruction, and if the completion state is a busy state, continuing waiting;
if the completion state is an error state, judging that the read operation of the JTAG module of the chip to be debugged is abnormal;
and if the completion state is an error-free state, judging that the write operation of the JTAG module of the chip to be debugged is normal.
6. The RISC-V chip-based emulation debugging method of claim 5, wherein after judging that the write operation of the JTAG module of the chip to be debugged is normal, reading the read data of the read operation, and if the read data is identical to the write data, judging that the read-write debugging of the chip to be debugged is completed.
7. The RISC-V chip based emulation debugging method of claim 1, wherein the system memory comprises one or more of a system register, an SRAM memory area, and an EFLASH memory.
8. The RISC-V chip-based emulation debugging method of any one of claims 1-7, wherein the debugging signals comprise one or more of TCK, TMS, TDO, and TDI signals.
9. A simulation debugging device based on RISC-V chip is characterized by comprising:
the initialization module is used for initializing a system of a chip to be debugged and a JTAG module in the chip to be debugged;
the judging module is used for performing read-write operation on a system memory according to a debugging signal after initialization is completed, and judging whether the read-write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion state of the read-write operation; the method specifically comprises the following steps: and changing the state of the JTAG state machine according to the debugging signal, correspondingly writing write-in data into a write-in memory address of the system memory by sending a write-in instruction according to the state change of the JTAG state machine, and judging whether the write operation of the JTAG module of the chip to be debugged is normal or not by reading the completion condition of the write-in instruction after the write-in instruction is executed.
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