CN111863953A - Power switch device and manufacturing method thereof - Google Patents
Power switch device and manufacturing method thereof Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention discloses a power switch device and a manufacturing method thereof, mainly solving the problems of low threshold voltage and complex process for realizing high breakdown voltage of the existing power switch device, comprising the following steps: the gate structure comprises a substrate (1), a transition layer (2), a barrier layer (3), a first gate column (6), a second gate column (7), a source electrode (9), a drain electrode (10), a table board (11), a first gate electrode (12), a second gate electrode (13) and a passivation layer (14). The first grid column and the second grid column are both composed of a P-type layer (4) and an N-type layer (5); the N-type layer is composed of N‑Layers of type (51) and N+A layer of type (52); the barrier layer at the left side of the first gate pillar and the barrier layer at the right side of the second gate pillarEtching array holes (8); the upper part of the passivation layer is provided with a composite plate (15); and a protective layer (16) is arranged on the passivation layer and the periphery of the composite plate. The invention has simple manufacturing process, good forward blocking and reverse blocking and high threshold voltage, and can be used as a switching device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power switch device which can be used as a basic device of a power electronic system.
Technical Field
The power electronic system is widely applied to the fields of aerospace, industrial equipment, electric automobiles, household appliances and the like, and the power switch device is an important element of the power electronic system and is an important tool for realizing energy conversion and control. Therefore, the performance and reliability of the power switch device have a decisive influence on various technical indexes and performances of the whole power electronic system. At present, the performance of Si-based power switching devices has approached their theoretical limit and cannot meet the requirements of next generation of power electronic systems for high temperature, high voltage, high frequency, high efficiency and high power density. The third generation wide bandgap semiconductor material represented by GaN has the characteristics of large forbidden band width, high saturated electron drift velocity, large critical breakdown electric field and stable chemical property, and has unique advantages in the aspect of preparing power switching devices with lower on resistance, higher switching speed and higher breakdown voltage. Particularly, a high electron mobility device transistor based on a GaN-based heterojunction structure, namely a GaN-based high electron mobility transistor HEMT power switch device, has wide and special application prospects in the fields of national economy and military due to the excellent power characteristics of the high electron mobility device transistor.
The traditional GaN-based HEMT power switch device is based on a GaN-based heterojunction structure, and comprises: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a P type layer 4, a gate column 5, a source electrode 6, a drain electrode 7, a gate electrode 8, a table top 9 and a protective layer 10; a source electrode 6 is deposited on the left side above the barrier layer 3, a drain electrode 7 is deposited on the right side above the barrier layer 3, a P-type layer 4 is epitaxially grown on the barrier layer 3 between the source electrode 6 and the drain electrode 7, a gate electrode 8 is deposited on the P-type layer 4, and a protective layer 10 completely covers the barrier layer 3, the P-type layer 4, the source electrode 6, the drain electrode 7 and the region above the gate electrode 8, as shown in fig. 1.
However, in the conventional GaN-based HEMT power switching device, the activation rate of the P-type impurity magnesium in the P-type layer is low, and it is difficult to realize a highly doped P-type layer, so that the threshold voltage of the device tends to be lower than 2V. And studies have shown that a P-type layer with too high a doping concentration can in turn lead to a reduction in the threshold voltage of the device, see On the physical operation and optimization of the P-GaN gate in normal-off GaN HEMTs devices, Applied Physics Letters, vol.110, No.12, pp.1-5,2017. In addition, in the conventional GaN-based HEMT power switch device, an extremely high electric field peak is usually formed near the drain electrode of the device, so that when a positive drain voltage is applied to the device, namely, when the device is in a forward off state, the forward breakdown voltage of the device is far lower than a theoretically expected value, and the reliability problems of current collapse, inverse piezoelectric effect and the like exist, so that the practical application of the device is severely restricted. In order to solve the above practical problems, researchers have proposed many methods, and the multi-layer field plate structure is one of the most significant ones, see A130-W Boost Converter Operation Using a High-Voltage GaN-HEMT, IEEE Electron devices Letters, Vol.29, No.1, pp.8-10,2008.
In many technical fields of current electric vehicles, power management systems, class-S power amplifiers and the like, a power switching device is often required to have a strong reverse blocking capability, i.e., a reverse off-state capability, that is, it is desirable that the device has a high negative drain breakdown voltage, i.e., a reverse breakdown voltage, in an off-state. Since the drain of the conventional GaN-based HEMT power switching device is ohmic contact, a reverse voltage cannot be applied. Researchers have proposed a power switch device using schottky drain, see AlGaN/GaN HEMT With Integraded Recessed Schotty-Drain Protection Diode, IEEEElectron Device Letters, Vol.30, No.9, pp.901-903,2009. However, the schottky drain has a very limited ability to improve the reverse blocking characteristic of the device, so in order to further improve the reverse blocking capability of the power switching device, researchers have proposed a power switching device based on a source field plate and a drain field plate to take into account the forward and reverse blocking capabilities of the device, see Design optimization of high breakdown voltage AlGaN-GaN power on an insulating substrate for RONA-VBtrandeoff characteristics, IEEEtransactions on Electron Devices, Vol.52, No.1, pp.106-111,2005. In addition, the double-layer field plate structure is combined with the power switch device based on the source field plate and the drain field plate, namely the source field plate with the double-layer field plate structure and the drain field plate with the double-layer field plate structure are adopted to form the source-drain composite double-layer field plate power switch device, so that the forward and reverse breakdown voltages of the device can be further improved. However, the process of the source-drain composite double-layer field plate power switch device is complex, the manufacturing cost is higher, and the manufacturing of each layer of field plate needs the process steps of photoetching, metal deposition, passivation medium deposition and the like. And moreover, the thickness of the dielectric material under each layer of field plate needs to be optimized to realize the maximization of breakdown voltage, and complicated process debugging and optimization are needed, so that the difficulty of manufacturing the device is greatly increased, and the yield of the device is reduced.
Disclosure of Invention
The invention aims to provide a power switch device and a manufacturing method thereof aiming at the defects of the prior art, so as to remarkably improve the threshold voltage and the bidirectional blocking voltage of the device, effectively reduce the on-resistance of the device, reduce the manufacturing difficulty of the device and improve the reliability of the device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
A power switching device comprising, from bottom to top: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a P-type layer 4, an N-type layer 5 and a passivation layer 14, wherein a table top 11 is carved on the side surface of the barrier layer 3, and a first gate column 6 and a second gate column 7 are respectively arranged on two sides of the upper part of the barrier layer 3; a first grid electrode 12 is deposited on the first grid column 6, and a source electrode 9 is deposited on the left side of the first grid column; a second grid electrode 13 is deposited on the second grid column 7, and a drain electrode 10 is deposited on the right side of the second grid column; array holes 8 are etched in the barrier layer 3 on the left side of the first gate column 6 and the barrier layer 3 on the right side of the second gate column 7, and the array structure is characterized in that:
the first gate column 6 and the second gate column 7 are cuboids with the same size and are both composed of a P-type layer 4 and an N-type layer 5;
the N-type layer 5 consists of lower N-Layer 51 and upper N+A layer of type 52;
said N is-The layer 51 and the P-type layer 4 form a PN junction, and the PN junction of each gate column is the same in size;
2n +1 grooves with the same size are etched in the passivation layer 14 in the region between the first gate column 6 and the second gate column 7, wherein n is larger than or equal to 1; the upper part of the composite board is provided with a composite board 15;
the composite plate 15 is composed of a left modulation plate, a right modulation plate and 2n-1 independent metal blocks with the same size, the lower ends of the independent metal blocks are completely filled in 2n +1 grooves, the left modulation plate is electrically connected with the source electrode 9, the right modulation plate is electrically connected with the drain electrode 10, and the independent metal blocks are suspended mutually; the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center, and n is more than or equal to 1;
the passivation layer 14 and the outer periphery of the composite plate 15 are provided with a protective layer 16.
Further, the length of the source electrode 9 and the drain electrode 10 is LOAnd the width is W.
Further, the array of wells 8 consists of f × g wells of the same size, f>1，g>1, each hole is composed of an upper rectangular hole column 81 and a lower rectangular pyramid 82, and the distance k between two adjacent holes30.5 to 3 μm, the boundary distance k between the outermost hole and the source electrode 9 or the drain electrode 1011-4 μm; the upper and lower surfaces of the hole columns 81 are square, and the side length k of the square20.5-2 μm, the depth r of the hole columns 81 is 2-20 nm, and the lower surfaces of the hole columns 81 are superposed with the upper surfaces of the rectangular pyramids 82; the depth e of the rectangular pyramid 82 is 1-35 nm, and the four sides are the same.
Furthermore, the grooves on the passivation layer 14 have the same size, the depth d of each groove is greater than 0 μm and smaller than the thickness of the passivation layer 14, and the width a is 0.1-4 μm.
Further, the composite board 15 takes the nth independent metal block as a symmetry axis, and on the left side of the symmetry axis, the distance between the left modulation board and the first independent metal block is S1The distance between the first independent metal block and the second independent metal block is S2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Sn，S1<S2<...<Sn(ii) a On the right side of the symmetry axis, the distance between the right modulation plate and the 1 st independent metal block is U1The distance between the 1 st independent metal block and the 2 nd independent metal block is U2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Un，U1<U2<...<UnAnd S is1＝U1，S2＝U2，...，Sn＝Un，n≥1。
Further, the thickness of the left modulation board, the thickness of the right modulation board and the thickness of each independent metal block are the same, the length t of each independent metal block is 0.5-5 microns, the distance between the right edge of the left modulation board and the right edge of the first grid column 6 is equal to the distance between the left edge of the right modulation board and the left edge of the second grid column 7, and the distance is L.
Furthermore, each groove takes the (n + 1) th groove as a symmetry axis, and the distance between the first grid column 6 and the first groove is b on the left side of the symmetry axis1And 0 μm<b1<(L-a) the first groove is spaced from the second groove by a distance c1And so on, the distance between the nth groove and the (n + 1) th groove is cn，c1<c2<...<cn(ii) a On the right side of the symmetry axis, the distance between the second grid column 7 and the 1 st groove is b2And 0 μm<b2<(L-a) the distance between the 1 st groove and the 2 nd groove is i1By analogy, the distance between the nth groove and the (n + 1) th groove is in，i1<i2<...<inAnd b is1＝b2,c1＝i1,c2＝i2,…,cn＝in,n≥1。
Further, in the first gate pillar 6 and the second gate pillar 7, N+The thickness of the layer 52 is less than N-Thickness of the layer 51, N+The doping concentration of the layer 52 is equal to or greater than N-The doping concentration of the layer 51; n is a radical of-The thickness of the type layer 51 is more than or equal to that of the P-type layer 4, the thickness of the P-type layer 4 is 5-300 nm, and N is-The doping concentration of the type layer 51 is less than or equal to that of the P-type layer 4, and the lengths of the first gate 12 and the second gate 13 are equal to each other and less than that of the first gate column 6.
Second, the manufacturing method
The method for manufacturing the power switch device is characterized by comprising the following steps of:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate 1 by adopting a metal organic chemical vapor deposition technology to form a transition layer 2 with the thickness of 1-10 mu m;
B) extending a GaN-based wide bandgap semiconductor material on the transition layer 2 by adopting a metal organic chemical vapor deposition technology to form a barrier layer 3 with the thickness of 4-60 nm;
C) a P-type GaN semiconductor material is epitaxially formed on the barrier layer 3 by adopting a metal organic chemical vapor deposition technology to form a GaN semiconductor layer with the thickness of 5-300 nm and the doping concentration of 5 multiplied by 1016～5×1020cm-3P-type layer 4;
D) manufacturing an N-type layer 5:
D1) the N-type GaN semiconductor material is epitaxially formed on the P-type layer 4 by adopting the metal organic chemical vapor deposition technology, the thickness of the formed P-type layer 4 is more than or equal to that of the formed N-type GaN semiconductor material, and the doping concentration of the formed N-type GaN semiconductor material is 1 multiplied by 1011～1×1018cm-3N of (A)-A layer 51;
D2) in N-The N-type GaN semiconductor material is epitaxially formed on the layer 51 by MOCVD to a thickness less than N-Layer 51 with a doping concentration of 1X 1018～5×1020cm-3N of (A)+Layer of type 52, N-Layers 51 and N+The layers 52 together form an N-type layer 5;
E) manufacturing a mask on the N-type layer 5 for the first time, etching the two sides of the N-type layer 5 by using the mask until the upper surface of the barrier layer 3 is etched to form a first gate column 6 and a second gate column 7 which are cuboid, have the same size and are longer than or equal to 1 nm;
F) preparing array holes 8:
F1) making masks on the upper parts of the barrier layer 3, the first gate column 6 and the second gate column 7 for the second time, and etching the barrier layer 3 on the left side and the right side by using the masks to form f × g cuboid hole columns 81 with the same size;
F2) a mask is made on the barrier layer 3, the first gate post 6 and the second gate post 7 for the third time, and F × g cuboid hole posts 81 with the same size formed by F1) are etched by using the mask to form rectangular pyramids 82 on the lower parts of the hole posts 81, and the F × g cuboid hole posts 81 with the same size and the rectangular pyramids 82 on the lower parts of the rectangular hole posts 81 and the rectangular pyramids form array holes 8 together;
G) manufacturing a source electrode 9 and a drain electrode 10:
G1) manufacturing masks on the upper parts of the barrier layer 3, the first gate column 6 and the second gate column 7 for the fourth time, depositing metal on the barrier layer 3 on the left side and the right side by using an electron beam evaporation technology by using the masks, and completely filling the array holes 8, wherein the metal adopts Gd, Zr or Ta;
G2) continuing with the mask of G1), depositing a metal using one of Ti/Al/Ni/Au, Ti/Al/Mo/Au or Ti/Al/Ti/Au again using electron beam evaporation techniques and in N2Performing rapid thermal annealing in the atmosphere to complete the manufacture of the source electrode 9 and the drain electrode 10;
H) making masks on the barrier layer 3, the first gate column 6, the second gate column 7, the source electrode 9 and the drain electrode 10 for the fifth time, etching the barrier layer 3 on the left side of the source electrode 9 and the right side of the drain electrode 10 by using the masks, and forming a table top 11, wherein the depth of an etching area is greater than the thickness of the barrier layer;
I) making a mask on the barrier layer 3, the first gate column 6, the second gate column 7, the source electrode 9, the drain electrode 10 and the upper part of the table top 11 for the sixth time, depositing metal on the first gate column 6 and the second gate column 7 by using the mask through an electron beam evaporation technology, and making a first gate electrode 12 and a second gate electrode 13, wherein the two gate electrodes are equal in length and are both smaller than the first gate column 6;
J) depositing a passivation layer 14 with the thickness of more than or equal to 100nm on the upper parts and the peripheral areas of the first gate column 6, the second gate column 7, the source electrode 9, the drain electrode 10, the first gate electrode 12 and the second gate electrode 13 by adopting a plasma enhanced chemical vapor deposition technology;
K) manufacturing a mask on the passivation layer 14 for the seventh time, and etching 2n +1 grooves with the same size on the passivation layer 14 between the first gate pillar 6 and the second gate pillar 7 by using the mask, wherein n is more than or equal to 1;
l) manufacturing masks on the passivation layer 14 and the upper portion of the groove for the eighth time, depositing metal on the upper portion of the passivation layer 14 and in the groove by using an electron beam evaporation technology by using the masks, wherein the lower end of the metal is completely filled in the groove, sequentially manufacturing a left modulation plate, 2n-1 independent metal blocks and a right modulation plate, wherein n is more than or equal to 1, the left modulation plate is electrically connected with the source electrode 9, the right modulation plate is electrically connected with the drain electrode 10, the independent metal blocks are suspended from each other, and the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center to form a composite plate 15;
m) depositing a protective layer 16 on the passivation layer 14 and the peripheral region of the composite plate 15 by using an insulating dielectric material and adopting a plasma enhanced chemical vapor deposition technology, thereby completing the manufacture of the whole device.
Compared with the traditional GaN-based HEMT power switch device, the device has the following advantages:
firstly, the device of the invention adopts N below the grid electrode+Layer of type 52, N-The layer 51 and the P-type layer 4 structure, N when the grid is forward biased-The type layer 51 is fully depleted, forming a high resistance space charge region that shares most of the gate voltage and is formed by increasing N-Thickness of the layer 51, N reduction-The concentration of the type layer 51, etc., may further increase the gate voltage shared by the high resistance region. In addition, in N-The P-type layer side of the interface between the layer 51 and the P-type layer 4 also forms a region of high resistance space charge that can also share a portion of the gate voltage. Therefore, the threshold voltage of the device can be obviously improved.
Secondly, the device adopts the structure of the array holes 8 below the source electrode 9 and the drain electrode 10, and the electrical characteristics of the metal in each hole in contact with the barrier layer can be effectively modulated by adjusting the shapes of the cuboid hole column at the upper part and the rectangular pyramid at the lower part of each hole in the array holes and the relative position relationship of each hole, so that the ohmic contact resistance of the source electrode and the drain electrode of the device is effectively reduced.
Thirdly, the composite plate structure is adopted above the passivation layer 14, so that the potential distribution in the barrier layer between the first gate column 6 and the second gate column 7 can be effectively modulated, when the device is blocked in the forward direction, namely the first gate is biased at 0V, the second gate is in short circuit with the drain and a high potential greater than the potential of the source is applied, the potential in the barrier layer can be increased from the first gate column 6 to the second gate column 7 in a gradual mode, and when the device is blocked in the reverse direction, namely the second gate is biased at 0V, the first gate is in short circuit with the source and a high potential greater than the potential of the drain is applied, the potential in the barrier layer can be increased from the second gate column 7 to the first gate column 6 in a gradual mode. Therefore, when the device is blocked in the forward direction or the reverse direction, the composite plate structure adopted in the device can realize approximately uniform electric field distribution in the barrier layer between the first grid column 6 and the second grid column 7, so that the voltage resistance of the barrier layer between the first grid column 6 and the second grid column 7 can be fully exerted, and the forward breakdown voltage and the reverse breakdown voltage of the device are remarkably improved.
Drawings
Fig. 1 is a structural view of a conventional GaN-based HEMT power switch device;
FIG. 2 is a block diagram of the power switching device of the present invention;
FIG. 3 is a top view of an array of holes in a device of the present invention;
FIG. 4 is a cross-sectional view of an array of holes from left to right in a device of the present invention;
FIG. 5 is a perspective view of an array of holes in a device of the present invention;
FIG. 6 is a schematic overall flow chart of the present invention for fabricating a power switching device;
FIG. 7 is a graph of transfer characteristics simulated for a conventional device and a device of the present invention;
fig. 8 is a graph of breakdown characteristics simulated for a conventional device and a device of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, the power switching device of the present example includes: substrate 1, transition layer 2, barrier layer 3, P type layer 4, N type layer 5, first gate post 6, second gate post 7, array hole 8, source 9, drain electrode 10, mesa 11, first grid 12, second grid 13, passivation layer 14, composite sheet 15 and protective layer 16, wherein:
the substrate 1 is made of sapphire, silicon carbide or silicon material;
the transition layer 2 is positioned at the upper part of the substrate 1 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the transition layer is 1-10 mu m;
the barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the barrier layer is 4-60 nm;
the first gate column 6 and the second gate column 7 are cuboids with the same size, are respectively positioned at two sides of the upper part of the barrier layer 3, and are respectively composed of a P-type layer 4 and an N-type layer 5, and the N-type layer 5 is composed of an N layer at the lower part-Layer 51 and upper N+Layer 52 composition, N-The layer 51 and the P-type layer 4 form two PN junction structures with the same size, the PN junction of each gate column has the same size, the length of each gate column is more than or equal to 1nm, and each N is N+The thickness of the layer 52 is less than N-Thickness of the layer 51, N+The doping concentration of the layer 52 is equal to or greater than N-The doping concentration of the type layer 51, the thickness of the P-type layer 4 is 5-300 nm, and N-The thickness of the type layer 51 is greater than or equal to that of the P-type layer 4, and the doping concentration of the P-type layer 4 is 5 x 1016～5×1020cm-3，N-The doping concentration of the layer 51 is 1 × 1011～1×1018cm-3，N+The doping concentration of the layer 52 is 1 x 1018～5×1020cm-3And N is-The doping concentration of the layer 51 is less than or equal to that of the P-type layer 4;
the barrier layer 3 at the left side of the first gate pillar 6Array holes 8 are arranged in the barrier layer 3 on the right side of the second gate column 7, each array hole 8 is composed of f multiplied by g holes with the same size, and f>1，g>1, each hole is composed of an upper rectangular hole column 81 and a lower rectangular pyramid 82, and the distance k between two adjacent holes30.5 to 3 μm, the boundary distance k between the outermost hole and the source electrode 9 or the drain electrode 1011-4 μm as shown in FIG. 3; the upper and lower surfaces of the hole columns 81 are square, and the side length k of the square20.5-2 μm, the depth r of the hole pillars 81 is 2-20 nm, and the lower surfaces of the hole pillars 81 and the upper surfaces of the rectangular pyramids 82 coincide, as shown in FIG. 4; the depth e of the rectangular pyramid 82 is 1-35 nm, and the four side surfaces are the same, as shown in FIG. 5;
the source electrode 9 is positioned at the left side of the first gate column 6, the drain electrode 10 is positioned at the right side of the second gate column 7, the source electrode 9 and the drain electrode 10 completely fill the array hole 8, and the length of the array hole is LOThe width is W;
the mesa 11 is positioned at two edges of the barrier layer 3, and the depth of the mesa is greater than the thickness of the barrier layer 3;
the first grid 12 and the second grid 13 are respectively positioned on the first grid column 6 and the second grid column 7, the lengths of the first grid 12 and the second grid 13 are equal, and the lengths are smaller than the length of the first grid column 6;
the passivation layer 14 has a thickness of 100nm or more, and completely covers the first gate pillar 6, the second gate pillar 7, the source electrode 9, the drain electrode 10, the first gate electrode 12, the upper portion of the second gate electrode 13 and the peripheral region thereof, and the passivation layer 14 is made of SiO2、SiN、Al2O3、Sc2O3、HfO2、TiO2Any one of or other insulating dielectric materials;
2n +1 grooves are formed in the passivation layer 14 between the first gate pillar 6 and the second gate pillar 7, n is larger than or equal to 1, the grooves are the same in size, the depth d of each groove is larger than 0 mu m and smaller than the thickness of the passivation layer 14, and the width a is 0.1-4 mu m; the two grid columns 6 and 7 take the n +1 th groove as a symmetry axis, and the left side of the symmetry axis has the distance b between the first grid column 6 and the first groove1And 0 μm<b1<(L-a) the first groove is spaced from the second groove by a distance c1By analogy, the nth groove and the (n + 1) th grooveThe groove pitch is cnAnd c is and c1<c2<...<cn(ii) a On the right side of the symmetry axis, the distance between the second grid column 7 and the 1 st groove is b2And 0 μm<b2<(L-a) the distance between the 1 st groove and the 2 nd groove is i1By analogy, the distance between the nth groove and the (n + 1) th groove is in，i1<i2<...<inAnd b is1＝b2,c1＝i1,c2＝i2,…,cn＝in,n≥1；
The composite plate 15 is located on the upper portion of the passivation layer 14, and is composed of a left modulation plate, a right modulation plate and 2n-1 independent metal blocks with the same size, the lower end of the composite plate is completely filled in 2n +1 grooves, the left modulation plate is electrically connected with the source electrode 9, the right modulation plate is electrically connected with the drain electrode 10, and the independent metal blocks are suspended in the air; the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center, and n is more than or equal to 1. Taking the nth independent metal block as a symmetry axis, and on the left side of the symmetry axis, the distance between the left modulation board and the first independent metal block is S1The distance between the first independent metal block and the second independent metal block is S2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Sn，S1<S2<...<Sn(ii) a On the right side of the symmetry axis, the distance between the right modulation plate and the 1 st independent metal block is U1The distance between the 1 st independent metal block and the 2 nd independent metal block is U2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Un，U1<U2<...<UnAnd S is1＝U1，S2＝U2，...，Sn＝UnN is more than or equal to 1; the thickness of the left modulation plate, the thickness of the right modulation plate and the thickness of each independent metal block are the same, the length t of each independent metal block is 0.5-5 mu m, the distance between the right edge of the left modulation plate and the right edge of the first grid column 6 is equal to the distance between the left edge of the right modulation plate and the left edge of the second grid column 7, and the distance is L.
The protective layer 16 is located on the passivation layer14 and a peripheral region of the composite plate 15, which employs SiO2、SiN、Al2O3、Sc2O3、HfO2、TiO2Or other insulating dielectric material.
Referring to fig. 6, the power switch device manufactured by the present invention provides the following three embodiments.
The first embodiment is as follows: the P-type layer 4 is made with a thickness of 5nm and a concentration of 51020cm-3，N-The layer 51 has a thickness of 100nm and a concentration of 5X 1017cm-3，N+The layer 52 has a thickness of 50nm and a concentration of 5X 1020cm-3The lengths of the first gate column 6 and the second gate column 7 are both 1nm, the array hole 8 is composed of 2 multiplied by 2 holes with the same size, the number of the grooves is 3, and the number of the independent metal blocks is 1.
1a) A GaN material with the thickness of 30nm is epitaxially grown on a sapphire substrate 1 by using a metal organic chemical vapor deposition technology, and the process conditions are as follows: the temperature is 530 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the gallium source flow is 22 mu mol/min;
1b) GaN material with the thickness of 0.97 mu m is epitaxially grown on the GaN material by using a metal organic chemical vapor deposition technology to form an undoped transition layer 2, and the process conditions are as follows: the temperature was 960 deg.C, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, and the gallium source flow was 120. mu. mol/min.
Step 2, depositing undoped Al on the undoped GaN transition layer 20.3Ga0.7N produces the barrier layer 3 as shown in fig. 6 b.
Depositing undoped Al with a thickness of 4nm and an aluminum composition of 0.3 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique0.3Ga0.7The process conditions of the N barrier layer 3 are as follows: the temperature was 980 ℃, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, the gallium source flow was 35. mu. mol/min, and the aluminum source flow was 7. mu. mol/min.
Step 3. epitaxial P-type layer 4 on barrier layer 3, as shown in fig. 6 c.
Epitaxial thickness of 5nm and doping concentration of 5 × 10 on the barrier layer 3 by using metal organic chemical vapor deposition20cm-3P-type GaN semiconductor material of (4) to form a P-type layer.
The epitaxial process conditions are as follows: the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the high-purity Mg source is used as a doping agent, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min.
Step 4, manufacturing an N-type layer 5, as shown in FIG. 6 d.
4a) The epitaxial thickness of 100nm and the doping concentration of 5 x 10 are formed on the P-type layer 4 by using the metal organic chemical vapor deposition technology17cm-3Forming N is formed of the N-type GaN semiconductor material-A layer 51 of the type.
The epitaxial process conditions are as follows: high purity SiH at 950 deg.C, 40Torr and 4000sccm hydrogen flow4As a doping agent, the flow rate of ammonia gas is 4000sccm, and the flow rate of a gallium source is 100 mu mol/min.
4b) Using metal organic chemical vapor deposition techniques on N-The epitaxial layer 51 has an epitaxial thickness of 50nm and a doping concentration of 5X 1020cm-3Forming N is formed of the N-type GaN semiconductor material+Layer of type 52, N-Layers 51 and N+The layers 52 together form an N-type layer 5.
The epitaxial process conditions are as follows: high purity SiH at 950 deg.C, 40Torr and 4000sccm hydrogen flow4As a doping agent, the flow rate of ammonia gas is 4000sccm, and the flow rate of a gallium source is 100 mu mol/min.
And 5, manufacturing a first gate pillar 6 and a second gate pillar 7, as shown in fig. 6 e.
Making a mask on the N-type layer 5 for the first time, etching the two sides of the N-type layer 5 by using a reactive ion etching technology to form a first grid column 6 and a second grid column 7 which are 1nm in length, wherein the etching depth is 155nm, and the etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step 6. make array holes 8, as shown in FIG. 6 f.
6a) Al at a thickness of 4nm0.3Ga0.7Making mask on the N barrier layer 3, the first gate pillar 6 and the second gate pillar 7 for the second time, wherein the mask pattern is composed of 2 x 2 side lengths k2Is an array of square holes of 0.5 μm, the spacing k of two adjacent holes30.5 μm, boundary spacing k of the outermost hole and the source electrode 9 or the drain electrode 101Is 1 μm; using the mask to etch Al by reactive ion etching0.3Ga0.72 x 2 cuboid hole columns 81 are etched on the N barrier layer 3, wherein the depth r of each hole column 81 is 2 nm.
The etching hole column 81 adopts the following process conditions: cl2/BCl3The flow ratio was 3:1, the pressure was 30mTorr, and the power was 150W.
6b) Al at a thickness of 4nm0.3Ga0.7A mask is made on the N barrier layer 3, the first gate post 6 and the second gate post 7 for the third time, the same rectangular pyramid 82 is made by etching in 2 × 2 rectangular hole posts 81 with the same size formed in 6a) by using the mask through a reactive ion etching technology, and the 2 × 2 rectangular hole posts 81 with the same size and the rectangular pyramid 82 at the lower part form an array hole 8 together. The upper surfaces of the rectangular pyramids coincide with the lower surface of the hole pillar 81, the depth e of the rectangular pyramid 81 is 1nm, the four sides are the same, and Al0.3Ga0.7The thickness of the N barrier layer 3 after etching was 1 nm.
The process conditions adopted for etching the rectangular pyramid 82 are as follows: BCl3The flow rate is 60sccm, the pressure is 25mTorr, and the power is 150W.
And 7, manufacturing a source electrode 9 and a drain electrode 10, as shown in fig. 6 g.
7a) And manufacturing a mask for the fourth time on the upper parts of the barrier layer 3, the first gate column 6 and the second gate column 7, depositing metal on the barrier layer 3 on the left side and the right side by using an electron beam evaporation technology by using the mask, and completely filling the array holes 8, wherein the metal adopts Gd.
The process conditions adopted for depositing the metal are as follows: high purity Gd source with vacuum degree less than 1.8 x 10-3Pa, power of 400W, evaporation rate of less than
7b) Continuing to deposit metal again by electron beam evaporation using the mask of 7a), and depositing N2And carrying out rapid thermal annealing in the atmosphere to manufacture the source electrode 9 and the drain electrode 10, wherein the deposited metal is a Ti/Al/Ni/Au metal combination, namely Ti, Al, Ni and Au are respectively arranged from bottom to top, and the thickness of the deposited metal is 0.018 mu m/0.135 mu m/0.046 mu m/0.052 mu m.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 850 ℃ and the time was 35 s.
And 8, etching the barrier layers on the left side of the source electrode 9 and the right side of the drain electrode 10 to manufacture a table top 11, as shown in fig. 6 h.
And manufacturing masks on the barrier layer 3, the first gate column 6, the second gate column 7, the source electrode 9 and the drain electrode 10 for the fifth time, and etching the barrier layer on the left side of the source electrode 9 and the right side of the drain electrode 10 by using the masks by using a reactive ion etching technology to form a mesa 11, wherein the etching depth is 80 nm.
The etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step 9, fabricate the first gate 12 and the second gate 13, as shown in fig. 6 i.
And manufacturing a mask on the barrier layer 3, the first gate column 6, the second gate column 7, the source electrode 9, the drain electrode 10 and the upper part of the table top 11 for the sixth time, depositing metal on the first gate column 6 and the second gate column 7 by using an electron beam evaporation technology by using the mask, and manufacturing a first gate electrode 12 and a second gate electrode 13, wherein the lengths of the two gate electrodes are equal and are both smaller than the length of the first gate column 6, the deposited metal is a Ni/Au metal combination, namely the lower layer is Ni, the upper layer is Au, and the thickness of the deposited metal is 0.045 mu m/0.20 mu m.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 200W, evaporation rate of less than
Depositing SiO with the thickness of 100nm on the upper parts of the first gate column 6, the second gate column 7, the source electrode 9, the drain electrode 10, the first gate electrode 12 and the second gate electrode 13 and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology2A passivation layer 14.
The process conditions for depositing the passivation layer 14 are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the RF power was 20W, and the pressure was 1100 mT.
Step 11, make 3 grooves, as shown in fig. 6 k.
And manufacturing a mask on the passivation layer 14 for the seventh time, and etching the passivation layer 14 between the first gate pillar 6 and the second gate pillar 7 by using the mask by using a reactive ion etching technology to manufacture 3 grooves with the same depth and the same width, wherein the width a of the groove is 0.1 μm, and the depth d of the groove is 80 nm. The two grids 6 and 7 take the 2 nd groove as a symmetry axis, and the distance b between the first grid 6 and the first groove is arranged on the left side of the symmetry axis10.5 μm, the distance c between the first and second grooves10.5 μm; on the right side of the symmetry axis, the distance b between the second grid pillar 7 and the 1 st groove20.5 μm, the distance i between the 1 st and the 2 nd grooves1And was 0.5 μm.
The etching adopts the following process conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And step 12, manufacturing a left modulation board, 1 independent metal block and a right modulation board, as shown in FIG. 6 l.
Making a mask on the upper parts of the passivation layer 14 and the 3 grooves for the eighth time, depositing metal on the passivation layer between the first grid column 6 and the second grid column 7 in the 3 grooves by using an electron beam evaporation technology to make a left modulation plate, 1 independent metal block and a right modulation plate, electrically connecting the left modulation plate with the source electrode 9, electrically connecting the right modulation plate with the drain electrode 10, suspending the independent metal blocks, and symmetrically distributing the left modulation plate and the right modulation plate around the 1 st independent metal block to form a composite plate 15, wherein the deposited metal is a Ti/Au metal groupThe lower layer is Ti and the upper layer is Au, and the thickness is 0.1 μm/0.05 μm. Wherein the deposited metal completely fills the 3 recesses, the spacing S of the left modulator plate from its first independent metal block10.1 μm, the distance U between the right modulation plate and the 1 st independent metal block10.1 μm, the length t of the free-standing metal block is 0.5 μm, the distance between the right edge of the left modulator plate and the right edge of the first gate pillar 6 is equal to the distance between the left edge of the right modulator plate and the left edge of the second gate pillar 7, and the distance L is 0.8 μm.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 200W, evaporation rate of less than
Step 13. depositing SiO in the peripheral region of the passivation layer 14 and the composite plate 152A protective layer 16 is made, as shown in fig. 6 m.
Deposition of SiO in the peripheral region of the passivation layer 14 and the composite plate 15 using plasma enhanced chemical vapor deposition techniques2To produce a protective layer 16 having a thickness of 0.56 μm, thereby completing the production of the entire device.
The process conditions adopted for depositing the protective layer are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 deg.C, the RF power was 20W, and the pressure was 1100 mTorr.
Example two: the P-type layer 4 is made to have a thickness of 120nm and a concentration of 11018cm-3，N-The layer 51 has a thickness of 120nm and a concentration of 1X 1018cm-3，N+The layer 52 has a thickness of 30nm and a concentration of 1X 1018cm-3The lengths of the first gate column 6 and the second gate column 7 are both 1000nm, the array hole 8 is composed of 5 × 5 holes with the same size, the number of the grooves is 5, and the number of the independent metal blocks is 3.
Step one, a transition layer 2 is made by extending AlN and GaN materials from bottom to top on a silicon carbide substrate 1, as shown in figure 6 a.
1.1) extending an undoped AlN material with the thickness of 100nm on a silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the aluminum source flow is 5 mu mol/min;
1.2) using a metal organic chemical vapor deposition technology to epitaxially grow a GaN material with the thickness of 4.9 mu m on the AlN material under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the gallium source flow is 120 mu mol/min, and thus the manufacture of the transition layer 2 is completed.
Step two, depositing undoped Al on the GaN transition layer 20.2Ga0.8N produces the barrier layer 3 as shown in fig. 6 b.
Using metal organic chemical vapor deposition technology to deposit 20nm of undoped Al with the aluminum component of 0.2 on the GaN transition layer 2 under the process conditions that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4500sccm, the ammonia flow is 4500sccm, the gallium source flow is 37 mu mol/min and the aluminum source flow is 6 mu mol/min0.2Ga0.8An N barrier layer 3.
Step three, a P-type layer 4 is epitaxially grown on the barrier layer 3, as shown in fig. 6 c.
Using metal organic chemical vapor deposition technology to epitaxially grow a barrier layer 3 with a thickness of 120nm and a doping concentration of 1 × 10 under the process conditions of a high-purity Mg source as a dopant, a temperature of 950 ℃, a pressure of 40Torr, a hydrogen flow of 3900sccm, an ammonia flow of 3900sccm and a gallium source flow of 90 μmol/min18cm-3P-type GaN semiconductor material of (4) to form a P-type layer.
Step four, an N-type layer 5 is epitaxially grown on the P-type layer 4, as shown in FIG. 6 d.
4.1) chemical vapor deposition of high purity SiH using metal organic compounds4Is used as a dopant, the epitaxial thickness of the P-type layer 4 is 120nm and the doping concentration is 1 multiplied by 10 under the process conditions that the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4100sccm, the ammonia flow is 4100sccm and the gallium source flow is 120 mu mol/min18cm-3Forming N is formed of the N-type GaN semiconductor material-A layer 51;
4.2) chemical vapor deposition of high purity SiH using metal organic compounds4For mixing withImpurity agent, the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4100sccm, the ammonia flow is 4100sccm, the gallium source flow is 120 mu mol/min under the process condition of N-The epitaxial layer 51 has an epitaxial thickness of 30nm and a doping concentration of 1X 1018cm-3Forming N is formed of the N-type GaN semiconductor material+Layer of type 52, N-Layers 51 and N+The layers 52 together form an N-type layer 5.
And step five, manufacturing the first gate pillar 6 and the second gate pillar 7, as shown in fig. 6 e.
Making a mask on the N-type layer 5 for the first time, and etching Cl by using a reactive ion etching technology2And etching the two sides of the N-type layer 5 under the process conditions of 15sccm of flow, 10mTorr of pressure and 120W of power to form a first gate pillar 6 and a second gate pillar 7 which are 1000nm in length, wherein the etching depth is 270 nm.
Step six, making array holes 8, as shown in fig. 6 f.
6.1) Al at a thickness of 20nm0.2Ga0.8Making mask on the N barrier layer 3, the first gate pillar 6 and the second gate pillar 7 for the second time, wherein the mask pattern is composed of 5 × 5 side lengths k2Is an array of square holes of 1 μm, the spacing k between two adjacent holes 31 μm, the boundary spacing k between the outermost hole and the source electrode 9 or the drain electrode 101Is 2 μm; using the mask to perform a reactive ion etching process on Cl2/BCl3The flow ratio is 3:1, the pressure is 30mTorr and the power is 160W under the process conditions of Al0.2Ga0.8Etching and manufacturing 5 multiplied by 5 cuboid hole columns 81 on the N barrier layer 3, wherein the depth r of each hole column 81 is 8 nm;
6.2) Al at a thickness of 20nm0.2Ga0.8Making masks on the N barrier layer 3, the first gate pillar 6 and the second gate pillar 7 for the third time, and using the masks to etch 5 × 5 cuboid hole pillars 81 with the same size formed in 6.1) in BCl by using reactive ion etching technology3Under the process conditions of the flow of 60sccm, the pressure of 25mTorr and the power of 160W, the same rectangular pyramid 82 is etched, and the 5 × 5 cuboid hole columns 81 with the same size and the rectangular pyramid 82 at the lower part form array holes 8 together. The upper surfaces of these rectangular pyramids coincide with the lower surface of the hole pillar 81, and the depth e of the rectangular pyramids 818nm and four sides are the same, Al0.2Ga0.8The thickness of the N barrier layer 3 after etching was 4 nm.
Step seven, manufacturing a source electrode 9 and a drain electrode 10, as shown in fig. 6 g.
7.1) making a mask on the barrier layer 3, the first gate pillar 6 and the upper part of the second gate pillar 7 for the fourth time, and using the mask to use electron beam evaporation technology to form a high-purity Zr source on the barrier layer 3 at the left and right sides, wherein the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 450W, evaporation rate of less than
Under the process conditions of (1), depositing metal Zr, and completely filling the array holes 8;
7.2) continuing to use the mask in 7.1), again using electron beam evaporation technique in vacuum degree of less than 1.8 × 10- 3Pa, power of 450W, evaporation rate of less than
Under the process conditions of (1) depositing a metal and under the process conditions of a temperature of 850 ℃ and a time of 35s under N2And carrying out rapid thermal annealing in the atmosphere to manufacture the source electrode 9 and the drain electrode 10, wherein the deposited metal is a Ti/Al/Mo/Au metal combination, namely Ti, Al, Mo and Au are respectively arranged from bottom to top, and the thickness of the deposited metal is 0.015 mu m/0.132 mu m/0.048 mu m/0.056 mu m.
And step eight, etching the barrier layers on the left side of the source electrode 9 and the right side of the drain electrode 10 to manufacture a mesa 11, as shown in fig. 6 h.
Making a mask on the barrier layer 3, the first gate pillar 6, the second gate pillar 7, the source electrode 9 and the drain electrode 10 for the fifth time, and using the mask to perform reactive ion etching on the barrier layer on the left side of the source electrode 9 and the right side of the drain electrode 10 to form Cl2The mesa 11 is formed by etching vertically down to 200nm at a flow rate of 15sccm, a pressure of 10mTorr, and a power of 100W.
Step nine, the first gate 12 and the second gate 13 are fabricated, as shown in fig. 6 i.
A mask is formed on the barrier layer 3, the first gate pillar 6, the second gate pillar 7, the source electrode 9, the drain electrode 10 and the upper portion of the mesa 11 for the sixth time, and the mask is usedThe mask is formed on the first gate pillar 6 and the second gate pillar 7 by electron beam evaporation under vacuum degree of less than 1.8 × 10- 3Pa, power of 600W, evaporation rate of less than
Under the process conditions of (1), depositing metal to manufacture a first grid electrode 12 and a second grid electrode 13, wherein the lengths of the two grid electrodes are equal and are both smaller than the length of the first grid column 6, the deposited metal is a Pt/Au metal combination, the thickness of the lower layer Pt is 0.18 μm, and the thickness of the upper layer Au is 0.32 μm.
Step ten, the passivation layer 14 is manufactured, as shown in fig. 6 j.
The first gate column 6, the second gate column 7, the source electrode 9, the drain electrode 10, the first gate electrode 12, the second gate electrode 13 and the peripheral region thereof are subjected to a Plasma Enhanced Chemical Vapor Deposition (PECVD) process on NH3The flow rate was 2.5sccm, N2Flow rate 950sccm, SiH4The SiN passivation layer 14 is deposited at a thickness of 300nm under process conditions of a flow rate of 250sccm, a temperature of 300 deg.c, a RF power of 50W and a pressure of 950 mT.
Eleven. make 5 grooves, as in fig. 6 k.
A seventh process of forming a mask on the passivation layer 14, using the mask to etch the CF in the passivation layer 14 between the first gate pillar 6 and the second gate pillar 7 using a reactive ion etching technique4The flow rate was 45sccm, O25 grooves with the same depth and the same width are etched and manufactured under the process conditions that the flow is 5sccm, the pressure is 15mT and the power is 250W, the width a of each groove is 0.5 mu m, and the depth d is 250 nm. The two grid columns 6 and 7 take the 3 rd groove as a symmetry axis, and the left side of the symmetry axis is the distance b between the first grid column 6 and the first groove 11 μm, the first and second grooves having a spacing of c1The distance between the second groove and the third groove is c2And c is and c1<c2(ii) a On the right side of the symmetry axis, the distance b between the second grid pillar 7 and the 1 st groove2Is 1 μm, and the interval between the 1 st groove and the 2 nd groove is i1The distance between the 2 nd groove and the 3 rd groove is i2And i is1<i2，c1＝i1,c2＝i2。
And step twelve, manufacturing a left modulation board, 3 independent metal blocks and a right modulation board, as shown in FIG. 6 l.
Making a mask on the passivation layer 14 and the upper part of the 5 grooves for the eighth time, and using the mask to perform electron beam evaporation on the passivation layer between the first gate pillar 6 and the second gate pillar 7 in the 5 grooves under the condition that the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 600W, evaporation rate of less than
Under the process conditions of (1), depositing metal to manufacture a left modulation plate, 3 independent metal blocks and a right modulation plate, electrically connecting the left modulation plate with a source electrode 9, electrically connecting the right modulation plate with a drain electrode 10, suspending the 3 independent metal blocks, and symmetrically distributing the left modulation plate and the right modulation plate with the 3 rd independent metal block as the center to form a composite plate 15, wherein the deposited metal is a Ti/Au metal combination, namely the lower layer is Ti, the upper layer is Au, and the thickness of the composite plate is 0.2 mu m/0.11 mu m. Wherein the deposited metal is to completely fill 5 grooves, the 2 nd independent metal block is taken as a symmetry axis, and the left side of the symmetry axis is the space S between the left modulation board and the first independent metal block10.26 μm, the spacing S of the first independent metal block and the second independent metal block20.52 μm; distance U between right modulation board and 1 st independent metal block10.26 μm, the distance U between the 1 st and 2 nd independent metal blocks20.52 μm, the length t of the free-standing metal block is 2 μm, the distance between the right edge of the left modulator board and the right edge of the first gate pillar 6 is equal to the distance between the left edge of the right modulator board and the left edge of the second gate pillar 7, and the distance L is 2.25 μm.
Thirteen step of depositing SiO in the peripheral region of the passivation layer 14 and the composite plate 152A protective layer 16 is made, as shown in fig. 6 m.
Using plasma enhanced chemical vapor deposition techniques on N2O flow rate of 850sccm, SiH4Depositing SiO on the peripheral area of the passivation layer 14 and the composite plate 15 under the process conditions of the flow rate of 200sccm, the temperature of 250 ℃, the RF power of 50W and the pressure of 1100mTorr2To produce a protective layer 16 having a thickness of 0.7 μm, thereby completing the production of the entire device.
Example three: the P-type layer 4 is made to have a thickness of 300nm and a concentration of 51016cm-3，N-The layer 51 has a thickness of 350nm and a concentration of 1X 1011cm-3，N+The layer 52 has a thickness of 100nm and a concentration of 5X 1019cm-3The lengths of the first gate post 6 and the second gate post 7 are both 10 μm, the array hole 8 is composed of 10 × 10 holes with the same size, the number of the grooves is 7, and the number of the independent metal blocks is 5.
Step A. epitaxial growth of AlN and GaN materials on a silicon substrate 1 from bottom to top to form a transition layer 2, as shown in FIG. 6 a.
Firstly, a metal organic chemical vapor deposition technology is used for extending AlN material with the thickness of 400nm on a silicon substrate 1, and the process conditions are as follows: the temperature is 800 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the aluminum source flow is 25 mu mol/min;
then, a GaN material with the thickness of 9.6 μm is epitaxially grown on the AlN material by using a metal organic chemical vapor deposition technology, and the manufacture of the transition layer 2 is completed, wherein the process conditions are as follows: the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 120 mu mol/min.
Step B, depositing undoped Al on the GaN transition layer 20.1Ga0.9N produces the barrier layer 3 as shown in fig. 6 b.
Depositing undoped Al with a thickness of 60nm and an aluminum composition of 0.1 on the GaN transition layer 2 by using a metal-organic chemical vapor deposition technique0.1Ga0.9An N barrier layer 3;
the deposition process conditions are as follows: the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, the gallium source flow is 35 mu mol/min, and the aluminum source flow is 7 mu mol/min.
Step c. epitaxial P-type layer 4 on barrier layer 3, as in fig. 6 c.
Epitaxial thickness of 30 a on the barrier layer 3 using a metal organic chemical vapor deposition technique0nm, 5 × 10 doping concentration16cm-3Forming a P-type layer 4 of P-type GaN semiconductor material;
the epitaxial process conditions are as follows: the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4100sccm, the high-purity Mg source is used as a doping agent, the ammonia flow is 4100sccm, and the gallium source flow is 110 mu mol/min.
Step d. epitaxial N-type layer 5 on P-type layer 4, as shown in fig. 6 d.
Firstly, a metal organic chemical vapor deposition technology is used to epitaxially grow a layer with a thickness of 350nm and a doping concentration of 1 × 10 on the P-type layer 411cm-3Forming N is formed of the N-type GaN semiconductor material-Layer of type 51 having an epitaxy of N-Process conditions adopted for the layer 51: high purity SiH at 950 deg.C, 40Torr, 4200sccm hydrogen flow4As a dopant, the flow rate of ammonia gas was 4200sccm and the flow rate of gallium source was 105. mu. mol/min.
Then, using a metal organic chemical vapor deposition technique, in N-The epitaxial layer 51 has an epitaxial thickness of 100nm and a doping concentration of 5X 1019cm-3Forming N is formed of the N-type GaN semiconductor material+Layer of type 52, N-Layers 51 and N+The layers 52 together form an N-type layer 5, epitaxial N+Process conditions used for the layer 52: high purity SiH at 950 deg.C, 40Torr, 4200sccm hydrogen flow4As a dopant, the flow rate of ammonia gas was 4200sccm and the flow rate of gallium source was 105. mu. mol/min.
Step e, fabricating the first gate pillar 6 and the second gate pillar 7, as shown in fig. 6 e.
Manufacturing a mask on the N-type layer 5 for the first time, and etching two sides of the N-type layer 5 by using a reactive ion etching technology to form a first gate pillar 6 and a second gate pillar 7 which are 10 micrometers in length, wherein the etching depth is 750 nm;
the etching process conditions are as follows: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 110W.
Step f. make array holes 8, as in fig. 6 f.
First, in the case of Al having a thickness of 60nm0.1Ga0.9A mask is manufactured on the N barrier layer 3, the first gate pillar 6 and the second gate pillar 7 for the second time,the mask pattern is composed of 10 × 10 side lengths k2Is an array of square holes of 2 μm with a spacing k between two adjacent holes33 μm, boundary spacing k of the outermost hole and the source electrode 9 or the drain electrode 101Is 4 μm; using the mask to etch Al by reactive ion etching0.1Ga0.9Etching and manufacturing 10 multiplied by 10 cuboid hole columns 81 on the N barrier layer 3, wherein the depth r of each hole column 81 is 20nm, and the technological conditions adopted by etching the hole columns 81 are as follows: cl2/BCl3The flow ratio was 3:1, the pressure was 30mTorr, and the power was 150W.
Then, in the presence of Al having a thickness of 60nm0.1Ga0.9And making masks on the N barrier layer 3, the first gate column 6 and the second gate column 7 for the third time, and etching and making the same rectangular pyramids 82 in the 10 × 10 rectangular hole columns 81 with the same size by using the masks by using a reactive ion etching technology, wherein the 10 × 10 rectangular hole columns 81 with the same size and the rectangular pyramids 82 at the lower parts of the rectangular hole columns form array holes 8 together. The upper surfaces of the rectangular pyramids coincide with the lower surface of the hole pillar 81, the depth e of the rectangular pyramid 81 is 35nm, the four sides are the same, and Al0.1Ga0.9The thickness of the N barrier layer 3 after etching was 5 nm. The adopted process conditions for etching the rectangular pyramid 82 are as follows: BCl3The flow rate is 60sccm, the pressure is 25mTorr, and the power is 150W.
Step g. make source 9 and drain 10, as in fig. 6 g.
First, a mask is made on the barrier layer 3, the first gate pillar 6 and the second gate pillar 7 for the fourth time, and a metal is deposited on the barrier layer 3 on the left and right sides by using an electron beam evaporation technique using the mask, and the array holes 8 are completely filled with the metal, which is Ta. The process conditions adopted for depositing the metal are as follows: high purity Ta source, vacuum degree less than 1.8X 10-3Pa, power of 420W, evaporation rate of less than
Then, continuing to use the mask made for the fourth time, depositing metal again by adopting the electron beam evaporation technology, and depositing N2Performing rapid thermal annealing in an atmosphere to form a source electrode 9 and a drain electrode 10, wherein the deposited metal is Ti/Al/Ti-The Au metal combination is Ti, Al, Ti and Au from bottom to top, and the thickness of the Au metal combination is 0.012 μm/0.136 μm/0.041 μm/0.059 μm. The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 1000W, evaporation rate less than
The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 850 ℃ and the time was 35 s.
And step H, etching the barrier layers on the left side of the source electrode 9 and the right side of the drain electrode 10 to manufacture a table-board 11, as shown in figure 6 h.
Making masks on the barrier layer 3, the first gate column 6, the second gate column 7, the source electrode 9 and the drain electrode 10 for the fifth time, and etching the barrier layers on the left side of the source electrode 9 and the right side of the drain electrode 10 by using the masks by using a reactive ion etching technology to form a table top 11 with the etching depth of 400 nm;
the etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step i. fabricate the first gate 12 and the second gate 13, as shown in fig. 6 i.
Making a mask on the barrier layer 3, the first gate column 6, the second gate column 7, the source electrode 9, the drain electrode 10 and the upper part of the table top 11 for the sixth time, depositing metal on the first gate column 6 and the second gate column 7 by using an electron beam evaporation technology by using the mask, and making a first gate electrode 12 and a second gate electrode 13, wherein the lengths of the two gate electrodes are equal and are both smaller than the length of the first gate column 6, the deposited metal is a Ti/Au metal combination, namely the lower layer is Ti, the upper layer is Au, and the thickness of the deposited metal is 0.25 mu m/0.38 mu m;
the process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 1000W, evaporation rate less than
Step j. fabricate passivation layer 14, as in fig. 6 j.
Plasma is adopted to increase the area of the upper parts of the first grid column 6, the second grid column 7, the source electrode 9, the drain electrode 10, the first grid electrode 12 and the second grid electrode 13 and the peripheral area thereofDeposition of SiO with a thickness of 1000nm by means of a strong chemical vapor deposition technique2A passivation layer 14;
the process conditions used for depositing the passivation layer 14 are: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the RF power was 100W, and the pressure was 1100 mT.
And step K, manufacturing 7 grooves, as shown in figure 6 k.
And manufacturing a mask on the passivation layer 14 for the seventh time, and etching the passivation layer 14 between the first gate pillar 6 and the second gate pillar 7 by using the mask by using a reactive ion etching technology to manufacture 7 grooves with the same depth and the same width, wherein the width a of the groove is 4 microns, and the depth d of the groove is 600 nm. The two grids 6 and 7 take the 4 th groove as a symmetry axis, and the distance b between the first grid 6 and the first groove is arranged on the left side of the symmetry axis12 μm, the first and second grooves having a spacing of c1The distance between the second groove and the third groove is c2The distance between the third groove and the fourth groove is c3And c is and c1<c2<c3(ii) a On the right side of the symmetry axis, the distance b between the second grid pillar 7 and the 1 st groove2Is 2 μm, and the interval between the 1 st groove and the 2 nd groove is i1The distance between the 2 nd groove and the 3 rd groove is i2The distance between the 3 rd groove and the 4 th groove is i3And i is1<i2<i3，c1＝i1,c2＝i2,c3＝i3。
The etching adopts the following process conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And L, manufacturing a left modulation plate, 5 independent metal blocks and a right modulation plate, as shown in FIG. 6 l.
And manufacturing a mask on the passivation layer 14 and the upper part of the 7 grooves for the eighth time, using the mask to deposit metal on the passivation layer between the first gate pillar 6 and the second gate pillar 7 and in the 7 grooves by using an electron beam evaporation technology to manufacture a left modulation plate, 5 independent metal blocks and a right modulation plate, electrically connecting the left modulation plate with the source electrode 9, electrically connecting the right modulation plate with the drain electrode 10, and electrically connecting the 5 modulation plates with the drain electrode 10The independent metal blocks are suspended in the air, the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the 3 rd independent metal block as the center to form a composite plate 15, the deposited metal is a Ti/Au metal combination, namely the lower layer is Ti, the upper layer is Au, and the thickness of the composite plate is 0.35 mu m/0.28 mu m. Wherein the deposited metal is to completely fill 7 grooves, the 3 rd independent metal block is taken as a symmetry axis, and the left side of the symmetry axis is the space S between the left modulation board and the first independent metal block10.35 μm, the spacing S of the first independent metal block and the second independent metal block20.56 μm, the spacing S of the second independent metal block and the third independent metal block30.97 μm; distance U between right modulation board and 1 st independent metal block10.35 μm, the spacing U between the 1 st and 2 nd independent metal blocks20.56 μm, the spacing U between the 2 nd and 3 rd independent metal blocks30.97 μm, the length t of the independent metal block is 5 μm, the distance between the right edge of the left modulation plate and the right edge of the first gate pillar 6 is equal to the distance between the left edge of the right modulation plate and the left edge of the second gate pillar 7, and the distance L is 6.5 μm;
the process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 1000W, evaporation rate less than
Step M. SiO is deposited in the peripheral region of the passivation layer 14 and the composite plate 152A protective layer 16 is made, as shown in fig. 6 m.
Deposition of SiO in the peripheral region of the passivation layer 14 and the composite plate 15 using plasma enhanced chemical vapor deposition techniques2To make a protective layer 16 with a thickness of 1 μm, thereby completing the fabrication of the entire device;
the process conditions adopted for depositing the protective layer are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 deg.C, the RF power was 100W, and the pressure was 1100 mTorr.
The effects of the present invention can be further illustrated by the following simulations.
First, simulation parameter
The traditional GaN-based HEMT power switch device and the device of the invention adopt the same main body structure parameters, the device of the invention adopts 7 independent metal blocks, and the length of each independent metal block is 1 mu m.
Second, simulation content
Simulation 1: transfer characteristic simulation is performed on the conventional device and the device of the present invention, and as a result, as shown in fig. 7, the first gate and the second gate in the device of the present invention are short-circuited in the simulation.
As can be seen from fig. 7, the threshold voltage of the conventional device is 1V, while the threshold voltage of the device of the present invention is 7.5V, which indicates that the threshold voltage of the device of the present invention is significantly greater than that of the conventional device.
Simulation 2: the breakdown characteristic simulation was performed on the conventional device and the device of the present invention, respectively, and the results are shown in fig. 8.
As can be seen from fig. 8, the conventional device can only achieve forward blocking, and the drain-source voltage of the device is about 265V when the device breaks down, i.e., the drain current increases rapidly, whereas the device of the present invention can achieve forward blocking and reverse blocking, and the breakdown voltage of the device during forward blocking and the breakdown voltage of the device during reverse blocking are both about 1810V, which indicates that the device of the present invention can achieve bidirectional blocking characteristics, and the breakdown voltage is much greater than that of the conventional device.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.
Claims (10)
1. A power switching device comprising, from bottom to top: the device comprises a substrate (1), a transition layer (2), a barrier layer (3) and a passivation layer (14); a table top (11) is carved on the side surface of the barrier layer (3), and a first grid column (6) and a second grid column (7) are respectively arranged on two sides of the upper part of the barrier layer (3); a first grid electrode (12) is deposited on the first grid column (6), and a source electrode (9) is deposited on the left side of the first grid column; a second grid electrode (13) is deposited on the second grid column (7), and a drain electrode (10) is deposited on the right side of the second grid electrode; array holes (8) are etched in the barrier layer (3) on the left side of the first gate column (6) and the barrier layer (3) on the right side of the second gate column (7), and the method is characterized in that:
the first grid column (6) and the second grid column (7) are cuboids with the same size and are both composed of a P-type layer (4) and an N-type layer (5);
the N-type layer (5) is composed of lower N-A layer (51) of the type and an upper N+A layer of type (52);
said N is-The layer (51) and the P-type layer (4) form PN junctions, and the PN junctions of the gate columns are the same in size;
2n +1 grooves with the same size are etched in the passivation layer (14) in the area between the first gate column (6) and the second gate column (7), and n is larger than or equal to 1; the upper part of the composite board is provided with a composite board (15);
the composite plate (15) is composed of a left modulation plate, a right modulation plate and 2n-1 independent metal blocks with the same size, the lower ends of the independent metal blocks are completely filled in 2n +1 grooves, the left modulation plate is electrically connected with the source electrode (9), the right modulation plate is electrically connected with the drain electrode (10), and the independent metal blocks are suspended mutually; the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center, and n is more than or equal to 1;
and a protective layer (16) is arranged on the periphery of the passivation layer (14) and the composite plate (15).
2. Device according to claim 1, characterized in that the source (9) and the drain (10) have a length LOAnd the width is W.
3. The device of claim 1, wherein:
the array holes (8) are composed of f multiplied by g holes with the same size, f>1，g>1, each hole is composed of an upper cuboid hole column (81) and a lower rectangular pyramid (82), and the distance k between two adjacent holes30.5 to 3 μm, the boundary distance k between the outermost hole and the source electrode (9) or the drain electrode (10)11-4 μm;
the upper surface and the lower surface of the hole column (81) are both square, and the sides of the squareLong k20.5 to 2 μm, the depth r of the hole pillar (81) is 2 to 20nm, and the lower surface of the hole pillar (81) is superposed with the upper surface of the rectangular pyramid (82);
the depth e of the rectangular pyramid (82) is 1-35 nm, and the four side faces are the same.
4. The device according to claim 1, characterized in that the grooves in the passivation layer (14) have the same size, each groove having a depth d greater than 0 μm and less than the thickness of the passivation layer (14) and a width a of 0.1 to 4 μm.
5. The device of claim 1, wherein the nth independent metal block is taken as a symmetry axis, and the left modulation plate is spaced from the first independent metal block by S on the left side of the symmetry axis1The distance between the first independent metal block and the second independent metal block is S2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Sn，S1<S2<...<Sn(ii) a On the right side of the symmetry axis, the distance between the right modulation plate and the 1 st independent metal block is U1The distance between the 1 st independent metal block and the 2 nd independent metal block is U2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Un，U1<U2<...<UnAnd S is1＝U1，S2＝U2，...，Sn＝Un，n≥1。
6. The device according to claim 1, wherein the left modulation plate, the right modulation plate and each of the independent metal blocks have the same thickness, the length t of each of the independent metal blocks is 0.5-5 μm, and the distance between the right edge of the left modulation plate and the right edge of the first gate pillar (6) is equal to the distance between the left edge of the right modulation plate and the left edge of the second gate pillar (7), and the distance is L.
7. The device of claim 1, wherein the first groove is located on the left side of the symmetry axis with respect to the (n + 1) th groove as the symmetry axisThe distance between the grid column (6) and the first groove is b1And 0 μm<b1<(L-a) the first groove is spaced from the second groove by a distance c1And so on, the distance between the nth groove and the (n + 1) th groove is cn，c1<c2<...<cn(ii) a On the right side of the symmetry axis, the distance between the second grid column (7) and the 1 st groove is b2And 0 μm<b2<(L-a) the distance between the 1 st groove and the 2 nd groove is i1By analogy, the distance between the nth groove and the (n + 1) th groove is in，i1<i2<...<inAnd b is1＝b2,c1＝i1,c2＝i2,…,cn＝in,n≥1。
8. The device of claim 1, wherein N is in the first gate pillar (6) and the second gate pillar (7)+The thickness of the layer (52) is less than N-Thickness of the layer (51), N+The doping concentration of the layer (52) is greater than or equal to N-The doping concentration of the layer (51); n is a radical of-The thickness of the type layer (51) is more than or equal to that of the P-type layer (4), the thickness of the P-type layer (4) is 5-300 nm, and N is-The doping concentration of the type layer (51) is less than or equal to that of the P type layer (4), and the lengths of the first grid (12) and the second grid (13) are equal and less than that of the first grid column (6).
9. A method of making a power switching device, comprising the steps of:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate (1) by adopting a metal organic chemical vapor deposition technology to form a transition layer (2) with the thickness of 1-10 mu m;
B) extending a GaN-based wide bandgap semiconductor material on the transition layer (2) by adopting a metal organic chemical vapor deposition technology to form a barrier layer (3) with the thickness of 4-60 nm;
C) a P-type GaN semiconductor material is epitaxially formed on the barrier layer (3) by adopting a metal organic chemical vapor deposition technology to form a GaN semiconductor layer with the thickness of 5-300 nm and the doping concentration of 5 multiplied by 1016～5×1020cm-3A P-type layer (4);
D) manufacturing an N-type layer (5):
D1) the N-type GaN semiconductor material is epitaxially formed on the P-type layer (4) by adopting the metal organic chemical vapor deposition technology, the thickness of the N-type GaN semiconductor material is more than or equal to that of the P-type layer (4), and the doping concentration is 1 multiplied by 1011～1×1018cm-3N of (A)-A layer (51);
D2) in N-The N-type GaN semiconductor material is epitaxially formed on the type layer (51) by adopting a metal organic chemical vapor deposition technology, and the thickness of the N-type GaN semiconductor material is smaller than that of the N-A layer (51) of a type having a doping concentration of 1 x 1018～5×1020cm-3N of (A)+Layer of type (52), N-Layers of type (51) and N+The layers (52) together form an N-type layer (5);
E) manufacturing a mask on the N-type layer (5) for the first time, etching the two sides of the N-type layer (5) by using the mask until the upper surface of the barrier layer (3) is etched to form a cuboid first gate pillar (6) and a cuboid second gate pillar (7) which are longer than or equal to 1nm and have the same size;
F) preparing array holes (8):
F1) making masks on the barrier layer (3), the first gate column (6) and the second gate column (7) for the second time, and etching the barrier layer (3) on the left side and the right side by using the masks to form f × g cuboid hole columns (81) with the same size;
F2) a mask is made on the barrier layer (3), the first gate column (6) and the second gate column (7) for the third time, F × g cuboid hole columns (81) with the same size and formed by F1) are etched by using the mask to form a rectangular pyramid (82) at the lower part of the hole column (81), and the F × g cuboid hole columns (81) with the same size and the rectangular pyramid (82) at the lower part of the rectangular hole columns form an array hole (8) together;
G) manufacturing a source electrode (9) and a drain electrode (10):
G1) manufacturing masks on the upper parts of the barrier layer (3), the first gate column (6) and the second gate column (7) for the fourth time, depositing metal on the barrier layer (3) on the left side and the right side by using the masks by adopting an electron beam evaporation technology, and completely filling the array holes (8), wherein the metal adopts Gd, Zr or Ta;
G2) continuing to use the mask in G1), and again using the electron beamThe metal is deposited by evaporation technique, the metal is one of Ti/Al/Ni/Au, Ti/Al/Mo/Au or Ti/Al/Ti/Au, and is in N2Carrying out rapid thermal annealing in the atmosphere to finish the manufacture of the source electrode (9) and the drain electrode (10);
H) making a mask on the barrier layer (3), the first gate column (6), the second gate column (7), the source electrode (9) and the drain electrode (10) for the fifth time, etching the barrier layer (3) on the left side of the source electrode (9) and the right side of the drain electrode (10) by using the mask, and forming a table top (11) when the depth of an etching area is greater than the thickness of the barrier layer;
I) making a mask on the barrier layer (3), the first gate column (6), the second gate column (7), the source electrode (9), the drain electrode (10) and the upper part of the table top (11) for the sixth time, depositing metal on the upper parts of the first gate column (6) and the second gate column (7) by using the mask through an electron beam evaporation technology, and making a first gate (12) and a second gate (13), wherein the lengths of the two gates are equal and are both smaller than that of the first gate column (6);
J) depositing a passivation layer (14) with the thickness of more than or equal to 100nm on the upper parts of the first gate column (6), the second gate column (7), the source electrode (9), the drain electrode (10), the first grid electrode (12), the second grid electrode (13) and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology;
K) manufacturing a mask on the passivation layer (14) for the seventh time, and etching 2n +1 grooves with the same size on the passivation layer (14) between the first gate column (6) and the second gate column (7) by using the mask, wherein n is more than or equal to 1;
l) manufacturing masks on the passivation layer (14) and the upper portion of the groove for the eighth time, depositing metal on the upper portion of the passivation layer (14) and in the groove by using an electron beam evaporation technology by using the masks, completely filling the lower end of the metal in the groove, sequentially manufacturing a left modulation plate, 2n-1 independent metal blocks and a right modulation plate, wherein n is more than or equal to 1, the left modulation plate is electrically connected with the source electrode (9), the right modulation plate is electrically connected with the drain electrode (10), the independent metal blocks are suspended from each other, and the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center to form a composite plate (15);
and M) depositing a protective layer (16) on the peripheral areas of the passivation layer (14) and the composite plate (15) by using an insulating dielectric material and adopting a plasma enhanced chemical vapor deposition technology to finish the manufacture of the whole device.
10. The method of claim 7, wherein:
the electron beam evaporation technology comprises the following process conditions: vacuum degree less than 1.8X 10-3Pa, power of 200-1000W, evaporation rate less than
The plasma enhanced chemical vapor deposition technology has the process condition N2O flow rate of 850sccm, SiH4The flow rate is 200sccm, the temperature is 250 ℃, the RF power is 20-100W, and the pressure is 1100 mT.
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| WO2023051247A1 (en) * | 2021-09-30 | 2023-04-06 | 湖南三安半导体有限责任公司 | Gallium nitride bidirectional switch device and preparation method therefor |
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