CN111863852A - Pixel structure of image sensor and forming method thereof - Google Patents
Pixel structure of image sensor and forming method thereof Download PDFInfo
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Abstract
A pixel structure of an image sensor and a forming method thereof are provided, wherein the structure comprises: the first wafer is provided with a photosensitive surface and a non-photosensitive surface which are opposite, the first wafer comprises a plurality of photosensitive areas, and each photosensitive area is provided with 1 photosensitive device; a second wafer bonded to the first wafer, the second wafer having a functional surface and a non-functional surface opposite to the functional surface, the non-photosensitive surface facing the functional surface, the second wafer including a plurality of logic regions, each photosensitive region corresponding to 1 logic region, a circuit of each logic region including 1 transfer transistor and a floating diffusion connected to the transfer transistor; the photosensitive surface is exposed out of the surface of the first silicon through hole structure, and the photosensitive device of the corresponding photosensitive area and the transmission transistor of the logic area are electrically interconnected through the first silicon through hole structure. Thus, the performance of the image sensor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a pixel structure of an image sensor and a forming method thereof.
Background
Image sensors are classified into Complementary Metal Oxide (CMOS) image sensors and Charge Coupled Device (CCD) image sensors, and are generally used to convert optical signals into corresponding electrical signals. Compared with a CCD (charge coupled device) image sensor, the CMOS image sensor has the advantages of simple process, easiness in integration with other devices, small size, light weight, low power consumption, low cost and the like. At present, CMOS image sensors are widely used in still digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.
The CMOS image sensor may be classified into a line-by-line exposure CMOS image sensor and a global exposure CMOS image sensor according to an exposure method. A CMOS image sensor of line-by-line exposure (Rolling Shutter) has the defects of moving image inclination, distortion and the like due to different starting points of line exposure time; and all pixels in a frame of image of the CMOS image sensor with global exposure start exposure at a certain moment and end exposure at another moment, and the global exposure mode can eliminate the defects of line-by-line exposure and realize image output with high frame rate.
In the global exposure mode, signals generated by the pixel array need to be read row by row. Therefore, the pixel unit is provided with a floating diffusion region and a storage node unit connected with the floating diffusion region, so that signals of each line can be read out to a back-end circuit in a time-sharing mode row by row during reading through the floating diffusion region and the storage node unit.
However, in the pixel structure of the image sensor of the global exposure, a photosensitive unit for photosensitive and a floating diffusion region for temporarily storing signals, and a storage node unit connected to the floating diffusion region are on the same substrate, and the substrate is used for both photosensitive and storing the storage node signals. When the photosensitive unit, the floating diffusion area and the storage node unit are located on the same substrate, the floating diffusion area and the storage node unit are easily affected by the photosensitive unit or external light, so that a parasitic light sensation effect is generated, the storage node unit is subjected to electric leakage due to the adverse effect, and when the pixel signal is read line by line, the pixel signal which is read later is distorted, so that the performance of the image sensor is affected.
Disclosure of Invention
The invention provides a pixel structure of an image sensor and a forming method thereof, which aims to improve the performance of the image sensor.
To solve the above technical problem, an embodiment of the present invention provides a pixel structure of an image sensor, including: the first wafer is provided with a photosensitive surface and a non-photosensitive surface which are opposite, the first wafer comprises a plurality of photosensitive areas, and each photosensitive area is provided with 1 photosensitive device; a second wafer bonded to the first wafer, the second wafer having a functional surface and a non-functional surface opposite to the functional surface, the non-photosensitive surface facing the functional surface, the second wafer including a plurality of logic regions, each photosensitive region corresponding to 1 logic region, a circuit of each logic region including 1 transfer transistor and a floating diffusion connected to the transfer transistor; the photosensitive surface is exposed out of the surface of the first silicon through hole structure, and the photosensitive device of the corresponding photosensitive area and the transmission transistor of the logic area are electrically interconnected through the first silicon through hole structure.
Optionally, each photosensitive region further has a first conductive structure electrically interconnected with the photosensitive device, each logic region further has a second conductive structure electrically interconnected with the transfer transistor, and each first tsv structure is electrically interconnected with the first conductive structure of the corresponding photosensitive region and the second conductive structure of the logic region, respectively.
Optionally, the material of the first tsv structure includes a metal material or polysilicon.
Optionally, the method further includes: a second through-silicon-via structure located within each logic area and electrically interconnected with circuitry of the logic area, and the non-functional side exposes a surface of the second through-silicon-via structure.
Optionally, the material of the second tsv structure includes a metal material or polysilicon.
Optionally, the method further includes: a metal redistribution layer on the non-functional side, the metal redistribution layer electrically interconnected with the second through-silicon via structure.
Optionally, the photosensitive device is a photodiode.
Optionally, the circuitry of each logic region further comprises storage node cells electrically interconnected with floating diffusion regions within the logic region.
Optionally, the circuit of each logic region further includes a reset transistor, a source follower, a row selection transistor, a readout circuit, a correlated double sampling circuit, a digital-to-analog conversion circuit, and an amplifier.
Optionally, the method further includes: the grid layer is positioned on the photosensitive surface, and a plurality of grid grooves are formed in the grid layer; the filter layer is positioned in the grid groove; and the micro lens is positioned on the surface of the filter layer.
Correspondingly, the technical solution of the present invention further provides a method for forming a pixel structure of the image sensor, including: forming a first wafer, wherein the first wafer is provided with a photosensitive surface and a non-photosensitive surface which are opposite, the first wafer comprises a plurality of photosensitive areas, and each photosensitive area is provided with 1 photosensitive device; forming a second wafer, wherein the second wafer is provided with a functional surface and an inactive surface which are opposite to each other, the second wafer comprises a plurality of logic areas, and a circuit of each logic area comprises 1 transmission transistor and a floating diffusion area connected with the transmission transistor; bonding a first wafer and a second wafer, wherein the non-photosensitive surface faces the functional surface, and each photosensitive area corresponds to 1 logic area; and after the first wafer and the second wafer are bonded, forming a first silicon through hole structure in each corresponding photosensitive area and logic area, wherein the photosensitive surface exposes the surface of the first silicon through hole structure, and the photosensitive devices of the corresponding photosensitive areas and the transmission transistors of the logic areas are electrically interconnected through the first silicon through hole structures.
Optionally, each photosensitive region further has a first conductive structure electrically interconnected with the photosensitive device, each logic region further has a second conductive structure electrically interconnected with the transfer transistor, and each first tsv structure is electrically interconnected with the first conductive structure of the corresponding photosensitive region and the second conductive structure of the logic region, respectively.
Optionally, the method for forming the first through silicon via structure includes: after the first wafer and the second wafer are bonded, etching the photosensitive surface, and forming a first through hole in each photosensitive area, wherein the first through hole also extends into a logic area corresponding to the photosensitive area, and the first through hole exposes the surface of the first conductive structure and the surface of the second conductive structure; forming a first dielectric film on the side wall surface of the first through hole; and forming the first through silicon via structure in the first through hole after the first dielectric film is formed.
Optionally, the method for bonding the first wafer and the second wafer includes: and after the non-photosensitive surface faces the functional surface, pressurizing and attaching the first wafer and the second wafer.
Optionally, the method for bonding the first wafer and the second wafer further includes: and after the first wafer and the second wafer are pressed and attached, annealing the first wafer and the second wafer.
Optionally, the circuitry of each logic region further comprises storage node cells electrically interconnected with floating diffusion regions within the logic region.
Optionally, the method further includes: after the first wafer and the second wafer are bonded, before the first through silicon via structure is formed, the photosensitive surface of the first wafer is thinned.
Optionally, the method further includes: after bonding the first wafer and the second wafer, forming a second through silicon via structure electrically interconnected with the circuit of the logic area in each logic area, and exposing the surface of the second through silicon via structure by the non-functional surface.
Optionally, the method further includes: after forming the second through-silicon-via structure, forming a metal redistribution layer on the non-functional side, the metal redistribution layer being electrically interconnected with the second through-silicon-via structure.
Optionally, the method further includes: after the first through silicon via structure is formed, a grid layer is formed on the light sensing surface, and a plurality of grid grooves are formed in the grid layer; forming a filter layer in the grid groove; and forming a micro lens on the surface of the filter layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the pixel structure of the image sensor provided by the technical scheme of the invention comprises a first wafer and a second wafer which are bonded, wherein the first wafer comprises a plurality of photosensitive areas, each photosensitive area is internally provided with 1 photosensitive device, the second wafer comprises a plurality of logic areas, a circuit of each logic area comprises a floating diffusion area, and each photosensitive area corresponds to 1 logic area, so that the photosensitive devices of the corresponding photosensitive areas and the floating diffusion areas of the logic areas are respectively positioned in different wafers, the influence of the photosensitive units and the external light rays on the floating diffusion areas is reduced, the generation of parasitic photosensitive effect is reduced, and the performance of the finally formed image sensor is further improved. Specifically, since the circuit of each logic region includes 1 transfer transistor and a floating diffusion connected to the transfer transistor, and the pixel structure further includes a first through-silicon-via structure located in each corresponding photosensitive region and logic region, and the photosensitive device of the corresponding photosensitive region and the transfer transistor of the logic region are electrically interconnected through the first through-silicon-via structure, it is possible to control conduction or disconnection between the floating diffusion and the photosensitive device through the transfer transistor, and form an overall pixel structure. In the pixel structure, the photosensitive device is positioned in the first wafer, and the floating diffusion region is positioned in the second wafer, so that the photosensitive device and the floating diffusion region are respectively positioned in different wafers to isolate the photosensitive device and the floating diffusion region, and therefore, when signals are read line by line, the influence of the photosensitive device and external light on the floating diffusion region is reduced, the generation of parasitic light sensation effect is reduced, and the performance of the finally formed image sensor is improved.
Drawings
Fig. 1 to 9 are schematic structural diagrams illustrating a process of forming a pixel structure of an image sensor according to an embodiment of the invention.
Detailed Description
As described in the background, in the pixel structure of the globally exposed image sensor, the light sensing unit for sensing light and the floating diffusion region for temporarily storing signals, and the storage node unit connected to the floating diffusion region are on the same substrate, and the substrate is used for both sensing light and storing the storage node signals. When the photosensitive unit, the floating diffusion area and the storage node unit are located on the same substrate, the floating diffusion area and the storage node unit are easily affected by the photosensitive unit or external light, so that a parasitic light sensation effect is generated, the storage node unit is subjected to electric leakage due to the adverse effect, and when the pixel signal is read line by line, the pixel signal which is read later is distorted, so that the performance of the image sensor is affected.
In order to solve the above problems, the technical solution of the present invention provides a pixel structure of an image sensor, in which a photosensitive device is located in a first wafer, and a floating diffusion region is located in a second wafer, so that the influence of the photosensitive device and external light on the floating diffusion region when reading signals line by line is reduced, the generation of a parasitic light sensing effect is reduced, and the performance of the finally formed image sensor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 9 are schematic structural diagrams illustrating a process of forming a pixel structure of an image sensor according to an embodiment of the invention.
Referring to fig. 1 and 2, fig. 2 is a schematic circuit diagram of each photosensitive area of the first wafer in fig. 1, forming a first wafer 100, where the first wafer 100 has a photosensitive surface 101 and a non-photosensitive surface 102 opposite to each other, and the first wafer 100 includes a plurality of photosensitive areas a, and each photosensitive area a has 1 photosensitive device 110 therein.
In the present embodiment, the first wafer 100 includes a first substrate (not shown), and a first insulating layer (not shown) on the first substrate, the non-photosensitive surface 102 is a top surface of the first insulating layer, and the photosensitive surface 101 is a bottom surface of the first substrate.
The material of the first substrate comprises silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide. In this embodiment, the material of the first substrate is silicon.
In the present embodiment, each photosensitive region a further has a first conductive structure 120 electrically interconnected with the photosensitive device 110.
In this embodiment, the photosensitive device 110 is directly connected to the first conductive structure 120. Therefore, the interference of the signal in the process of transmitting the signal by the photosensitive device 110 is reduced, and the accuracy of the transmitted signal is improved.
In other embodiments, the photosensitive device is indirectly connected with the first conductive structure through other conductive structures.
In the present embodiment, the light sensing device 110 includes a photodiode PD.
In the present embodiment, the material of the first conductive structure 120 includes a metal material, such as copper, tungsten, aluminum, silver, and the like.
In this embodiment, the photosensitive regions a are arranged in an array.
Note that the capacitance Cs in fig. 2 is a parasitic capacitance.
Referring to fig. 3 and 4, fig. 4 is a schematic circuit diagram of each logic area of the second wafer in fig. 3, forming a second wafer 200, where the second wafer 200 has a functional surface 201 and an inactive surface 202 opposite to each other, and the second wafer 200 includes a plurality of logic areas B.
In the present embodiment, the second wafer 200 includes a second substrate (not shown), and a second insulating layer (not shown) on the second substrate, the functional surface 201 is a top surface of the first insulating layer, and the non-functional surface 202 is a bottom surface of the second substrate.
The material of the second substrate comprises silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide. In this embodiment, the material of the second substrate is silicon.
In the present embodiment, the circuit 210 of each logic region B includes 1 transfer transistor TX, and a floating diffusion FD connected to the transfer transistor TX.
Specifically, in the present embodiment, the transfer transistor TX includes a source doped region (not shown) and a drain doped region (not shown), and the floating diffusion FD is one of the source doped region or the drain doped region of the transfer transistor TX.
In this embodiment, each logic region B also has a second conductive structure 220 electrically interconnected with the transmission transistor TX.
In the present embodiment, the transmission transistor TX is directly connected to the second conductive structure 220. Therefore, the interference of the signal in the process of transmitting the signal by the photosensitive device 110 is reduced, and the accuracy of the transmitted signal is improved.
In other embodiments, the pass transistor is indirectly connected to the second conductive structure through another conductive structure.
In the present embodiment, the material of the second conductive structure 220 includes a metal material, such as copper, tungsten, aluminum, silver, and the like.
In this embodiment, the logic areas B are arranged in an array.
In this embodiment, the circuit 210 of each logic region B further includes: a storage node unit electrically interconnected with the floating diffusion region FD in the logic region B.
In the present embodiment, the storage node unit includes a storage capacitor CL.
In the present embodiment, the circuit 210 of each logic region B further includes a reset transistor RST, a source follower SF, a row select transistor SEL, and a readout circuit RDOutA correlated double sampling circuit CDS, a digital-to-analog conversion circuit ADC and an amplifier AMP.
Referring to fig. 5, the first wafer 100 and the second wafer 200 are bonded, the non-photosensitive surface 102 faces the functional surface 201, and each photosensitive area a corresponds to 1 logic area B.
Specifically, in the present embodiment, the projection of each photosensitive area a on the surface of the first substrate coincides with the projection of the corresponding logic area B on the surface of the first substrate. Therefore, in a direction perpendicular to the surface of the first substrate, the corresponding photosensitive area a and the logic area B can overlap, so that the utilization rate of the areas of the first wafer 100 and the second wafer 200 can be improved, and the integration level of the pixel structure of the image sensor can be improved.
In other embodiments, the projection of each photosensitive region on the first substrate surface is overlapped or not overlapped with the projection part of the corresponding logic region on the first substrate surface, and the integration level of the pixel structure of the image sensor is reduced along with the reduction of the overlapped part.
In this embodiment, the method for bonding the first wafer 100 and the second wafer 200 includes: after the non-photosensitive surface 102 is faced to the functional surface 201, the first wafer 100 and the second wafer 200 are pressed and bonded.
In this embodiment, the method for bonding the first wafer 100 and the second wafer 200 further includes: after the first wafer 100 and the second wafer 200 are bonded by pressing, the first wafer 100 and the second wafer 200 are annealed.
The parameters of the annealing treatment comprise: the annealing temperature range is 80-350 ℃, and the annealing time is 30-120 min.
In this embodiment, before the first wafer 100 and the second wafer 200 are bonded, the adhesive layer 300 is formed on the non-photosensitive surface 102 of the first wafer 100, so that the reliability of the bonding between the first wafer 100 and the second wafer 200 can be improved.
In other embodiments, an adhesive layer is formed on the functional surface of the second wafer before bonding the first wafer and the second wafer.
In other embodiments, the adhesive layer is not formed.
Referring to fig. 6 and 7, fig. 7 is a schematic circuit diagram illustrating a circuit structure of 1 photosensitive area and 1 corresponding logic area after the first tsv structure is formed in fig. 6, after the first wafer 100 and the second wafer 200 are bonded, a first tsv structure 130 is formed in each corresponding photosensitive area a and logic area B, the photosensitive surface 101 exposes the surface of the first tsv structure 130, and the photosensitive devices 110 in the corresponding photosensitive areas a and the transmission transistors TX in the logic areas B are electrically interconnected through the first tsv structure 130.
Specifically, in the present embodiment, each of the first through silicon via structures 130 is electrically interconnected with the corresponding first conductive structure 120 of the photosensitive area a and the second conductive structure 220 of the logic area B. Accordingly, the light sensing device 110 of the corresponding light sensing region a and the transfer transistor TX of the logic region B can be electrically interconnected through the first through-silicon-via structure 130.
In this embodiment, the method for forming the first through-silicon-via structure 130 includes: after the first wafer 100 and the second wafer 200 are bonded, etching the photosensitive surface 101, and forming a first through hole (not shown) in each photosensitive area a, where the first through hole further extends into the logic area B corresponding to the photosensitive area a, and the first through hole exposes the surface of the first conductive structure 120 and the surface of the second conductive structure 220; forming a first dielectric film (not shown) on a sidewall surface of the first via hole; after the first dielectric film is formed, filling the material of the first through silicon via structure 130 in the first through hole, and forming the first through silicon via structure 130.
The process for forming the first through hole comprises at least 1 of a dry etching process or a wet etching process.
The process of filling the material of the first through-silicon-via structure 130 includes: at least 1 of a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, an epitaxial growth process, or a metal plating process.
In this embodiment, the material of the first tsv structure 130 includes a metal material, such as copper, aluminum, tungsten, gold, or silver, or polysilicon, which may be single polysilicon, or polysilicon doped with other ions.
In this embodiment, after the first wafer 100 and the second wafer 200 are bonded, and before the first through silicon via structure 130 is formed, the photosensitive surface 101 of the first wafer 100 is thinned.
The thickness of the thinned first wafer 100 is 2 μm to 20 μm.
By thinning the photosensitive surface 101, the light can better irradiate the photosensitive device 110, so that photons are more fully converted into electrons and holes; in addition, the thinned first wafer 100 is beneficial to improving heat dissipation, and meanwhile, the size and the dimension of the first wafer 100 are reduced, so that the packaging requirement is facilitated.
Referring to fig. 8, after the first wafer 100 and the second wafer 200 are bonded, a second tsv structure 230 electrically interconnected with the circuits 210 of the logic area B is formed in each logic area B, and the non-functional surface 202 exposes a surface of the second tsv structure 230.
Specifically, in the present embodiment, the second through silicon via structure 230 is connected to the second conductive structure 220, so that the second through silicon via structure 230 is electrically interconnected with the circuit 210 of the logic region B.
In this embodiment, the method for forming the second through silicon via structure 230 includes: after the first tsv structures 130 are formed, the non-functional surface 202 is etched, and second vias (not shown) are formed in each logic area B, wherein the second vias expose the surfaces of the second conductive structures 220; forming a second dielectric film (not shown) on a sidewall surface of the second via hole; after the second dielectric film is formed, the second through hole is filled with a material of the second through hole structure 230, and the second through hole structure 230 is formed.
In this embodiment, since the second tsv structure 230 is formed after the first tsv structure 130 is formed, the time that the surface of the second tsv structure 230 is exposed in the air before the subsequent formation of the metal redistribution layer is reduced, and the oxidation degree of the surface of the second tsv structure 230 is reduced, so that the contact resistance between the metal redistribution layer and the second tsv structure 230 can be reduced, and the performance and reliability of the pixel structure of the image sensor are improved.
The process for forming the second through hole comprises at least 1 of a dry etching process or a wet etching process.
The process of filling the material of the second through-silicon-via structure 230 includes: at least 1 of a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, an epitaxial growth process, or a metal plating process.
In this embodiment, the material of the second tsv structure 230 includes a metal material such as copper, aluminum, tungsten, gold, or silver, or a polysilicon, which may be a single polysilicon, or a polysilicon doped with other ions.
In other embodiments, the second through silicon via structure may also be formed after bonding the first wafer and the second wafer and before forming the first through silicon via structure.
Referring to fig. 9, after forming the second tsv structure 230, a metal redistribution layer 240 is formed on the non-functional side 202, wherein the metal redistribution layer 240 is electrically interconnected with the second tsv structure 230.
In this embodiment, a method of forming the metal redistribution layer 240 includes: forming a layer of metal redistribution material (not shown) on the non-functional side 202; patterning the metal redistribution layer to form the metal redistribution layer 240, wherein the metal redistribution layer 240 covers the surface of the second through-silicon-via structure 230.
In this embodiment, the process of forming the metal redistribution material layer includes: at least 1 of a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, an epitaxial growth process, or a metal plating process.
In this embodiment, the process of patterning the metal redistribution layer includes one of a dry etching process and a wet etching process.
In this embodiment, the method for forming the pixel structure of the image sensor further includes: after the metal redistribution layer 240 is formed, a grid layer (not shown) having grid grooves (not shown) therein is formed on the photosensitive surface 101; forming a filter layer (not shown) in the grid groove; microlenses (not shown) are formed on the surface of the filter layer.
Accordingly, the technical solution of the present invention further provides a pixel structure of an image sensor formed by the above method, please refer to fig. 7 and fig. 9, including: a first wafer 100, where the first wafer 100 has a photosensitive surface 101 and a non-photosensitive surface 102 opposite to each other, and the first wafer 100 includes a plurality of photosensitive areas a, and each photosensitive area a has 1 photosensitive device 110 therein; a second wafer 200 bonded to the first wafer 100, the second wafer 200 having a functional surface 201 and a non-functional surface 202 opposite to each other, the non-photosensitive surface 102 facing the functional surface 201, the second wafer 200 including a plurality of logic regions B, each photosensitive region a corresponding to 1 logic region B, a circuit 210 of each logic region B including 1 transfer transistor TX and a floating diffusion FD connected to the transfer transistor TX; the first tsv structures 130 are located in each corresponding photosensitive area a and logic area B, the photosensitive surface 101 exposes the surface of the first tsv structure 130, and the photosensitive devices 110 of the corresponding photosensitive areas a and the transmission transistors TX of the logic areas B are electrically interconnected through the first tsv structures 130.
Because the first wafer 100 and the second wafer 200 are bonded, the first wafer 100 includes a plurality of photosensitive areas a, each photosensitive area a has 1 photosensitive device 110 therein, the second wafer 200 includes a plurality of logic areas B, the circuit 210 of each logic area B includes a floating diffusion FD, and each photosensitive area a corresponds to 1 logic area B, so that the photosensitive devices 110 of the corresponding photosensitive areas a and the floating diffusion FD of the logic areas B are respectively located in different wafer substrates, the influence of the photosensitive units 110 and the external light on the floating diffusion FD is reduced, the generation of parasitic light sensing effect is reduced, and the performance of the finally formed image sensor is further improved.
Specifically, since the circuit 210 of each logic region B includes 1 transfer transistor TX and a floating diffusion FD connected to the transfer transistor TX, and the pixel structure of the image sensor further includes a first through-silicon-via structure 130 located in each corresponding photosensitive region a and logic region B, and the photosensitive device 110 of the corresponding photosensitive region a and the transfer transistor TX of the logic region B are electrically interconnected through the first through-silicon-via structure 130, it is possible to control the conduction or disconnection between the floating diffusion FD and the photosensitive device 110 through the transfer transistor TX and form the entire pixel structure. In the pixel structure, the photosensitive device 110 is located in the first wafer 100, and the floating diffusion region FD is located in the second wafer 200, so that the photosensitive device 110 and the floating diffusion region FD are respectively located in different wafers to isolate the photosensitive device 110 from the floating diffusion region FD, thereby reducing the influence of the photosensitive device 110 and external light on the floating diffusion region FD when reading signals line by line, reducing the generation of parasitic light sensing effect, and further improving the performance of the finally formed image sensor.
In the present embodiment, the first wafer 100 includes a first substrate (not shown), and a first insulating layer (not shown) on the first substrate, the non-photosensitive surface 102 is a top surface of the first insulating layer, and the photosensitive surface 101 is a bottom surface of the first substrate.
The material of the first substrate comprises silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide. In this embodiment, the material of the first substrate is silicon.
In the present embodiment, each photosensitive region a further has a first conductive structure 120 electrically interconnected with the photosensitive device 110.
In this embodiment, the photosensitive device 110 is directly connected to the first conductive structure 120. Therefore, the interference of the signal in the process of transmitting the signal by the photosensitive device 110 is reduced, and the accuracy of the transmitted signal is improved.
In other embodiments, the photosensitive device is indirectly connected with the first conductive structure through other conductive structures.
In the present embodiment, the light sensing device 110 includes a photodiode PD.
In the present embodiment, the material of the first conductive structure 120 includes a metal material, such as copper, tungsten, aluminum, silver, and the like.
In this embodiment, the photosensitive regions a are arranged in an array.
In the present embodiment, the thickness of the first wafer 100 is 2 μm to 20 μm.
In the present embodiment, the second wafer 200 includes a second substrate (not shown), and a second insulating layer (not shown) on the second substrate, the functional surface 201 is a top surface of the first insulating layer, and the non-functional surface 202 is a bottom surface of the second substrate.
The material of the second substrate comprises silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide. In this embodiment, the material of the second substrate is silicon.
In the present embodiment, the circuit 210 of each logic region B includes 1 transfer transistor TX, and a floating diffusion FD connected to the transfer transistor TX.
Specifically, in the present embodiment, the transfer transistor TX includes a source doped region (not shown) and a drain doped region (not shown), and the floating diffusion FD is one of the source doped region or the drain doped region of the transfer transistor TX.
In this embodiment, each logic region B also has a second conductive structure 220 electrically interconnected with the transmission transistor TX.
Specifically, in the present embodiment, each of the first through silicon via structures 130 is electrically interconnected with the corresponding first conductive structure 120 of the photosensitive area a and the second conductive structure 220 of the logic area B. Accordingly, the light sensing device 110 of the corresponding light sensing region a and the transfer transistor TX of the logic region B can be electrically interconnected through the first through-silicon-via structure 130.
In the present embodiment, the transmission transistor TX is directly connected to the second conductive structure 220. Therefore, the interference of the signal in the process of transmitting the signal by the photosensitive device 110 is reduced, and the accuracy of the transmitted signal is improved.
In other embodiments, the pass transistor is indirectly connected to the second conductive structure through another conductive structure.
In the present embodiment, the material of the second conductive structure 220 includes a metal material, such as copper, tungsten, aluminum, silver, and the like.
In this embodiment, the logic areas B are arranged in an array.
In this embodiment, the circuit 210 of each logic region B further includes: a storage node unit electrically interconnected with the floating diffusion region FD in the logic region B.
In the present embodiment, the storage node unit includes a storage capacitor CL.
In the present embodiment, the circuit 210 of each logic region B further includes a reset transistor RST, a source follower SF, a row select transistor SEL, and a readout circuit RDOutA correlated double sampling circuit CDS, a digital-to-analog conversion circuit ADC and an amplifier AMP.
In this embodiment, the projection of each photosensitive area a on the surface of the first substrate coincides with the projection of the corresponding logic area B on the surface of the first substrate. Therefore, in a direction perpendicular to the surface of the first substrate, the corresponding photosensitive area a and the logic area B can overlap, so that the utilization rate of the areas of the first wafer 100 and the second wafer 200 can be improved, and the integration level of the pixel structure of the image sensor can be improved.
In other embodiments, the projection of each photosensitive region on the first substrate surface is overlapped or not overlapped with the projection part of the corresponding logic region on the first substrate surface, and the integration level of the pixel structure of the image sensor is reduced along with the reduction of the overlapped part.
In this embodiment, an adhesion layer 300 is further disposed between the first wafer 100 and the second wafer 200. Accordingly, the reliability of the bonding between the first wafer 100 and the second wafer 200 can be improved.
In other embodiments, the adhesive layer is absent.
In the present embodiment, each logic region B further has a second tsv structure 230 therein, and the second tsv structure 230 is electrically interconnected with the circuits 210 of the logic region B, and the non-functional surface 202 exposes the surface of the second tsv structure 230.
Specifically, in the present embodiment, the second through silicon via structure 230 is connected to the second conductive structure 220, so that the second through silicon via structure 230 is electrically interconnected with the circuit 210 of the logic region B.
In this embodiment, the material of the first tsv structure 130 includes a metal material, such as copper, aluminum, tungsten, gold, or silver, or polysilicon, which may be single polysilicon, or polysilicon doped with other ions.
In this embodiment, the material of the second tsv structure 230 includes a metal material such as copper, aluminum, tungsten, gold, or silver, or a polysilicon, which may be a single polysilicon, or a polysilicon doped with other ions.
In this embodiment, a metal redistribution layer 240 is further disposed on the non-functional surface 202, and the metal redistribution layer 240 is electrically interconnected with the second tsv structure 230.
Specifically, in the present embodiment, the metal redistribution layer 240 covers the surface of the second tsv structure 230, that is, the metal redistribution layer 240 is connected to the second tsv structure 230.
In this embodiment, the pixel structure of the image sensor further includes: a grid layer (not shown) on the photosensitive surface 101, the grid layer having grid grooves (not shown) therein; a filter layer (not shown) located in the grid groove; a microlens (not shown) on the surface of the filter layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A pixel structure of an image sensor, comprising:
the first wafer is provided with a photosensitive surface and a non-photosensitive surface which are opposite, the first wafer comprises a plurality of photosensitive areas, and each photosensitive area is provided with 1 photosensitive device;
a second wafer bonded to the first wafer, the second wafer having a functional surface and a non-functional surface opposite to the functional surface, the non-photosensitive surface facing the functional surface, the second wafer including a plurality of logic regions, each photosensitive region corresponding to 1 logic region, a circuit of each logic region including 1 transfer transistor and a floating diffusion connected to the transfer transistor;
the photosensitive surface is exposed out of the surface of the first silicon through hole structure, and the photosensitive device of the corresponding photosensitive area and the transmission transistor of the logic area are electrically interconnected through the first silicon through hole structure.
2. The image sensor pixel structure of claim 1, further comprising a first conductive structure in each photosensitive region electrically interconnecting the photosensitive devices, and a second conductive structure in each logic region electrically interconnecting the transfer transistors, wherein each first through silicon via structure is electrically interconnected with the first conductive structure of the corresponding photosensitive region and the second conductive structure of the logic region, respectively.
3. The pixel structure of claim 2, wherein the material of the first through silicon via structure comprises a metal material or polysilicon.
4. The pixel structure of an image sensor as claimed in claim 1, further comprising: a second through-silicon-via structure located within each logic area and electrically interconnected with circuitry of the logic area, and the non-functional side exposes a surface of the second through-silicon-via structure.
5. The image sensor pixel structure of claim 4, wherein the second through silicon via structure comprises a metal material or polysilicon.
6. The pixel structure of an image sensor of claim 4, further comprising: a metal redistribution layer on the non-functional side, the metal redistribution layer electrically interconnected with the second through-silicon via structure.
7. The pixel structure of claim 1, wherein said light sensing device is a photodiode.
8. The image sensor pixel structure of claim 1, wherein the circuitry of each logic region further comprises storage node cells electrically interconnected to floating diffusion regions within the logic region.
9. The image sensor pixel structure of claim 8, wherein the circuitry of each logic region further comprises a reset transistor, a source follower, a row select transistor, a readout circuit, an associated double sampling circuit, a digital-to-analog conversion circuit, and an amplifier.
10. The pixel structure of an image sensor as claimed in claim 1, further comprising: the grid layer is positioned on the photosensitive surface, and a plurality of grid grooves are formed in the grid layer; the filter layer is positioned in the grid groove; and the micro lens is positioned on the surface of the filter layer.
11. A method for forming a pixel structure of an image sensor, comprising:
forming a first wafer, wherein the first wafer is provided with a photosensitive surface and a non-photosensitive surface which are opposite, the first wafer comprises a plurality of photosensitive areas, and each photosensitive area is provided with 1 photosensitive device;
forming a second wafer, wherein the second wafer is provided with a functional surface and an inactive surface which are opposite to each other, the second wafer comprises a plurality of logic areas, and a circuit of each logic area comprises 1 transmission transistor and a floating diffusion area connected with the transmission transistor;
bonding a first wafer and a second wafer, wherein the non-photosensitive surface faces the functional surface, and each photosensitive area corresponds to 1 logic area;
and after the first wafer and the second wafer are bonded, forming a first silicon through hole structure in each corresponding photosensitive area and logic area, wherein the photosensitive surface exposes the surface of the first silicon through hole structure, and the photosensitive devices of the corresponding photosensitive areas and the transmission transistors of the logic areas are electrically interconnected through the first silicon through hole structures.
12. The method of claim 11, further comprising electrically interconnecting a first conductive structure of the photosensitive device in each photosensitive region, electrically interconnecting a second conductive structure of the transfer transistor in each logic region, and electrically interconnecting the first conductive structure of the corresponding photosensitive region and the second conductive structure of the logic region.
13. The method of forming a pixel structure of an image sensor of claim 12, wherein forming the first through-silicon-via structure comprises: after the first wafer and the second wafer are bonded, etching the photosensitive surface, and forming a first through hole in each photosensitive area, wherein the first through hole also extends into a logic area corresponding to the photosensitive area, and the first through hole exposes the surface of the first conductive structure and the surface of the second conductive structure; forming a first dielectric film on the side wall surface of the first through hole; and forming the first through silicon via structure in the first through hole after the first dielectric film is formed.
14. The method of claim 11, wherein bonding the first wafer to the second wafer comprises: and after the non-photosensitive surface faces the functional surface, pressurizing and attaching the first wafer and the second wafer.
15. The method of claim 12, wherein bonding the first wafer to the second wafer further comprises: and after the first wafer and the second wafer are pressed and attached, annealing the first wafer and the second wafer.
16. The image sensor pixel structure of claim 11, wherein the circuitry of each logic region further comprises storage node cells electrically interconnected to floating diffusion regions within the logic region.
17. The method of forming a pixel structure of an image sensor as claimed in claim 11, further comprising: after the first wafer and the second wafer are bonded, before the first through silicon via structure is formed, the photosensitive surface of the first wafer is thinned.
18. The method of forming a pixel structure of an image sensor as claimed in claim 11, further comprising: after bonding the first wafer and the second wafer, forming a second through silicon via structure electrically interconnected with the circuit of the logic area in each logic area, and exposing the surface of the second through silicon via structure by the non-functional surface.
19. The method of forming a pixel structure of an image sensor of claim 18, further comprising: after forming the second through-silicon-via structure, forming a metal redistribution layer on the non-functional side, the metal redistribution layer being electrically interconnected with the second through-silicon-via structure.
20. The method of forming a pixel structure of an image sensor as claimed in claim 11, further comprising: after the first through silicon via structure is formed, a grid layer is formed on the light sensing surface, and a plurality of grid grooves are formed in the grid layer; forming a filter layer in the grid groove; and forming a micro lens on the surface of the filter layer.
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