CN111863796A - Semiconductor packaging device - Google Patents
Semiconductor packaging device Download PDFInfo
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- CN111863796A CN111863796A CN202010740347.5A CN202010740347A CN111863796A CN 111863796 A CN111863796 A CN 111863796A CN 202010740347 A CN202010740347 A CN 202010740347A CN 111863796 A CN111863796 A CN 111863796A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 238000000465 moulding Methods 0.000 claims description 28
- 150000001875 compounds Chemical class 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 18
- 238000002161 passivation Methods 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application discloses semiconductor package device, this semiconductor package device includes: the packaging structure comprises a substrate, a plurality of first packaging elements and an electric connector, wherein the plurality of first packaging elements are stacked on the substrate and comprise at least one main chip and an electric connecting structure, and the electric connecting structure is electrically connected with a bonding pad on a functional surface of the main chip and is provided with an exposed part positioned on the side surface of the first packaging element; the electric connecting piece is positioned on the side surfaces of the plurality of first packaging elements which are arranged in a stacked mode and is electrically connected with the electric connecting structures positioned on the side surfaces of the plurality of first packaging elements and the substrate. Through the mode, the occupied space after the main chip is stacked can be reduced, and the reliability of connection between the main chip and the substrate is improved.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor package device.
Background
With the upgrading of electronic products, the functions of the electronic products are increasingly required to be diversified and the volume of the electronic products is required to be more compact, so that the volume of stacked chips needs to be compressed as much as possible in a stacking manner capable of realizing the non-functional chips.
In the prior art, a through hole is usually formed in stacked main chips in a semiconductor package device, and a conductive material is filled in the through hole to interconnect the main chips and a substrate; or the main chips in the semiconductor packaging device are arranged in a staggered and stacked mode, the upper main chip does not completely cover the lower main chip so that the bonding pads of the main chips are exposed, and bonding wires are arranged between the bonding pads of the main chips and between the bonding pads of the main chips close to the substrate and the substrate so that the main chips and the substrate are interconnected.
The inventor of the application finds that in the existing semiconductor packaging device, the structural strength of the main chip provided with the through hole is poor, the occupied volume of the staggered and laminated main chip is large, the joint of the bonding wire is weak, and the requirements of small volume and reliable connection are difficult to meet.
Disclosure of Invention
The technical problem that this application mainly solved provides a semiconductor package device, can reduce the occupied space after the main chip piles up and improve the reliability that main chip and base plate are connected.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor package device including: the package structure comprises a substrate, a plurality of first package elements and an electric connector. The first packaging elements are stacked on the substrate and comprise at least one main chip and an electric connection structure, and the electric connection structure is electrically connected with bonding pads on the functional surface of the main chip and provided with an exposed part positioned on the side surface of the first packaging element; and the electric connector is positioned on the side surfaces of the plurality of first packaging elements which are arranged in a stacked mode and is electrically connected with the electric connection structures positioned on the side surfaces of the plurality of first packaging elements and the substrate.
Wherein the first package element further comprises: the first plastic packaging layer and the first insulating layer are positioned on one side of the functional surface of the main chip, the first insulating layer is far away from the main chip relative to the first plastic packaging layer, and at least part of the electric connection structure is positioned between the first plastic packaging layer and the first insulating layer; wherein at least a portion of the electrical connection structure located at the side of the first package element is exposed from the first molding compound layer and the first insulating layer.
Wherein all the electrical connection structures are positioned between the first plastic package layer and the first insulating layer, and the side surfaces of the electrical connection structures are flush with the side surfaces of the first plastic package layer and the first insulating layer; or, a part of the electrical connection structure is located between the first plastic package layer and the first insulating layer, the rest of the electrical connection structure covers the side surface of the first plastic package layer, and the rest of the electrical connection structure is flush with the side surface of the first insulating layer.
The electrical connection piece is a strip-shaped hard conductive piece, a first conductive part electrically connected with the electrical connection structure is arranged on one side, close to the first packaging elements, of the electrical connection piece, and a second conductive part electrically connected with the substrate is arranged on one side, facing the substrate, of the electrical connection piece; wherein the first conductive portion and the second conductive portion are electrically connected.
A groove is formed in the position, corresponding to the electric connecting piece, of the substrate, at least part of the electric connecting piece is located in the groove, and the side faces of the first packaging elements are flush with the side walls of the groove; or the surface of the substrate provided with the plurality of first packaging elements is flat.
When the substrate is provided with the groove, a part of the electric connector, which is located in the groove, is provided with a conductive hole, the extending direction of the conductive hole is not parallel to the stacking direction of the plurality of first packaging elements, and one end of the conductive hole is electrically connected with an exposed part of a circuit in the substrate at a corresponding position from the groove.
The electric connecting piece is an L-shaped or Z-shaped flexible conductive piece, and comprises a first connecting part and a second connecting part extending from the first connecting part in a non-parallel mode, the first connecting part is electrically connected with the electric connecting structures on the side faces of the plurality of first packaging elements, and the second connecting part is electrically connected with the substrate.
Wherein the substrate is provided with a flat surface of the plurality of first package elements.
Wherein the semiconductor package device further comprises: and the logic chip is positioned on one side of the substrate, which is provided with the plurality of first packaging elements, and is electrically connected with the circuit in the substrate.
The electric connecting piece is an L-shaped silicon bridge, a groove is formed in the position, corresponding to the electric connecting piece, of the substrate, and one end of the electric connecting piece is located in the groove; the semiconductor package device further includes: and the logic chip is positioned on one side of the substrate, on which the plurality of first packaging elements are arranged, and bridged on one end of the electric connector and the substrate adjacent to the groove, and the logic chip is electrically connected with the electric connector and the substrate.
The beneficial effect of this application is: the electrical connection structure on the first package element in the present application is exposed from the side surface of the first package element, and the electrical connection structure is electrically connected to the pads on the functional surface, and the electrical connectors are electrically connected to the electrical connection structures on the side surfaces of the plurality of first package elements and the substrate, so as to interconnect the plurality of main chips and the substrate. The first packaging elements are stacked in a stacking mode and are not staggered, so that the transverse space is saved, the overall size is reduced, holes are not punched in the main chip, the yield and the reliability of the main chip are improved, the side faces of the first packaging elements stacked mutually are connected with each other through the electric connecting pieces and are connected with the substrate, the connection is firmer, and the reliability is higher.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of a semiconductor package device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of one embodiment of the first package component of FIG. 1;
FIG. 3 is a schematic flow chart diagram of one embodiment of forming the first package component of FIG. 2;
FIG. 4 is a flowchart illustrating an embodiment corresponding to step S101 in FIG. 3;
FIG. 5a is a schematic cross-sectional view of an embodiment corresponding to step S201 in FIG. 4;
FIG. 5b is a schematic cross-sectional view of an embodiment corresponding to step S202 in FIG. 4;
FIG. 5c is a schematic cross-sectional view of an embodiment corresponding to step S203 in FIG. 4;
FIG. 5d is a schematic cross-sectional view of an embodiment corresponding to step S204 in FIG. 4;
FIG. 6 is a schematic cross-sectional view of an embodiment corresponding to step S102 in FIG. 3;
FIG. 7 is a schematic cross-sectional view of one embodiment after step S102 in FIG. 3;
FIG. 8 is a schematic structural diagram of another embodiment of the first package component of FIG. 1;
FIG. 9 is a schematic structural diagram of yet another embodiment of the first package component of FIG. 1;
FIG. 10 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application;
FIG. 11 is a schematic structural diagram of yet another embodiment of a semiconductor package device of the present application;
fig. 12 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of an embodiment of a semiconductor package device of the present application, and fig. 2 is a schematic structural diagram of an embodiment of a first package component in fig. 1, where the semiconductor package device 20 includes: a substrate 202, a plurality of first package elements 10 and electrical connections 204. The plurality of first package elements 10 are stacked on the substrate 202, each first package element 10 includes at least one main chip 100 and an electrical connection structure 104, and the electrical connection structure 104 is electrically connected to a pad 1000 on a functional surface of the main chip 100 and has an exposed portion located on a side surface of the first package element 10. In addition, the electrical connector 204 is located at a side of the stacked first package elements 10, and is electrically connected to the electrical connection structure 104 and the substrate 202 located at the side of the first package elements 10.
Further, the first package component 10 is stacked on the substrate 202, so as to save the lateral space, thereby reducing the volume of the first package component 10 after being connected and packaged with the substrate 202. Fig. 1 is only schematic, and the number of the first package elements 10 may be selected according to actual needs, wherein the type of the main chip 100 of the first package element 10 may also be selected according to actual needs, for example, the main chip 100 may be one or more of an ASIC chip, a CPU chip, a GPU chip, an FPGA chip, and an MCU chip.
In a specific application scenario, a non-conductive adhesive (not shown) is further included between the plurality of first package elements 10, and the non-conductive adhesive adheres and fixes the first package elements 10 and adheres and fixes the surface of the first package element 10 contacting the substrate 202 and the substrate 202. The non-conductive adhesive can further protect the circuit structures on the first package elements 10, improve the safety of the circuit structures on the stacked first package elements 10, and reduce the probability of damage to the electrical elements due to accidental touch.
In another specific application scenario, a heat sink (not shown) is further included between the first package elements 10, and the heat sink may be a metal sheet with a groove on both sides or a metal sheet with an inclined angle on both sides to achieve better heat dissipation effect, so that heat of the main chip 100 can be dissipated as soon as possible, thereby improving the stability of the main chip 100 and prolonging the service life thereof.
The electrical connection structures 104 on the first package element 10 in this embodiment are exposed from the side surface of the first package element 10, and the electrical connection structures 104 are electrically connected to the pads 1000 on the functional surface, and the electrical connectors 204 are electrically connected to the electrical connection structures 104 on the side surfaces of the plurality of first package elements 10 and the substrate 202, so as to interconnect the plurality of main chips 100 and the substrate 202. The first package elements 10 are stacked without being staggered in a stacking mode, so that the transverse space is saved, the overall size is reduced, the main chip 100 is not perforated, the yield and the reliability of the main chip 100 are improved, and the side surfaces of the stacked first package elements 10 are connected with each other by the electric connectors 204 and the substrate 202, so that the connection is firmer and the reliability is higher.
Further, the first package element 10 further includes: the first molding compound layer 102 and the first insulating layer 106 are located on one side of the functional surface of the main chip 100, the first insulating layer 106 is located away from the main chip 100 relative to the first molding compound layer 102, and at least a portion of the electrical connection structure 104 is located between the first molding compound layer 102 and the first insulating layer 106. At least a portion of the electrical connection structure 104 located on the side of the first package component 10 is exposed from the first molding compound layer 102 and the first insulating layer 106.
In one application, as shown in fig. 2, all the electrical connection structures 104 are located between the first molding layer 102 and the first insulating layer 106, and the side surfaces of the electrical connection structures 104 are flush with the side surfaces of the first molding layer 102 and the first insulating layer 106.
In another application, a part of the electrical connection structure 104 is located between the first molding layer 102 and the first insulating layer 106, the remaining part of the electrical connection structure 104 covers the side surface of the first molding layer 102, and the remaining part of the electrical connection structure 104 is flush with the side surface of the first insulating layer 106.
In the two application modes, the first plastic package layer 102 covers the functional surface and the side surface of the main chip 100, so as to protect the main chip 100 below the first plastic package layer 102, thereby reducing the probability of short circuit of the circuit structure on the main chip 100, and the first insulating layer 106 covers the side of the electrical connection structure 104 away from the main chip 100, so that the electrical connection structure 104 cannot be electrically connected with other electrical elements except the exposed part located on the side surface of the first package element 10.
Further, as shown in fig. 2, the electrical connection structure 104 includes: the first conductive layer 1040 is located at one side of the first molding compound layer 102 and electrically connected to the pad 1000, and the first conductive pillar 1042 is electrically connected to the first conductive layer 1040.
In a specific application scenario, referring to fig. 2 again, first notches (not shown) are disposed on two sides of the first plastic package layer 102, the first conductive layer 1040 is located on one side of the first plastic package layer 102 and electrically connected to the pad 1000, the first conductive pillar 1042 is located on a side surface of the first conductive layer 1040, the first conductive layer 1040 and the first conductive pillar 1042 fill the first notches on the first plastic package layer 102, and side surfaces of the first conductive layer 1040 and the first conductive pillar 1042 are flush with the first plastic package layer 102.
Referring to fig. 3, fig. 3 is a schematic flow chart of an embodiment of forming the first package device of fig. 2, the method comprising:
step S101: and forming a first plastic package layer on the side surfaces and one side of the functional surfaces of the main chips, wherein the bonding pads on the functional surfaces of the main chips are exposed out of the first plastic package layer, and a first opening is formed on the first plastic package layer between the adjacent main chips.
In an application manner, please refer to fig. 4, where fig. 4 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 3, and step S101 specifically includes:
step S201: and pasting one side of the non-functional surfaces of the main chips on the first carrier plate.
Specifically, referring to fig. 5a, fig. 5a is a schematic cross-sectional structure diagram of an embodiment corresponding to step S201 in fig. 4, the first carrier 200 in fig. 5 only schematically shows one of the regions, in practical applications, the first carrier 200 may be a larger region, and is divided into a plurality of small regions, and a peelable adhesive is used to adhere the non-functional surface side of the main chip 100 to the first carrier 200 in each small region.
Step S202: the first die is arranged on one side of the functional surfaces of the main chips, wherein a plurality of first convex parts are arranged on one side, facing the main chips, of the first die, and the first convex parts correspond to areas between the adjacent main chips.
Specifically, referring to fig. 5b, fig. 5b is a schematic cross-sectional structure view of an embodiment corresponding to step S202 in fig. 4, after the first mold 300 is disposed on the plurality of main chips 100, the main chips 100 are spaced apart by the first protrusions 3000 on the first mold 300. Fig. 5b is merely schematic, and when N main chips 100 are provided, N-1 first protrusions 3000 between the corresponding main chips 100 on the first mold 300, two first protrusions 3000 at the outermost edge on the first mold 300, and the width of the first protrusions 3000 between the corresponding main chips 100 of the first mold 300 is twice the width of the first protrusions 3000 at the outermost edge. The first protrusion 3000 may contact the first carrier 200 or may have a certain distance from the first carrier 200 as shown in fig. 5 b.
Step S203: and forming a first plastic package layer on the side surface and one side of the functional surface of the main chip, exposing the bonding pad on the functional surface of the main chip from the first plastic package layer, and forming a first opening on the first plastic package layer at a position corresponding to the first convex part.
Specifically, referring to fig. 5c, fig. 5c is a schematic cross-sectional structure diagram of an embodiment corresponding to step S203 in fig. 4, the first carrier 200, the main chip 100 and the first mold 300 are disposed in a mold cavity for molding to form the first molding layer 102, and the first mold 300 is schematically removed away from the main chip 100 in fig. 5c to make the illustration more clear. As shown in fig. 5c, the first protrusion 3000 is spaced apart from the first carrier 200, and a space is formed between the bottom of the first opening 1020 of the first molding compound layer 102 and the first carrier 200. If the first protrusion 3000 contacts the first carrier 200, the first carrier 200 is exposed from the first opening 1020 after the first molding compound layer 102 is formed. If the end of the first protrusion 3000 contacting the first mold 300 is farther from the first carrier 200 than the functional surface of the main chip 100, the first molding compound 102 is formed to cover the functional surface of the main chip 100. Specifically, the size of the first mold 300 and the position where the first mold 300 is disposed may be selected according to actual needs.
Step S204: the first mold is removed.
Specifically, referring to fig. 5d, fig. 5d is a schematic cross-sectional structure view of an embodiment corresponding to step S204 in fig. 4, when the first molding compound layer 102 does not cover the functional surface of the main chip 100, the first mold 300 is removed, and when the first molding compound layer 102 covers the functional surface of the main chip 100, the first molding compound layer 102 on one side of the functional surface of the main chip 100 is ground to expose the bonding pad 1000 after the first mold 300 is removed.
Step S102: and forming an electric connection structure on the first plastic packaging layer, wherein the electric connection structure is electrically connected with the bonding pad and covers the surface of the first opening.
Specifically, referring to fig. 6, fig. 6 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S102 in fig. 3, an electrical connection structure 104 is formed on one side of the functional surface of the main chip 100, the electrical connection structure 104 is electrically connected to the pad 1000, and the electrical connection structure 104 covers the surface of the first opening 1020.
Specifically, the first conductive layer 1040 is formed on the side of the first molding compound layer 102 away from the functional surface of the main chip 100, the first conductive layer 1040 is formed by sputtering, and after the first conductive layer 1040 is formed, the first conductive layer 1040 is etched to retain a required portion of the first conductive layer 1040, so that the pad 1000 is independent, and the first conductive layer 1040 is fine and is more tightly bonded to the first molding compound layer 102 made of resin. The first conductive layer 1040 covers the first molding layer 102 and the surface of the first opening 1020, and the first conductive layer 1040 is electrically connected to the pad 1000. A first conductive pillar 1042 is formed at a remaining position in the first opening 1020, and the first conductive pillar 1042 is electrically connected to the first conductive layer 1040.
Further, referring to fig. 7, fig. 7 is a schematic cross-sectional view of an embodiment after the step S102 in fig. 3, in which a first insulating layer 106 is formed on a side of the electrical connection structure 104 away from the functional surface of the main chip 100, and the first insulating layer 106 covers a surface of the electrical connection structure 104.
Step S103: and cutting off part of the first plastic packaging layer and part of the electric connection structure between the adjacent main chips to obtain a first packaging element containing a single main chip, wherein the side surface of the first packaging element is provided with the electric connection structure electrically connected with the bonding pad.
Specifically, referring to fig. 2 again, and referring to fig. 5a to 5d in combination, a portion of the first insulating layer 106, the electrical connection structure 104 and the first molding compound layer 102 are cut apart, and the first carrier board 200 is removed to form the first package device 10 including a single main chip 100, the electrical connection structure 104 is electrically connected to the bonding pad 1000, the top and the bottom of the electrical connection structure 104 are covered by the first insulating layer 106 and the first molding compound layer 102, respectively, and only the portion exposed from the side surface of the first package device 10 can be electrically connected to other electrical devices or the main chip 100.
In another specific application scenario, referring to fig. 8, fig. 8 is a schematic structural diagram of another embodiment of the first package element in fig. 1, in which the first molding compound layer 102a covers a functional surface and a side surface of the main chip 100a, the first package element 10a further includes a first passivation layer 105a, an opening (not shown) is disposed on the first passivation layer 105a at a position corresponding to the pad 1000a of the main chip 100a, and the first conductive layer 1040a covers a side of the first passivation layer 105a away from the main chip 100a and is electrically connected to the pad 1000a through the opening on the first passivation layer 105 a. The first conductive pillar 1042a is located on the first conductive layer 1040a at a side away from the main chip 100a, and is electrically connected to the first conductive layer 1040 a. The first insulating layer 106a covers a side of the first conductive layer 1040a away from the main chip 100a, and the first insulating layer 106a covers a side of the first conductive pillar 1042a away from the main chip 100a and a side of the first conductive pillar 1042a close to a center line (not shown) of the main chip 100a, where the side of the first conductive pillar 1042a is flush with the side of the first molding layer 102a and the side of the first insulating layer 106 a.
In another specific application scenario, referring to fig. 9, fig. 9 is a schematic structural diagram of another embodiment of the first package element in fig. 1, in which the first molding compound layer 102b covers a functional surface and a side surface of the main chip 100b, the first package element 10b further includes a first passivation layer 105b, an opening (not shown) is formed on the first passivation layer 105b at a position corresponding to the pad 1000b of the main chip 100b, and the first conductive layer 1040b covers a side of the first passivation layer 105b away from the main chip 100b and a side surface of the first passivation layer 105b, and is electrically connected to the pad 1000b through the opening on the first passivation layer 105 b. The first conductive pillar 1042b is located at a side of the first molding layer 102b and electrically connected to the first conductive layer 1040b at a side of the first passivation layer 105 b. The first insulating layer 106b covers a side of the first conductive layer 1040b away from the main chip 100b, and a side surface of the first conductive pillar 1042b is flush with a side surface of the first insulating layer 106 b. In this embodiment, the first conductive pillar 1042b and the first conductive layer 1040b may be integrally formed.
Further, referring to fig. 1 again, the electrical connection element 204 is a rigid strip-shaped electrical conductor (not labeled), a first conductive portion 2040 electrically connected to the electrical connection structure 104 is disposed on a side of the electrical connection element 204 facing the plurality of first package components 10, and a second conductive portion 2042 electrically connected to the substrate 202 is disposed on a side of the electrical connection element 204 facing the substrate 202, wherein the first conductive portion 2040 is electrically connected to the second conductive portion 2042. The substrate 202 is provided with a plurality of surface levels of the first package components 10.
Specifically, the first conductive portion 2040 and the second conductive portion 2042 are electrically connected through a line (not shown) inside the electrical connector 204, the first conductive portion 2040 on the electrical connector 204 enables interconnection between the first package elements 10, the pad 1000 is electrically connected to the first conductive portion 2040 through the electrical connection structure 104, the second conductive portion 2042 of the electrical connector 204 is electrically connected to the substrate 202, so that the stacked first package components 10 are electrically connected to the substrate 202, the first conductive portion 2040 and the second conductive portion 2042 of the electrical connector 204 have a larger area exposed from the electrical connector 204, the contact with the electrical connection structure 104 and the substrate 202 is more sufficient, and the electrical connections 204 are located at the sides of the plurality of first package elements 10, not punched in the main chip 100, meanwhile, the surface of the substrate 202 provided with the plurality of first package elements 10 is flat to improve the structural strength of the semiconductor package device 20 as a whole.
Referring to fig. 10 and 10, fig. 10 is a schematic structural diagram of another embodiment of the semiconductor package device of the present application, for convenience of understanding, the first package device 10 in fig. 10 is exemplified by the first package device 10 in fig. 2, and a portion of the first package device 10 is combined with fig. 2, and may be replaced by the first package device 10a or 10b in fig. 8 or 9 in other embodiments. In the semiconductor package device 20a of fig. 10, the substrate 202a is provided with a groove (not shown) corresponding to the electrical connector 204a, at least a portion of the electrical connector 204a is located in the groove, and the side surfaces of the plurality of first package elements 10 are flush with the side walls of the groove. When the number of the first package elements 10 is small and the length of the electrical connector 204a is greater than the height of the stacked first package elements 10, the groove on the substrate 202a can accommodate a portion of the electrical connector 204a to reduce the height of the semiconductor package device 20a after packaging, so as to make the semiconductor package device 20a smaller.
Further, when the substrate 202a is provided with a groove, a portion of the electrical connector 204a located in the groove is provided with a conductive hole 2044a, an extending direction of the conductive hole 2044a is non-parallel to the stacking direction of the plurality of first package elements 10, and one end of the conductive hole 2044a is electrically connected to a portion of the substrate 202a (not shown) exposed from the groove.
Specifically, the first conductive portion 2040a on the electrical connector 204a is electrically connected to the electrical connection structure 104 on the side of the plurality of first package elements 10, when the first package elements 10 are stacked on the substrate 202a, the stacking direction of the first package elements 10 is vertical to the substrate 202a, the extending direction of the conductive hole 2044a on the electrical connector 204a is non-parallel to the direction vertical to the substrate 202a, the shape of the conductive hole 2044a may be any polygon such as rectangle and trapezoid, the second conductive portion 2042a is located on the sidewall of the conductive hole 2044a, the second conductive portion 2042a is specifically a deposited metal layer, and the second conductive portion 2042a is electrically connected to the circuit in the substrate 202a at the position corresponding to the conductive hole 2044a, so that the plurality of first package elements 10 are electrically connected to each other and to the substrate 202 a.
Further, the semiconductor package device 20a further includes: a logic chip 206. The logic chip 206 is disposed on the side of the substrate 202a where the plurality of first package elements 10 are disposed, and is electrically connected to the circuits in the substrate 202 a. The Logic chip 206 may be a fixed Logic Device or a Programmable Logic Device (PLD) to adapt to a system with high requirements for operation and timing.
Referring to fig. 11 and 11, fig. 11 is a schematic structural diagram of another embodiment of the semiconductor package device of the present application, for convenience of understanding, the first package device 10 in fig. 11 is exemplified by the first package device 10 in fig. 2, and a portion of the first package device 10 is combined with fig. 2, and may be replaced by the first package device 10a or 10b in fig. 8 or 9 in other embodiments. In the semiconductor package device 20b in fig. 11, the electrical connection element 204b is an L-shaped or Z-shaped flexible conductive member (not labeled), the electrical connection element 204b includes a first connection portion 2046b and a second connection portion 2048b extending from the first connection portion 2046b in a non-parallel manner, the first connection portion 2046b is electrically connected to the electrical connection structures 104 on the side surfaces of the plurality of first package components 10, and the second connection portion 2048b is electrically connected to the substrate 202 b.
Specifically, if the flexible conductive member 2040b on the first connecting portion 2046b is electrically connected to the electrical connection structures 104 on the side surfaces of the plurality of first package components 10, and the second connecting portion 2042b on the second connecting portion 2048b is electrically connected to the substrate 202b, and the total height of the stacked first package component 10 is smaller than the length of the flexible conductive member, a part of the flexible conductive member is disposed on the surface of the side of the first package component 10 away from the substrate 202b, forming the structure shown in fig. 11, if the total height of the stacked first package component 10 is larger than the length of the flexible conductive member, the first connecting portion 2046b of the flexible conductive member is disposed on the side of the stacked first package elements 10, and the surface of the first package element 10 far from the substrate 202b is not covered by the flexible conductive member, so as to form an L-shaped structure. Therefore, the flexible conductive member has a higher adaptability to the number of the stacked first package components 10, so as to meet the requirements of different numbers of first package components 10.
Further, the substrate 202b of the semiconductor package device 20b in the present embodiment is provided with a plurality of surface levels of the first package elements 10 to improve the structural strength of the semiconductor package device 20 b. The side of the second connecting portion 2048b of the electrical connector 204b and the side away from the substrate 202b are further provided with underfill 208b, so that the electrical connector 204b is fixed to the substrate 202b, and the stability of the electrical connector 204b is improved.
It should be noted that the semiconductor package device 20 in fig. 1 and the semiconductor package device 20b in fig. 11 may also include a logic chip 206 as shown in the semiconductor package device 20a in fig. 10, and the logic chip 206 is disposed on the side of the substrate 202/202a/202b where the plurality of first package elements 10 are disposed and electrically connected to the circuits within the substrate 202/202a/202 b. The Logic chip 206 may be a fixed Logic Device or a Programmable Logic Device (PLD) to adapt to a system with high requirements for operation and timing.
Referring to fig. 12 and 12, fig. 12 is a schematic structural diagram of another embodiment of the semiconductor package device of the present application, for convenience of understanding, the first package device 10 in fig. 12 is exemplified by the first package device 10 in fig. 2, and a portion of the first package device 10 is combined with fig. 2, and may be replaced by the first package device 10a or 10b in fig. 8 or 9 in other embodiments. In the first package component 10 of fig. 12, the electrical connection element 204c is an L-shaped silicon bridge (not labeled), a groove (not shown) is formed on the substrate 202c corresponding to the electrical connection element 204c, and one end of the electrical connection element 204c is located in the groove.
Specifically, the first connecting portion 2046c of the electrical connector 204c is located on the side of the stacked first package element 10, the second connecting portion 2048c of the electrical connector 204c is located at least partially in the groove on the substrate 202c, and the first connecting portion 2046c of the electrical connector 204c is fixed to the side of the first package element 10 by a conductive adhesive (not shown), and is further electrically connected to the electrical connection structure 104 on the side thereof. The surface of the second connecting portion 2048c of the electrical connector 204c, which is close to the groove on the substrate 202c, is provided with a non-conductive adhesive (not shown), so that the second connecting portion 2048c of the electrical connector 204c is fixed to the substrate 202c, and the circuit structure on the groove is isolated from other electrical components.
Further, the semiconductor package device 20c in the present embodiment further includes: a logic chip 206 c. The logic chip 206c is disposed on the side of the substrate 202c where the plurality of first package elements 10 are disposed, and is bridged over one end of the electrical connector 204c and the substrate 202c adjacent to the groove, and the logic chip 206c is electrically connected to the electrical connector 204c and the substrate 202 c.
Specifically, the L-shaped silicon bridge can improve the efficiency of high-frequency and high-density signal transmission between the main chips 100, the logic chip 206c can meet the system with higher timing requirement, one end of the logic chip 206c is electrically connected to the second connecting portion 2048c of the electrical connecting member 204c, and the other end is electrically connected to the substrate 202c, so that the main chip 100 in the first package component 10 is electrically connected to the substrate 202c through the electrical connecting structure 104, the electrical connecting member 204c, and the logic chip 206c, and meets the requirement of a system with higher signal transmission speed and computation load, such as an onboard controller, a computer, and the like.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A semiconductor package device, comprising:
a substrate;
the first packaging elements are stacked on the substrate and comprise at least one main chip and an electric connection structure, and the electric connection structure is electrically connected with bonding pads on the functional surface of the main chip and provided with an exposed part positioned on the side surface of the first packaging element;
and the electric connector is positioned on the side surfaces of the plurality of first packaging elements which are arranged in a stacked mode and is electrically connected with the electric connection structures positioned on the side surfaces of the plurality of first packaging elements and the substrate.
2. The semiconductor package device of claim 1,
the first package component further includes: the first plastic packaging layer and the first insulating layer are positioned on one side of the functional surface of the main chip, the first insulating layer is far away from the main chip relative to the first plastic packaging layer, and at least part of the electric connection structure is positioned between the first plastic packaging layer and the first insulating layer;
wherein at least a portion of the electrical connection structure located at the side of the first package element is exposed from the first molding compound layer and the first insulating layer.
3. The semiconductor package device of claim 2,
all the electric connection structures are positioned between the first plastic packaging layer and the first insulating layer, and the side surfaces of the electric connection structures are flush with the side surfaces of the first plastic packaging layer and the first insulating layer; or,
and part of the electric connection structure is positioned between the first plastic packaging layer and the first insulating layer, the rest part of the electric connection structure covers the side surface of the first plastic packaging layer, and the rest part of the electric connection structure is flush with the side surface of the first insulating layer.
4. The semiconductor package device of claim 1,
the electric connecting piece is a strip-shaped hard conductive piece, a first conductive part electrically connected with the electric connecting structure is arranged on one side of the electric connecting piece, which is close to the first packaging elements, and a second conductive part electrically connected with the substrate is arranged on one side of the electric connecting piece, which faces the substrate; wherein the first conductive portion and the second conductive portion are electrically connected.
5. The semiconductor package device of claim 4,
a groove is formed in the position, corresponding to the electric connecting piece, of the substrate, at least part of the electric connecting piece is located in the groove, and the side faces of the first packaging elements are flush with the side walls of the groove;
or the surface of the substrate provided with the plurality of first packaging elements is flat.
6. The semiconductor package device of claim 5,
when the substrate is provided with the groove, a part of the electric connector, which is located in the groove, is provided with a conductive hole, the extending direction of the conductive hole is not parallel to the stacking direction of the plurality of first packaging elements, and one end of the conductive hole is electrically connected with a part, exposed out of the groove, of a circuit in the substrate at a corresponding position.
7. The semiconductor package device of claim 1,
the electric connecting piece is an L-shaped or Z-shaped flexible conductive piece, and comprises a first connecting part and a second connecting part which extends from the first connecting part in a non-parallel mode, the first connecting part is electrically connected with the electric connecting structures on the side faces of the plurality of first packaging elements, and the second connecting part is electrically connected with the substrate.
8. The semiconductor package device of claim 7,
the substrate is provided with a flat surface of the plurality of first package elements.
9. The semiconductor package device of any of claims 4-6, 8, further comprising:
and the logic chip is positioned on one side of the substrate, which is provided with the plurality of first packaging elements, and is electrically connected with the circuit in the substrate.
10. The semiconductor package device of claim 7,
the electric connecting piece is an L-shaped silicon bridge, a groove is formed in the position, corresponding to the electric connecting piece, of the substrate, and one end of the electric connecting piece is located in the groove;
the semiconductor package device further includes: and the logic chip is positioned on one side of the substrate, on which the plurality of first packaging elements are arranged, and bridged on one end of the electric connector and the substrate adjacent to the groove, and the logic chip is electrically connected with the electric connector and the substrate.
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| CN202010740347.5A CN111863796B (en) | 2020-07-28 | 2020-07-28 | Semiconductor packaging device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112838013A (en) * | 2021-01-05 | 2021-05-25 | 山东傲天环保科技有限公司 | Chip structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110943041A (en) * | 2019-12-16 | 2020-03-31 | 山东砚鼎电子科技有限公司 | Semiconductor structure with side surface led out, manufacturing method thereof and stacking structure |
| CN111106078A (en) * | 2019-12-16 | 2020-05-05 | 山东砚鼎电子科技有限公司 | Multi-chip integrated packaging structure |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110943041A (en) * | 2019-12-16 | 2020-03-31 | 山东砚鼎电子科技有限公司 | Semiconductor structure with side surface led out, manufacturing method thereof and stacking structure |
| CN111106078A (en) * | 2019-12-16 | 2020-05-05 | 山东砚鼎电子科技有限公司 | Multi-chip integrated packaging structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112838013A (en) * | 2021-01-05 | 2021-05-25 | 山东傲天环保科技有限公司 | Chip structure and manufacturing method thereof |
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