CN111863110B - Flash memory error page proportion evaluation model and method based on bit error rate - Google Patents
Flash memory error page proportion evaluation model and method based on bit error rate Download PDFInfo
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- CN111863110B CN111863110B CN202010650488.8A CN202010650488A CN111863110B CN 111863110 B CN111863110 B CN 111863110B CN 202010650488 A CN202010650488 A CN 202010650488A CN 111863110 B CN111863110 B CN 111863110B
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention discloses a flash memory error page proportion evaluation model and method based on bit error rate. The flash memory error page ratio can provide a basis for optimizing the performance and power consumption of the solid state disk, but huge time and space overhead is needed for directly acquiring the error page ratio, so that the error page ratio is difficult to directly evaluate. The bit error rate of the flash memory is very convenient to obtain, and the cost is extremely low. Therefore, the invention provides a model and a method for testing and acquiring the bit error rate and the error page proportion related data of a flash memory by analyzing the characteristics of the flash memory, establishing a flash memory bit error rate and error page proportion incidence relation model, and finally approximately estimating the error page proportion by using the bit error rate of the flash memory. The invention has great significance for improving the performance of the solid state disk, reducing the power consumption and relevant industrial application.
Description
Technical Field
The invention belongs to the field of computer storage, and particularly relates to a flash memory error page proportion evaluation model and method based on bit error rate.
Background
In recent years, the development of flash memory technology overcomes the defects of slow read-write performance, high power consumption, poor shock resistance and the like of the traditional mechanical hard disk storage to a certain extent. Compared with the traditional mechanical hard disk, the flash memory has the advantages that the storage capacity is improved sharply due to the three-dimensional flash memory and the multi-bit storage unit technology. However, the rise of big data, artificial intelligence application and mass media data provides more and more serious challenges for the storage system.
At present, the solid state disk obtains high performance by increasing the number of channels and improving the parallel capability, and simultaneously brings huge hardware resource overhead and power consumption. If the error page proportion in the flash memory can be sensed, the dynamic cascade code can be designed. If the error pre-detection technology is implemented, the decoding operation is not necessary for the page without the error, so that the performance and the power consumption of the solid state disk are optimized. However, performing pre-detection on a page with errors results in additional detection operations, reducing read performance and increasing power consumption. Therefore, the error page ratio of the flash memory can be evaluated to guide the dynamic implementation of the error pre-detection operation, and when the error page ratio is very high, the decoding operation is directly performed. The error page proportion of the flash memory cannot be directly obtained, and certain challenges are brought to optimizing the performance and power consumption of the solid state disk by using a similar method.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides a flash memory error page proportion evaluation model and a flash memory error page proportion evaluation method based on a bit error rate, and aims to solve the technical problem that the error page proportion cannot be directly obtained by establishing a flash memory error page proportion and bit error rate correlation model and further evaluating the flash memory error page proportion by using the bit error rate. The adopted specific technical scheme is as follows:
to achieve the above object, according to an aspect of the present invention, there is provided a flash memory error page ratio evaluation model based on bit error rate, comprising the steps of:
(1) sampling and testing the flash memory to obtain error page proportion and bit error rate data under different interference condition combinations;
(2) the error page proportion and the corresponding bit error rate are analyzed and counted, and the statistical result is expressed in number pairs, for example: (error page ratio 1, bit error rate 1), (error page ratio 2, bit error rate 2), … …, (error page ratio i, bit error rate i), … …, (error page ratio N, bit error rate N);
(3) dividing the bit error rate into different intervals, such as dividing a large interval of the bit error rate from 0 to 0.5 into small bit error rate intervals according to a step size of 0.0001, and expressing the small bit error rate intervals as [0, 0.5, 0.0001 ];
(4) counting the bit error rate interval of the data pair in the step (2) according to the bit error rate, and counting the average value (or other statistical indexes) corresponding to all error page proportion data in the same interval;
(5) and (4) correlating the bit error rate interval obtained in the step (3) with the error page ratio result corresponding to each interval in the step (4) to obtain an error page ratio and a bit error rate evaluation model y ═ f (x), wherein x is the bit error rate and y is the error page ratio.
Preferably, in the present invention, the model is established between the error page ratio and the bit error rate of the flash memory.
Preferably, in the present invention, the flash memory error page ratio is equal to the quotient of the error page in a specific unit and the total number of pages, wherein the error page refers to a physical or logical (sub) page containing error bits. The particular units may be different levels of pages, blocks, groupings, and so on.
Preferably, in the present invention, the statistical level of the bit error rate may be counted at a page level, a block level, a super block level, and the like.
Preferably, in the present invention, the error page ratio and bit error rate of the model may be derived from different levels of statistics, such as establishing a block level error page ratio and page level bit error rate model.
Preferably, in the present invention, besides measuring the error page proportion corresponding to the same bit error rate interval by using an average value, the error page proportion may also be measured by counting indexes such as a maximum value, a mode, a median, and an average value of the highest (low) value of the first percentile i.
According to another aspect of the present invention, there is provided a method for evaluating a flash memory error page ratio, including:
(1) for a given bit error rate, judging a bit error rate interval to which the given bit error rate belongs;
(2) and acquiring the error page proportion corresponding to the interval, namely the error page proportion evaluation result.
It should be noted that the error page ratio evaluation model is a model for a specific flash chip model and batch, and the modeling in steps (1) to (5) should be performed again for different flash chip models and batches.
The claimed technical solution is as follows:
a flash memory error page proportion evaluation model and method based on bit error rate, the model establishment includes the following steps:
(1) sampling and testing the flash memory to obtain error page proportion and bit error rate data under different interference condition combinations;
(2) analyzing and counting the error page proportion and the corresponding bit error rate, and representing the statistical result in pairs;
(3) dividing the bit error rate into different intervals;
(4) counting the bit error rate interval of the data pair in the step (2) according to the bit error rate, and counting the statistical data corresponding to all the error page proportion data corresponding to the same interval;
(5) and (4) correlating the bit error rate interval obtained in the step (3) with the error page ratio result corresponding to each interval in the step (4) to obtain an error page ratio and a bit error rate evaluation model y ═ f (x), wherein x is the bit error rate and y is the error page ratio.
The model application comprises the following steps:
(1) for a given bit error rate, judging a bit error rate interval to which the given bit error rate belongs;
(2) and acquiring the error page proportion corresponding to the interval, namely the error page proportion evaluation result.
Preferably, the model is established between the error page ratio and the bit error rate of the flash memory.
Preferably, the error page ratio is a physical page or a logical sub-page, wherein the logical sub-page is divided by the physical page.
Preferably, the statistical data in step (4) may be any one of an average value of all error page ratios, a maximum value, a mode, a median, and an average value of top (low) percentile values.
Preferably, the error page ratio and the bit error rate can be tested and counted at any level of page level, block level and super block level, and the model is obtained by combining the error page ratio and the bit error rate at different or same level.
In general, the above technical solutions contemplated by the present invention can achieve the following beneficial effects:
the invention can quickly evaluate the error page proportion of the flash memory. The method can be used for rapidly evaluating the error page ratio of the flash memory because the error page ratio of the flash memory is evaluated by the bit error rate of the flash memory according to the model proposed by the method, and the bit error rate is easy to obtain.
Drawings
FIG. 1 is a block diagram illustrating a method for establishing a bit error rate-based flash error page ratio estimation model according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The overall idea of the invention is to establish a flash memory error page proportion and bit error rate model, and utilize the bit error rate to carry out an evaluation method on the error page proportion, thereby reducing the problem of excessive cost for directly acquiring the error page proportion. Specifically, as shown in fig. 1, the model building includes the following steps:
(1) data sampling: firstly, sampling test is carried out on the flash memory, and error page proportion and bit error rate data of the flash memory under different interference condition combinations are tested by adopting a control variable method. The error page proportion can be counted at different levels of a page level, a block level, a super block level and the like of the flash memory, and the specific acquisition level is determined according to the application scene of the error page proportion. The statistics of the bit error rate and the error page ratio can be performed at different levels, for example, when the page-level bit error rate is adopted to quickly evaluate the block-level error page ratio, the test sampling of the bit error rate and the error page ratio is performed at the page level and the block level respectively;
(2) and (3) data analysis: analyzing the statistical error page proportion and the corresponding bit error rate, and expressing the statistical result in a number pair, for example: (error page ratio 1, bit error rate 1), (error page ratio 2, bit error rate 2), … …, (error page ratio i, bit error rate i), … …, (error page ratio N, bit error rate N). Dividing the bit error rate into different intervals, such as [0, 0.5, 0.0001] representing dividing a large interval of the bit error rate 0 to 0.5 into small bit error rate intervals according to a step size of 0.0001; the data pairs (error page ratio, bit error rate) are stored into the corresponding bit error rate intervals according to the bit error rate.
(3) Establishing a model: counting error pages corresponding to each bit error rate interval in the step (2), and averaging error page proportion data in the interval, or averaging maximum values, modes, median values and top (low) values of the first percentile i, wherein the average value is determined according to an application scene; and associating the bit error rate interval with a corresponding error page proportion result, for example, establishing a functional relation of the bit error rate, and fitting the error page proportion to obtain an error page proportion and a bit error rate evaluation model, for example, y ═ f (x), wherein x is the bit error rate and y is the error page proportion.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A flash memory error page proportion evaluation model and method based on bit error rate is characterized in that the model establishment comprises the following steps:
(1) sampling and testing the flash memory to obtain error page proportion and bit error rate data under different interference condition combinations;
(2) analyzing and counting the error page proportion and the corresponding bit error rate, and representing the statistical result in pairs;
(3) dividing the bit error rate into different intervals;
(4) counting the bit error rate interval of the data pair in the step (2) according to the bit error rate, and counting the statistical data corresponding to all the error page proportion data corresponding to the same interval;
(5) associating the bit error rate interval obtained in the step (3) with the error page proportion result corresponding to each interval in the step (4) to obtain an error page proportion and a bit error rate evaluation model y = F (x), wherein x is the bit error rate and y is the error page proportion;
the error page ratio is equal to the quotient of the error page and the total page number in a specific unit, wherein the error page refers to a physical page or a logical sub-page containing error bits, and the specific unit can be different levels of pages, blocks and groups.
2. The bit error rate based flash memory error page ratio evaluation model and method of claim 1, wherein: the model is built between the error page ratio and the bit error rate of the flash memory.
3. The bit error rate based flash memory error page ratio evaluation model and method of claim 1, wherein: the statistical data in step (4) may be any one of an average value, a maximum value, a mode, a median, and an average value of the top i percent highest or lowest values of all error page ratios.
4. A flash memory error page proportion evaluation model and method based on bit error rate is characterized in that the model application comprises the following steps:
(1) for a given bit error rate, judging a bit error rate interval to which the given bit error rate belongs;
(2) acquiring the error page proportion corresponding to the interval, namely an error page proportion evaluation result;
the error page ratio is equal to the quotient of the error page and the total page number in a specific unit, wherein the error page refers to a physical page or a logical sub-page containing error bits, and the specific unit can be different levels of pages, blocks and groups.
5. The bit error rate based flash memory error page ratio evaluation model and method as claimed in claim 1 or 4, wherein: the error page ratio and the bit error rate may be tested and counted at any level of page level, block level, super block level, the model being a combination of different or the same level of error page ratio and bit error rate.
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| CN106415502A (en) * | 2014-12-12 | 2017-02-15 | 华为技术有限公司 | Data storage method and device |
| CN106502821A (en) * | 2016-10-26 | 2017-03-15 | 武汉迅存科技有限公司 | A kind of method and system for obtaining flash memory antithesis page false correlations |
| CN109637576A (en) * | 2018-12-17 | 2019-04-16 | 华中科技大学 | A kind of service life of flash memory prediction technique based on support vector regression |
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| WO2009078006A2 (en) * | 2007-12-18 | 2009-06-25 | Densbits Technologies Ltd. | Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith |
| JP6102800B2 (en) * | 2014-03-04 | 2017-03-29 | ソニー株式会社 | Memory controller, storage device, information processing system, and control method therefor. |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106415502A (en) * | 2014-12-12 | 2017-02-15 | 华为技术有限公司 | Data storage method and device |
| CN106502821A (en) * | 2016-10-26 | 2017-03-15 | 武汉迅存科技有限公司 | A kind of method and system for obtaining flash memory antithesis page false correlations |
| CN109637576A (en) * | 2018-12-17 | 2019-04-16 | 华中科技大学 | A kind of service life of flash memory prediction technique based on support vector regression |
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