CN106502821A - A kind of method and system for obtaining flash memory antithesis page false correlations - Google Patents
A kind of method and system for obtaining flash memory antithesis page false correlations Download PDFInfo
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- CN106502821A CN106502821A CN201610947668.6A CN201610947668A CN106502821A CN 106502821 A CN106502821 A CN 106502821A CN 201610947668 A CN201610947668 A CN 201610947668A CN 106502821 A CN106502821 A CN 106502821A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses a kind of method for obtaining flash memory antithesis page false correlations, with the lifting of flash memory storage density, data reliability is destroyed.Raw bit error rate alreadys exceed the error correcting capability of error correcting code, so that error correcting code is not sufficient to ensure that data reliability, in order to design effective error correction code algorithms, it is necessary there is individual being apparent to the failure mode of flash memory, for this purpose, our false correlations to antithesis page in flash memory are studied, when there are bit-errors due to interference in some page of flash memory, the bit of its antithesis page can also be interfered and make a mistake, and this phenomenon is referred to as the false correlations of flash memory antithesis page.By studying to the false correlations of flash memory antithesis page, can effective error correcting code reasonable in design ensureing data reliability.
Description
Technical field
The invention belongs to solid-state disk technical field of memory, obtains flash memory antithesis page mistake correlation more particularly, to a kind of
The method and system of property.
Background technology
Flash memory has the advantages such as high-performance, Large Copacity, low energy consumption, quick read or write speed and is widely used in computer
In storage system, with the increase of flash memory storage density, raw Bit-Error-Rate is gradually lifted, and data reliability declines, and causes tradition
Error correction code algorithms be not sufficient to ensure that data reliability, in order to design targetedly algorithm, need to enter the error pattern of flash memory
Row research.
Flash memory antithesis page is present in flash block, its structure as shown in figure 1, when by bit data write flash memory in when, per
Two bits of individual unit are written in two different pages, and wherein the two bits are referred to as antithesis bit, the two bits
Affiliated page is referred to as antithesis page, and wherein each page is a single error correcting code unit, and the wrong data in each page passes through
Error correction code algorithms are independently corrected.
However, existing to flash block in page error property carry out research and there is following clearly disadvantageous part：
First, the existing error property to Hash memory pages is studied the bit-errors correlative character that does not explore between antithesis page,
The impact to the bit in its antithesis page when page in flash block occurs bit-errors is not accounted for；Secondly, existing research
Method does not fully excavate the internal error feature of Hash memory pages；The appearance of the two problems, when can cause subsequent design error correcting code
Extra memory space is needed, so as to increased expense.
Content of the invention
Disadvantages described above or Improvement requirement for prior art, the invention provides a kind of obtain flash memory antithesis page mistake phase
Close property method and system, it is intended that by consider flash block in page occur bit-errors when to its antithesis page in
The impact of bit, and by fully excavating the internal error feature of Hash memory pages, solve subsequently to set present in existing research method
Extra memory space is needed during meter error correcting code, so as to increased the technical problem of expense.
For achieving the above object, according to one aspect of the present invention, there is provided a kind of acquisition flash memory antithesis page mistake is related
The method of property, comprises the following steps：
(1) receive and be sequentially written in request of data from top service device, request of data is sequentially written in for SSD controls according to this
The random data that device processed is generated distributes corresponding caching, all of caching composition data pond；
(2) request that is sequentially written in from user side is received, and request is sequentially written in for distribution in step (1) according to this
All data distribution page addresses in each caching, and all data in data pool are write according to the page address of distribution
To in the page of flash memory；
(3) judge whether all pages in the flash memory of SSD are all written into, if it is, proceeding to step (4), otherwise turn
Enter step (7)；
(4) corresponding data that will be stored according to first page address that distributes in step (2) in flash memory pages reads,
And the data in first caching of the data for reading with distribution in step (1) are compared, it is somebody's turn to do with counting in flash memory pages
The number of errors of data and errors present；
(5) for the remaining page address of distribution in step (2), above-mentioned steps (4) are repeated, until in flash memory pages
Till all data are all finished by statistics, and by the quantity of all wrong data in the flash memory pages for counting, errors present and
Address of the wrong data in flash memory pages is stored in default error message list as data entries；
(6) antithesis page is determined according to address of the wrong data in flash memory pages in error message list, and counts all
Antithesis number of bit errors and position in antithesis page, and the antithesis number of bit errors for counting and position are stored in mistake
In information list；
(7) continue the remaining data in data pool to be written in the page of flash memory according to the page address of distribution, until
Till flash memory pages are write completely completely, step (4) is then back to.
Preferably, being sequentially written in request of data and requiring data to be write by page, the size of the caching is equal to the flash memory of SSD
Page-size.
Preferably, the allocated page address of each data is：Packet in SSD channel number+SSD chip number+SSD chips
Page number in number+SSD chips in the block number+SSD chips of packet number in the block of packet number；
Preferably, the error message list can be arranged in SSD, it is also possible to be arranged on server or user side.
Preferably, after being additionally included in the step (6), before step (7), by error number in error message list
According to quantity, errors present and wrong data address and antithesis number of bit errors in flash memory pages and position write
In journal file.
It is another aspect of this invention to provide that there is provided a kind of obtain flash memory antithesis page false correlations system, including：
First module, is sequentially written in request of data for receiving from top service device, is sequentially written in data according to this
Ask to distribute corresponding caching, all of caching composition data pond for the random data that SSD controller is generated；
Second module, for receiving the request that is sequentially written in from user side, and is sequentially written in request for first according to this
All data distribution page addresses in module in each caching of distribution, and according to the page address that distributes by data pool
All data are written in the page of flash memory；
Three module, for judging whether all pages in the flash memory of SSD are all written into, if it is, proceed to the 4th
Module, otherwise proceeds to the 7th module；
4th module is right in flash memory pages for will be stored according to first page address that distributes in the second module
Data read-out is answered, and the data in first caching of the data of reading with distribution in the first module are compared, to count
The number of errors of the data and errors present in flash memory pages；
5th module, for for the remaining page address that distributes in the second module, repeating above-mentioned 4th module, directly
To in flash memory pages, all data are all finished by statistics, and the number by all wrong data in the flash memory pages for counting
Amount, the address of errors present and wrong data in flash memory pages are stored in default error message row as data entries
In table；
6th module, for determining antithesis page according to address of the wrong data in flash memory pages in error message list,
And count the antithesis number of bit errors in all antithesis pages and position, and by the antithesis number of bit errors for counting and position
It is stored in error message list；
7th module, for continuing the page that the remaining data in data pool is written to flash memory according to the page address of distribution
In face, till flash memory pages are write completely completely, the 4th module is then back to.
Preferably, being sequentially written in request of data and requiring data to be write by page, the size of the caching is equal to the flash memory of SSD
Page-size.
Preferably, the allocated page address of each data is：Packet in SSD channel number+SSD chip number+SSD chips
Page number in number+SSD chips in the block number+SSD chips of packet number in the block of packet number；
Preferably, the error message list can be arranged in SSD, it is also possible to be arranged on server or user side.
Preferably, also include the 8th module, for by the quantity of wrong data, errors present and mistake in error message list
Address of the data in flash memory pages and antithesis number of bit errors and position are write in journal file by mistake.
In general, by the contemplated above technical scheme of the present invention compared with prior art, can obtain down and show
Beneficial effect：
(1) present invention arrives step (6) as a result of step (2), and its page that considers in flash block occurs bit-errors
When impact to bit in its antithesis page, and by fully excavating the internal error feature of Hash memory pages, so as to solve existing grinding
Extra memory space is needed when studying carefully subsequent design error correcting code present in method, so as to increased the technical problem of expense；
(2) present invention can provide foundation and reference for designing effective error correction code algorithms.
Description of the drawings
Fig. 1 is the internal structure schematic diagram of existing flash block.
Fig. 2 is the flow chart of the method that the present invention obtains flash memory antithesis page false correlations.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, and
It is not used in the restriction present invention.As long as additionally, involved technical characteristic in invention described below each embodiment
Do not constitute conflict each other can just be mutually combined.
As shown in Fig. 2 the method that the present invention obtains flash memory antithesis page false correlations is comprised the following steps：
(1) receive and be sequentially written in request of data from top service device, request of data is sequentially written in for solid-state according to this
The random data that disk (Solid state disk, abbreviation SSD) controller is generated distributes corresponding caching, all of caching composition
Data pool；Specifically, being sequentially written in request of data and requiring data to be write by page, the size of the caching is equal to the flash memory of SSD
The page-size of (Flash Memory, abbreviation FM)；
The advantage of this step is：The random data for generating can effectively be managed, the number in needing to cache
According to when quickly and efficiently can extract.
(2) request that is sequentially written in from user side is received, and request is sequentially written in for distribution in step (1) according to this
All data distribution page addresses in each caching, and all data in data pool are write according to the page address of distribution
To in the page of flash memory；Specifically, the allocated page address of each data is：SSD channel number+SSD chip number+SSD cores
Page number in packet number+SSD chips in piece in the block number+SSD chips of packet number in the block of packet number；
The advantage of this step is：Clearly the random data of generation can be written in the SSD pages that specifies, so as to
Data required for rapidly can reading when reading.
(3) judge whether all pages in the flash memory of SSD are all written into, if it is, proceeding to step (4), otherwise turn
Enter step (8)；
(4) corresponding data that will be stored according to first page address that distributes in step (2) in flash memory pages reads,
And the data in first caching of the data for reading with distribution in step (1) are compared, it is somebody's turn to do with counting in flash memory pages
The number of errors of data and errors present；Specifically, the two data is exactly carried out (bit) comparison by turn by this step, once
The two differs, then the corresponding data in explanation flash memory pages makes a mistake, and now records the wrong data in flash memory pages
In position；
The advantage of this step is：The wrong data being stored in the SSD pages can be effectively counted, be research SSD
The false correlations feature of antithesis page provides foundation.
(5) for the remaining page address of distribution in step (2), above-mentioned steps (4) are repeated, until in flash memory pages
Till all data are all finished by statistics, and by the quantity of all wrong data in the flash memory pages for counting, errors present and
Address of the wrong data in flash memory pages is stored in default error message list as data entries；Concrete and
Speech, the error message list can be arranged in SSD, it is also possible to be arranged on server or user side；
The advantage of this step is：The antithesis page being clear that according to page address in the SSD pages, and antithesis
The amount of bits of page error and position.
(6) antithesis page is determined according to address of the wrong data in flash memory pages in error message list, and counts all
Antithesis number of bit errors and position in antithesis page (page 2 in wordline 1 in such as Fig. 1 and page 8 be antithesis page), and
The antithesis number of bit errors for counting and position are stored in error message list；
(7) by the ground of the quantity of wrong data, errors present and wrong data in flash memory pages in error message list
In location and antithesis number of bit errors and position write journal file；
The advantage of this step is：Research is carried out for the follow-up false correlations feature to SSD antithesis pages and provides one kind just
Profit, the data when research needs, required for directly can transferring.
(8) continue the remaining data in data pool to be written in the page of flash memory according to the page address of distribution, until
Till flash memory pages are write completely completely, step (4) is then back to.
As it will be easily appreciated by one skilled in the art that the foregoing is only presently preferred embodiments of the present invention, not in order to
The present invention, all any modification, equivalent and improvement that is made within the spirit and principles in the present invention etc. is limited, all should be included
Within protection scope of the present invention.
Claims (10)
1. a kind of obtain flash memory antithesis page false correlations method, it is characterised in that comprise the following steps：
(1) receive and be sequentially written in request of data from top service device, request of data is sequentially written in for SSD controller according to this
The random data of generation distributes corresponding caching, all of caching composition data pond；
(2) request that is sequentially written in from user side is received, and each that asks as distributing in step (1) is sequentially written according to this
All data distribution page addresses in caching, and all data in data pool are written to by sudden strain of a muscle according to the page address of distribution
In the page that deposits；
(3) judge whether all pages in the flash memory of SSD are all written into, if it is, proceeding to step (4), otherwise proceed to step
Suddenly (7)；
(4) corresponding data that will be stored according to first page address that distributes in step (2) in flash memory pages reads, and will
The data of reading are compared with the data in first caching of distribution in step (1), to count the data in flash memory pages
Number of errors and errors present；
(5) for the remaining page address of distribution in step (2), above-mentioned steps (4) are repeated, until owning in flash memory pages
Till data are all finished by statistics, and by the quantity of all wrong data, errors present and mistake in the flash memory pages for counting
Address of the data in flash memory pages is stored in default error message list as data entries；
(6) antithesis page is determined according to address of the wrong data in flash memory pages in error message list, and counts all antithesis
Antithesis number of bit errors and position in page, and the antithesis number of bit errors for counting and position are stored in error message
In list；
(7) continue the remaining data in data pool to be written in the page of flash memory according to the page address of distribution, until flash memory
Till the page is write completely completely, step (4) is then back to.
2. method according to claim 1, it is characterised in that be sequentially written in request of data and require to write data by page,
The size of the caching is equal to the page-size of the flash memory of SSD.
3. method according to claim 1, it is characterised in that the allocated page address of each data is：SSD channel numbers
Page in packet number+SSD chips in+SSD chip number+SSD chips in the block number+SSD chips of packet number in the block of packet number
Number.
4. method according to claim 1, it is characterised in that the error message list can be arranged in SSD, it is also possible to
It is arranged on server or user side.
5. method according to claim 1, it is characterised in that after being additionally included in the step (6), step (7)
Before, by the address of the quantity of wrong data, errors present and wrong data in flash memory pages in error message list and
In antithesis number of bit errors and position write journal file.
6. a kind of obtain flash memory antithesis page false correlations system, it is characterised in that include：
First module, is sequentially written in request of data for receiving from top service device, is sequentially written in request of data according to this
Distribute corresponding caching, all of caching composition data pond for the random data that SSD controller is generated；
Second module, for receiving the request that is sequentially written in from user side, and is sequentially written in request for the first module according to this
All data distribution page addresses in each caching of middle distribution, and will be all in data pool according to the page address of distribution
Data are written in the page of flash memory；
Three module, for judging whether all pages in the flash memory of SSD are all written into, if it is, the 4th module is proceeded to,
Seventh module is otherwise proceeded to；
4th module, for will be stored in the corresponding number in flash memory pages according to first page address that distributes in the second module
According to reading, and the data in first caching of the data of reading with distribution in the first module are compared, to count flash memory
The number of errors of the data and errors present in the page；
5th module, for for the remaining page address that distributes in the second module, repeating above-mentioned 4th module, until dodge
Deposit till in the page, all data are all finished by statistics, and by the quantity of all wrong data, mistake in the flash memory pages for counting
The address of position and wrong data in flash memory pages is stored in default error message list as data entries by mistake；
6th module, for determining antithesis page according to address of the wrong data in flash memory pages in error message list, and unites
The antithesis number of bit errors in all antithesis pages and position is counted, and the antithesis number of bit errors for counting and position are stored
In error message list；
7th module, for continuing the page that the remaining data in data pool is written to flash memory according to the page address of distribution
In, till flash memory pages are write completely completely, it is then back to the 4th module.
7. system according to claim 6, it is characterised in that be sequentially written in request of data and require to write data by page,
The size of the caching is equal to the page-size of the flash memory of SSD.
8. system according to claim 6, it is characterised in that the allocated page address of each data is：SSD channel numbers
Page in packet number+SSD chips in+SSD chip number+SSD chips in the block number+SSD chips of packet number in the block of packet number
Number.
9. system according to claim 6, it is characterised in that the error message list can be arranged in SSD, it is also possible to
It is arranged on server or user side.
10. system according to claim 6, it is characterised in that also include the 8th module, for by error message list
The address of the quantity of wrong data, errors present and wrong data in flash memory pages and antithesis number of bit errors and position
Put in write journal file.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863110A (en) * | 2020-07-08 | 2020-10-30 | 上海威固信息技术股份有限公司 | Flash memory error page proportion evaluation model and method based on bit error rate |
| CN111863117A (en) * | 2020-07-08 | 2020-10-30 | 上海威固信息技术股份有限公司 | Flash memory error page proportion evaluation model and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599305A (en) * | 2008-06-04 | 2009-12-09 | 威刚科技股份有限公司 | Storage system with data repair function and data repair method thereof |
| CN102473138A (en) * | 2009-06-29 | 2012-05-23 | 甲骨文美国公司 | Extended main memory hierarchy having flash memory for page fault handling |
| CN103814409A (en) * | 2011-07-28 | 2014-05-21 | 桑迪士克科技股份有限公司 | Post-write read in non-volatile memories using comparison of data as written in binary and multi-state formats |
| CN103827971A (en) * | 2011-07-28 | 2014-05-28 | 桑迪士克科技股份有限公司 | Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages |
-
2016
- 2016-10-26 CN CN201610947668.6A patent/CN106502821A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599305A (en) * | 2008-06-04 | 2009-12-09 | 威刚科技股份有限公司 | Storage system with data repair function and data repair method thereof |
| CN102473138A (en) * | 2009-06-29 | 2012-05-23 | 甲骨文美国公司 | Extended main memory hierarchy having flash memory for page fault handling |
| CN103814409A (en) * | 2011-07-28 | 2014-05-21 | 桑迪士克科技股份有限公司 | Post-write read in non-volatile memories using comparison of data as written in binary and multi-state formats |
| CN103827971A (en) * | 2011-07-28 | 2014-05-28 | 桑迪士克科技股份有限公司 | Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages |
Non-Patent Citations (1)
| Title |
|---|
| 夏倩: "《http://www.airitilibrary.com/Publication/alDetailedMesh?docid=D01076028》", 1 September 2016 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863110A (en) * | 2020-07-08 | 2020-10-30 | 上海威固信息技术股份有限公司 | Flash memory error page proportion evaluation model and method based on bit error rate |
| CN111863117A (en) * | 2020-07-08 | 2020-10-30 | 上海威固信息技术股份有限公司 | Flash memory error page proportion evaluation model and method |
| CN111863117B (en) * | 2020-07-08 | 2022-04-29 | 上海威固信息技术股份有限公司 | Flash memory error page proportion evaluation model and method |
| CN111863110B (en) * | 2020-07-08 | 2022-04-29 | 上海威固信息技术股份有限公司 | Flash memory error page proportion evaluation model and method based on bit error rate |
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Application publication date: 20170315 |