CN111859833B - Configurable system level verification environment construction method, system and medium - Google Patents
Configurable system level verification environment construction method, system and medium Download PDFInfo
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Abstract
The invention discloses a configurable system-level verification environment construction method, which is used for constructing a system-level verification environment for generating an integrated circuit chip, and comprises the following steps: recording compiling parameters of all different platforms and different functional requirements in system level verification of the design to be tested into a template file; determining a switch for each compiling parameter in the template file; recording all logic relations among the switches by using a rule file; providing a configuration file according to the specific function required, and indicating the required switch and the value thereof; applying the rule file to the configuration file for validity check, and selecting required compiling parameters from the template file according to a switch designated by the configuration file if the rule file passes the check; otherwise, returning error information and exiting. The invention can meet the requirements of different verification platforms and different verification functions, and has the advantages of good reliability, easy use, flexible configuration, difficult error and convenient reuse.
Description
Technical Field
The present invention relates to integrated circuit chip verification technology, and in particular, to a configurable system level verification environment construction method, system and medium.
Background
When the integrated circuit chip performs system level verification, it is generally required to consider that the design code of the chip is verified in a simulation manner on a plurality of different verification platforms (such as a hardware simulator, a soft simulation and an FPGA), and according to the characteristics of the verification platforms, the requirements of tools on the design code are different, so that some design modules need to use different compiling parameters on different verification platforms, including different macro definitions, parameter assignment, file lists and compiling options. Even for the same platform, there is a part of modules in the chip design which are replaced by functional models, null models or some specific behavior components according to verification requirements, and when different functions are used, the different functions are also different in compiling parameters.
In order to meet the requirements of different verification platforms and different verification functions, a plurality of sets of macro definitions, parameter assignment, file lists and compiling option files can be maintained at the same time, but the disadvantage is that verification personnel are required to maintain the respective files respectively, the verification process is difficult to uniformly manage, confusion and errors are easy to occur, and reuse is not facilitated.
Disclosure of Invention
The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a configurable system-level verification environment construction method, a system and a medium, which can meet the requirements of different verification platforms and different verification functions and have the advantages of good reliability, easy use, flexible configuration, difficult error and convenient reuse.
In order to solve the technical problems, the invention adopts the following technical scheme:
A configurable system-level verification environment construction method for constructing a system-level verification environment for generating an integrated circuit chip, the method comprising:
Recording compiling parameters of all different platforms and different functional requirements in system level verification of the design to be tested into a template file;
determining a switch for each compiling parameter in the template file;
Recording all logic relations among the switches by using a rule file;
providing a configuration file according to the specific function required, and indicating the required switch and the value thereof;
Applying the rule file to the configuration file for validity check, and selecting required compiling parameters from the template file according to a switch designated by the configuration file if the rule file passes the check; otherwise, returning error information and exiting.
Optionally, the compiling parameters of all different platforms and different functional requirements recorded in the template file specifically include macro definitions, parameter assignment, file list and compiling options which can be directly identified by the compiling tool of the target platform.
Optionally, when determining a switch for each compiling parameter in the template file, each switch includes a switch name and a state quantity, where the state quantity includes a value of on or off of the switch, which means a configuration for turning on or off a function defined by the switch name.
Optionally, the logic relationship specifically refers to a logic relationship that takes a state quantity of a switch as a logic true value and a logic false value, and adopts a logic expression of a binary logic variable to represent the mutual association between the switches.
Optionally, the rule file contains a set of logical expressions with switch names as logical variables that fully embody constraints present in the design code, verification platform, verification functions, all of which must remain true.
Optionally, the validity check is specifically performed on a switch specified in a configuration file and a value thereof, values of all logic expressions in the check rule file are true values and can pass the check, and only the configuration file passing the validity check is the valid configuration file.
Optionally, when the switch specified according to the configuration file selects the required compiling parameter from the template file, a rule for selecting the required compiling parameter is as follows: if the compiling parameters in the template file have switch statement and are consistent with the values of the switches indicated by the configuration file, selecting; when the compiling parameter in the template file has a plurality of switch declarations, the compiling parameter can be selected only when each switch is consistent with the value of the switch indicated by the configuration file.
Optionally, the returning error information includes returning a specific logic expression with a value not true in the rule file.
The invention further provides a configurable system level verification environment construction system comprising a computer device programmed or configured to perform the steps of the configurable system level verification environment construction method, or a computer program programmed or configured to perform the configurable system level verification environment construction method stored in a memory of the computer device.
Furthermore, the present invention provides a computer-readable storage medium having stored therein a computer program programmed or configured to perform the configurable system-level verification environment construction method.
Compared with the prior art, the invention has the following advantages: the system level verification environment management system can uniformly and effectively manage the system level verification environment, has high flexibility, can be configured according to specific verification requirements, is convenient to use for users, is not easy to make mistakes, and well meets the requirements of a plurality of verification platforms and different verification functions. The invention can meet the requirements of different verification platforms and different verification functions, and has the advantages of good reliability, easy use, flexible configuration, difficult error and convenient reuse.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific examples.
The configurable system-level verification environment construction method of the present embodiment is used for constructing a system-level verification environment for generating an integrated circuit chip, as shown in fig. 1, and includes:
Recording compiling parameters of all different platforms and different functional requirements in system level verification of the design to be tested into a template file;
determining a switch for each compiling parameter in the template file;
Recording all logic relations among the switches by using a rule file;
providing a configuration file according to the specific function required, and indicating the required switch and the value thereof;
Applying the rule file to the configuration file for validity check, and selecting required compiling parameters from the template file according to a switch designated by the configuration file if the rule file passes the check; otherwise, returning error information and exiting.
In this embodiment, the compiling parameters of all different platforms and different functional requirements recorded in the template file specifically include macro definitions, parameter assignment, file list and compiling options that can be directly identified by the compiling tool of the target platform. In this embodiment, the compiling parameters are divided into two types, which must be used and only used under specific conditions, and for the compiling parameters used under specific conditions, single or multiple switches and values need to be declared for them in the template file.
The customization of compiling parameters of all different platforms and different functional requirements can be realized through macro definition, parameter assignment, file list and compiling options, so that the aim of meeting the requirements of different verification platforms and different verification functions is fulfilled.
In this embodiment, when determining a switch for each compiled parameter in the template file, each switch includes a switch name and a state quantity, where the state quantity includes a value of whether the switch is set to on (open) or off (closed), which means a configuration in which a function defined by the switch name is turned on or off. The template file is determined according to all macro definitions, file lists, parameter assignment and compiling options required by the verification platform and the verification function during system level verification of the design to be tested, and if each macro definition, file list, parameter assignment and compiling option in the template file is only started under a specific function, the corresponding switch statement is generated.
In this embodiment, the template file contains the compiling parameters required by the system to verify all the platforms and all the functions, and each compiling parameter may not assert a switch or assert a switch and its value. If the switch is not asserted, the compilation parameters are always useful and will appear in the final verification environment under all configuration conditions; if a single or multiple switches are asserted, the compilation parameters will only appear in the final verification environment if the value of these switches is equal to the asserted value.
Switches already declared in the template file, if there is an association, record this relationship to the rule file with a logical expression. In this embodiment, the logic relationship specifically refers to a logic relationship in which the state quantities (on and off) of the switches are regarded as logical true values and false values, and the logic expression of the binary logic variable is used to represent the correlation between the switches. The logical relationship refers to the interrelationship between the switches. Because the values on and off of the switches can be regarded as logical true and false values, the relationship between the switches can be represented by a logical expression of a binary logical variable. Logical operators that may be used to describe logical relationships in this embodiment include logical implications, logical AND, logical NOT, logical OR. For example, if the module A uses the empty model switch to be A_NULL and the module B uses the empty model switch to be B_NULL, then if the module A and the module B must use the empty model simultaneously in the appointed design code, then the logic relationship A_NULL implies B_NULL, and B_NULL implies A_NULL.
In this embodiment, the rule file contains a set of logical expressions with switch names as logical variables, which fully embody the constraints existing in the design code, verification platform, and verification function, and all the logical expressions in the rule file must remain true.
In this embodiment, the configuration file is specifically a description file indicating a group of switches and their values, which are provided by the user. For specifying the authentication platform used by the user and the system level authentication functions to be used by the user. And the user determines the switch and the value thereof to form a configuration file according to the function and the target verification platform required by the user.
In this embodiment, the validity check is specifically performed on the switch specified in one configuration file and the value thereof, the values of all the logic expressions in the check rule file are true values and can pass the check, and only the configuration file passing the validity check is the valid configuration file. And substituting the switch value in the configuration file defined by the user into the logic expression in the rule file by using the computer program, if all the logic expressions are true, passing the validity check, otherwise, not passing, and returning the logic expression with the result not true to the user.
In this embodiment, when a required compiling parameter is selected from a template file according to a switch specified by a configuration file, a rule for selecting the required compiling parameter is as follows: if the compiling parameters in the template file have switch statement and are consistent with the values of the switches indicated by the configuration file, selecting; when the compiling parameter in the template file has a plurality of switch declarations, the compiling parameter can be selected only when each switch is consistent with the value of the switch indicated by the configuration file. In the dead time, a computer program is used for reading in the switches and the values thereof in the configuration file, compiling parameter corresponding to the switch statement is read from the template file, and if each switch and the values thereof in the switch statement are consistent with the specification in the configuration file, the compiling parameter is reserved. If the compilation parameters do not assert a switch, then it is directly reserved.
In this embodiment, when the error information is returned, the specific logic expression whose value is not true in the return rule file is included, so as to obtain the error information for debugging and modification.
In addition, the embodiment also provides a configurable system-level verification environment construction system, which comprises a computer device, wherein the computer device is programmed or configured to execute the steps of the configurable system-level verification environment construction method, or a computer program programmed or configured to execute the configurable system-level verification environment construction method is stored in a memory of the computer device.
Furthermore, the present embodiment also provides a computer-readable storage medium having stored therein a computer program programmed or configured to perform the aforementioned configurable system-level verification environment construction method.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (8)
1. A configurable system-level verification environment construction method for constructing a system-level verification environment for generating integrated circuit chips, the method comprising:
Recording compiling parameters of all different platforms and different functional requirements in system level verification of the design to be tested into a template file;
determining a switch for each compiling parameter in the template file;
Recording all logic relations among the switches by using a rule file; the rule file contains a group of logic expressions taking switch names as logic variables, the logic expressions completely reflect constraints existing in design codes, verification platforms and verification functions, and all logic expressions in the rule file must be kept true;
providing a configuration file according to the specific function required, and indicating the required switch and the value thereof;
Applying the rule file to the configuration file for validity check, and selecting required compiling parameters from the template file according to a switch designated by the configuration file if the rule file passes the check; otherwise, returning error information and exiting; when the switch specified according to the configuration file selects the required compiling parameters from the template file, the rule for selecting the required compiling parameters is as follows: if the compiling parameters in the template file have switch statement and are consistent with the values of the switches indicated by the configuration file, selecting; when the compiling parameter in the template file has a plurality of switch declarations, the compiling parameter can be selected only when each switch is consistent with the value of the switch indicated by the configuration file.
2. The method of claim 1, wherein the compiling parameters of all different platforms and different functional requirements recorded in the template file specifically include macro definitions, parameter assignments, file lists, compiling options that can be directly identified by the compiling tool of the target platform.
3. The method of claim 1, wherein each switch includes a switch name and a state quantity when determining the switch for each compiled parameter in the template file, the state quantity including a value to which the switch is set to on or off, in the sense of a configuration to turn on or off a function defined by the switch name.
4. The method according to claim 1, wherein the logic relationship specifically refers to a logic relationship in which state quantities of switches are regarded as logical true values and false values, and a logic expression of a binary logic variable is used to represent the correlation between the switches.
5. The method according to claim 1, wherein the validity check is performed on a switch specified in a configuration file and a value thereof, values of all logical expressions in the check rule file are true values, and only configuration files passing the validity check are valid configuration files.
6. The method of claim 1, wherein the returning the error message comprises returning a specific logical expression in the rule file whose value is not true.
7. A configurable system level verification environment construction system comprising a computer device, characterized in that the computer device is programmed or configured to perform the steps of the configurable system level verification environment construction method of any one of claims 1 to 6, or a computer program programmed or configured to perform the configurable system level verification environment construction method of any one of claims 1 to 6 is stored in a memory of the computer device.
8. A computer-readable storage medium having stored therein a computer program programmed or configured to perform the configurable system-level verification environment construction method of any one of claims 1 to 6.
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| CN202010710253.3A CN111859833B (en) | 2020-07-22 | Configurable system level verification environment construction method, system and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107480327A (en) * | 2017-07-03 | 2017-12-15 | 北京东土军悦科技有限公司 | A kind of emulation verification method, device and electronic equipment |
| CN108536581A (en) * | 2018-03-08 | 2018-09-14 | 华东师范大学 | Formalization verification method and system when a kind of operation for source code |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107480327A (en) * | 2017-07-03 | 2017-12-15 | 北京东土军悦科技有限公司 | A kind of emulation verification method, device and electronic equipment |
| CN108536581A (en) * | 2018-03-08 | 2018-09-14 | 华东师范大学 | Formalization verification method and system when a kind of operation for source code |
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