CN111859833A - Configurable system level verification environment construction method, system and medium - Google Patents
Configurable system level verification environment construction method, system and medium Download PDFInfo
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- CN111859833A CN111859833A CN202010710253.3A CN202010710253A CN111859833A CN 111859833 A CN111859833 A CN 111859833A CN 202010710253 A CN202010710253 A CN 202010710253A CN 111859833 A CN111859833 A CN 111859833A
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Abstract
The invention discloses a configurable system level verification environment construction method, which is used for constructing and generating a system level verification environment of an integrated circuit chip and comprises the following steps: recording compiling parameters of all different platforms and different functional requirements during system level verification of the design to be tested into a template file; determining a switch for each compilation parameter in the template file; recording all logic relations among the switches by using a rule file; providing a configuration file according to the specific functions required, and indicating the required switches and values thereof; applying the rule file to the configuration file for validity check, and selecting a required compiling parameter from the template file according to a switch specified by the configuration file if the check is passed; otherwise, returning error information and exiting. The invention can meet the requirements of different verification platforms and different verification functions, and has the advantages of good reliability, easy use, flexible configuration, difficult error and convenient reuse.
Description
Technical Field
The invention relates to integrated circuit chip verification technology, in particular to a configurable system-level verification environment construction method, a system and a medium.
Background
When the system level verification is performed on an integrated circuit chip, simulation verification is usually performed on design codes of the chip on a plurality of different verification platforms (such as hardware simulators, soft simulation and FPGA), and requirements of tools on the design codes are different according to the characteristics of the verification platforms, so that different compiling parameters including different macro definitions, parameter assignment, file lists and compiling options are required to be used by some design modules on different verification platforms. Even aiming at the same platform, partial modules in the chip design are replaced by functional models, null models or components with certain specific behaviors according to verification requirements, and when different functions are used, the compiling parameters are different.
In order to meet the requirements of different verification platforms and different verification functions, multiple sets of macro definitions, parameter assignments, file lists and compiling option files can be maintained at the same time, but the defects are that verification personnel are required to maintain respective files, the verification process is difficult to manage uniformly, confusion and errors are easy to occur, and the reuse is not facilitated.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention can meet the requirements of different verification platforms and different verification functions, and has the advantages of good reliability, easy use, flexible configuration, difficult error and convenient reuse.
In order to solve the technical problems, the invention adopts the technical scheme that:
a configurable system-level verification environment construction method for constructing a system-level verification environment for generating integrated circuit chips, the method comprising:
recording compiling parameters of all different platforms and different functional requirements during system level verification of the design to be tested into a template file;
determining a switch for each compilation parameter in the template file;
recording all logic relations among the switches by using a rule file;
providing a configuration file according to the specific functions required, and indicating the required switches and values thereof;
applying the rule file to the configuration file for validity check, and selecting a required compiling parameter from the template file according to a switch specified by the configuration file if the check is passed; otherwise, returning error information and exiting.
Optionally, the compiling parameters of all different platforms and different functional requirements recorded in the template file specifically include macro definitions, parameter assignments, file lists, and compiling options that can be directly recognized by a compiling tool of the target platform.
Optionally, when determining a switch for each compiling parameter in the template file, each switch includes a switch name and a state quantity, where the state quantity includes a value that the switch is set to be on or off, meaning a configuration that a function defined by the switch name is turned on or off.
Optionally, the logical relationship specifically refers to a logical relationship in which the state quantities of the switches are regarded as a logical true value and a logical false value, and a logical expression of a binary logical variable is used to represent the correlation between the switches.
Optionally, the rule file contains a set of logic expressions with switch names as logic variables, the logic expressions fully embody constraints existing in design code, verification platform, and verification function, and all logic expressions in the rule file must be kept true.
Optionally, the validity check is to check all values of the logic expressions in the rule file to be true values for the specified switches and values thereof in one configuration file, and only the configuration file that passes the validity check is a valid configuration file.
Optionally, when the required compiling parameter is selected from the template file according to the switch specified by the configuration file, the rule for selecting the required compiling parameter is as follows: if the compiling parameters in the template file have switch declarations and are consistent with the values of the switches indicated by the configuration file, the compiling parameters are selected; when the compiling parameter in the template file has a plurality of switch declarations, the compiling parameter is selected only when each switch is consistent with the value of the switch indicated by the configuration file.
Optionally, the error information is returned by including a specific logic expression whose value is not true in the return rule file.
In addition, the invention also provides a configurable system level verification environment construction system, which comprises a computer device programmed or configured to execute the steps of the configurable system level verification environment construction method, or a computer program programmed or configured to execute the configurable system level verification environment construction method is stored in a memory of the computer device.
Furthermore, the present invention also provides a computer-readable storage medium having stored therein a computer program programmed or configured to perform the configurable system-level verification environment construction method.
Compared with the prior art, the invention has the following advantages: the system-level verification environment can be uniformly and effectively managed, the flexibility is high, the verification environment can be configured according to specific verification requirements, the use is convenient for users, errors are not easy to occur, and the requirements of a plurality of verification platforms and different verification functions are well met. The invention can meet the requirements of different verification platforms and different verification functions, and has the advantages of good reliability, easy use, flexible configuration, difficult error and convenient reuse.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
The configurable system-level verification environment construction method of the present embodiment is used for constructing a system-level verification environment for generating an integrated circuit chip, as shown in fig. 1, the method of the present embodiment includes:
recording compiling parameters of all different platforms and different functional requirements during system level verification of the design to be tested into a template file;
determining a switch for each compilation parameter in the template file;
recording all logic relations among the switches by using a rule file;
providing a configuration file according to the specific functions required, and indicating the required switches and values thereof;
applying the rule file to the configuration file for validity check, and selecting a required compiling parameter from the template file according to a switch specified by the configuration file if the check is passed; otherwise, returning error information and exiting.
In this embodiment, the compiling parameters of all different platforms and different functional requirements recorded in the template file specifically include macro definitions, parameter assignments, file lists, and compiling options that can be directly identified by a compiling tool of the target platform. In this embodiment, the compiling parameters are divided into two types, that is, the compiling parameters that must be used and the compiling parameters that are used under specific conditions need to be declared to be single or multiple switches and values in the template file.
By macro definition, parameter assignment, file list and compiling options, the compiling parameters of all different platforms and different functional requirements can be customized, so that the aims of meeting the requirements of different verification platforms and different verification functions are fulfilled.
In this embodiment, when determining a switch for each compiling parameter in the template file, each switch includes a switch name and a state quantity, where the state quantity includes a value that the switch is set to be on (on) or off (off), and means a configuration for turning on or off a function defined by the switch name. The template file is determined according to all verification platforms and macro definitions, file lists, parameter assignments and compiling options required by verification functions during system level verification of the design to be tested, and if each macro definition, file list, parameter assignment and compiling option in the template file is only started under a specific function, a corresponding switch statement exists.
In this embodiment, the template file contains compilation parameters required by all platforms and all functions for system verification, and each compilation parameter may not declare a switch or declare a switch and its value. If a switch is not asserted, the compiled parameters are always useful and will appear in the final verification environment under all configuration conditions; if a switch or switches are asserted, the compiled parameters will only appear in the final verification environment if the switch values equal the asserted values.
The switches that have been declared in the template file, if there is an association relationship, then this relationship is recorded to the rule file with a logical expression. In this embodiment, the logical relationship specifically refers to a logical relationship in which the state quantities (on and off) of the switches are regarded as a logical true value and a logical false value, and a logical expression of binary logical variables is used to represent the correlation between the switches. The logical relationship refers to the correlation relationship between the switches. Since the values on and off of the switches can be regarded as logic true values and logic false values, the relationship between the switches can be represented by a logic expression of a binary logic variable. The logical operators that can be used to describe the logical relationship in this embodiment include logical implications, logical and, logical not, logical or. For example, the switch of module a using the NULL model in the design code is a _ NULL, the switch of module B using the NULL model is B _ NULL, and if it is agreed that a and B must use the NULL model simultaneously in the design code, there is a logical relationship that a _ NULL implies B _ NULL and B _ NULL implies a _ NULL.
In this embodiment, the rule file includes a set of logic expressions using switch names as logic variables, the logic expressions completely embody constraints existing in design codes, verification platforms, and verification functions, and all the logic expressions in the rule file must be maintained as true.
In this embodiment, the configuration file is specifically an instruction file that instructs a group of switches and values thereof, and is provided by a user. For specifying the authentication platform used by the user and the system level authentication functions to be used by the user. And the user determines the switch and the value thereof to form a configuration file according to the required function and the target verification platform.
In this embodiment, the validity check specifically includes checking that all values of the logic expressions in the rule file are true values for the specified switches and values thereof in one configuration file, and only the configuration file that passes the validity check is a valid configuration file. And (3) substituting the switch values in the configuration file defined by the user into the logic expressions in the rule file by using a computer program, if all the logic expressions are true, passing the validity check, and if not, returning the logic expressions with the results not true to the user.
In this embodiment, when the required compiling parameter is selected from the template file according to the switch specified by the configuration file, the rule for selecting the required compiling parameter is as follows: if the compiling parameters in the template file have switch declarations and are consistent with the values of the switches indicated by the configuration file, the compiling parameters are selected; when the compiling parameter in the template file has a plurality of switch declarations, the compiling parameter is selected only when each switch is consistent with the value of the switch indicated by the configuration file. In the dead course, a computer program is used for reading in the switches and the values thereof in the configuration file, reading the switch declarations corresponding to the compiling parameters from the template file, and if each switch of the switch declarations and the values thereof are consistent with those specified in the configuration file, the compiling parameters are reserved. If the compile parameter does not assert the switch, it is directly retained.
In this embodiment, the error information is returned by including a specific logical expression whose value is not true in the return rule file, so that the error information is obtained for debugging and modifying.
In addition, the embodiment also provides a configurable system-level verification environment constructing system, which includes a computer device, where the computer device is programmed or configured to execute the steps of the configurable system-level verification environment constructing method, or a computer program, which is programmed or configured to execute the configurable system-level verification environment constructing method, is stored in a memory of the computer device.
Furthermore, the present embodiment also provides a computer-readable storage medium, in which a computer program programmed or configured to execute the configurable system-level verification environment constructing method is stored.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. A configurable system-level verification environment construction method for constructing a system-level verification environment for generating integrated circuit chips, the method comprising:
recording compiling parameters of all different platforms and different functional requirements during system level verification of the design to be tested into a template file;
determining a switch for each compilation parameter in the template file;
recording all logic relations among the switches by using a rule file;
providing a configuration file according to the specific functions required, and indicating the required switches and values thereof;
applying the rule file to the configuration file for validity check, and selecting a required compiling parameter from the template file according to a switch specified by the configuration file if the check is passed; otherwise, returning error information and exiting.
2. The configurable system-level verification environment construction method according to claim 1, wherein the compilation parameters of all different platforms and different functional requirements recorded in the template file specifically include macro definitions, parameter assignments, file lists, and compilation options that can be directly recognized by a compilation tool of a target platform.
3. The configurable system-level verification environment construction method according to claim 1, wherein when determining switches for each compiled parameter in the template file, each switch comprises a switch name and a state quantity, wherein the state quantity comprises a value that the switch is set to be on or off, meaning a configuration that turns on or off a function defined by the switch name.
4. The method according to claim 1, wherein the logical relationship is specifically that the state quantities of the switches are regarded as logical true values and false values, and the logical relationship of the correlation between the switches is represented by a logical expression of binary logical variables.
5. The configurable system-level verification environment construction method according to claim 1, wherein the rule file contains a set of logic expressions with switch names as logic variables, the logic expressions fully embody the constraints existing in design code, verification platform and verification function, and all logic expressions in the rule file must be kept true.
6. The method according to claim 1, wherein the validity check is specifically for the switches and their values specified in a configuration file, and the values of all logic expressions in the check rule file are true values and can pass the check, and only the configuration file that passes the validity check is a valid configuration file.
7. The configurable system-level verification environment construction method according to claim 1, wherein when the required compilation parameter is selected from the template file according to the switch specified by the configuration file, the rule for selecting the required compilation parameter is: if the compiling parameters in the template file have switch declarations and are consistent with the values of the switches indicated by the configuration file, the compiling parameters are selected; when the compiling parameter in the template file has a plurality of switch declarations, the compiling parameter is selected only when each switch is consistent with the value of the switch indicated by the configuration file.
8. The configurable system-level verification environment construction method according to claim 1, wherein the return of the error information comprises a return of a specific logical expression in a rule file whose value is not true.
9. A configurable system-level verification environment construction system comprising a computer device, wherein the computer device is programmed or configured to perform the steps of the configurable system-level verification environment construction method of any of claims 1-8, or wherein a memory of the computer device has stored therein a computer program programmed or configured to perform the configurable system-level verification environment construction method of any of claims 1-8.
10. A computer-readable storage medium having stored thereon a computer program programmed or configured to perform the configurable system-level verification environment construction method of any of claims 1-8.
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| CN115562719A (en) * | 2022-12-06 | 2023-01-03 | 中国人民解放军国防科技大学 | Interface-aware compiling configuration item completion method, system and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115562719A (en) * | 2022-12-06 | 2023-01-03 | 中国人民解放军国防科技大学 | Interface-aware compiling configuration item completion method, system and medium |
| CN115562719B (en) * | 2022-12-06 | 2023-04-07 | 中国人民解放军国防科技大学 | Interface-aware compiling configuration item completion method, system and medium |
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