CN111857994A - High-precision timer scheduling method, device, equipment and readable medium - Google Patents
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Abstract
The invention discloses a high-precision timer scheduling method, which comprises the following steps: creating a group of fast timers and a group of slow timers, and enabling the queue duration of each slow timer to be equal to the queue duration of each group of fast timers; in response to receiving a create timer event instruction, determining whether a timing duration of a timer event is within a set of fast timer ranges; responding to the situation that the timing duration is not in the range of a group of fast timers, judging the queue ordinal number of the timing duration in the queue of the slow timer, and inserting a timer event into the slow timer corresponding to the queue ordinal number; and polling the slow timer queues, successively converting each slow timer queue to be processed into a set of fast timer queues, and triggering a timer event in response to a timeout from polling to the timer event. The invention also discloses a high-precision timer scheduling device, computer equipment and a readable storage medium. The invention realizes nanosecond precision, improves task scheduling precision and reduces errors.
Description
Technical Field
The invention relates to the technical field of high-precision timers, in particular to a method, a device, equipment and a readable medium for scheduling a high-precision timer.
Background
In computer software systems, the scheduling of timer events is a common technique. The timer event is used for processing tasks which need to be executed after a period of time, and the tasks can be disposable or periodic, and respectively correspond to a disposable timer and a periodic timer.
The precision of a general timer is generally in the order of milliseconds, which means that the error is also in the order of milliseconds. For tasks in conventional software systems, scheduling errors in milliseconds are not a problem. However, in a software system with high requirements on performance or real-time performance, the error in milliseconds cannot be tolerated.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for scheduling a high-precision timer, where a slow clock and a fast clock are defined based on a CPU clock number, so as to achieve nanosecond precision, improve task scheduling precision, and reduce errors.
Based on the above object, an aspect of the embodiments of the present invention provides a method for scheduling a high-precision timer, including the following steps: creating a group of fast timers and a group of slow timers, and enabling the queue duration of each slow timer to be equal to the queue duration of each group of fast timers; in response to receiving a create timer event instruction, determining whether a timing duration of a timer event is within a set of fast timer ranges; responding to the situation that the timing duration is not in the range of a group of fast timers, judging the queue ordinal number of the timing duration in the queue of the slow timer, and inserting a timer event into the slow timer corresponding to the queue ordinal number; and polling the slow timer queues and successively converting each pending slow timer queue into a set of fast timer queues, triggering a timer event in response to a timeout from polling to the timer event.
In some embodiments, further comprising: responding to the fact that the timing duration is within a group of fast timers, judging a queue ordinal number of the timing duration in a fast timer queue, and inserting a timer event into the fast timer corresponding to the queue ordinal number; a fast timer queue is polled to trigger a timer event in response to a timeout from polling to the timer event.
In some embodiments, creating a set of fast timers and a set of slow timers such that one slow timer queue duration is equal to a set of fast timer queue durations comprises: defining a scheduling unit based on a clock of a CPU, and establishing a fast timer and a slow timer by taking the scheduling unit as a basic unit; creating a timer with the length of 1024 basic units as a fast timer, wherein a group of fast timers comprises 128 fast timers; the timer created is 128 x 1024 basic units long is recorded as one slow timer, and a group of fast timers contains 128 slow timers.
In some embodiments, determining whether the timing duration of the timer event is within a set of fast timer ranges comprises: defining the difference value between the overtime time and the initial time of the timer event as the timing duration of the timer event; it is determined whether the timing duration of the timer event is within a set of fast timer ranges.
In some embodiments, successively converting each pending slow timer queue into a set of fast timer queues includes: in response to the round-robin training to the first slow timer queue, converting the first slow timer queue to a set of fast timer queues; the second slow timer queue is converted to a set of fast timer queues in response to processing completing the set of fast timer queues to which the first slow timer queue is converted.
In another aspect of the embodiments of the present invention, a device for scheduling a high-precision timer is further provided, including: the timer creating module is configured for creating a group of fast timers and a group of slow timers, so that the queue time of each slow timer is equal to the queue time of each group of fast timers; a first determining module configured to determine whether a timing duration of a timer event is within a set of fast timers in response to receiving a create timer event instruction; the second judging module is configured to respond to the fact that the timing duration is not within the range of the fast timers, judge the queue ordinal number of the timing duration in the queue of the slow timer, and insert the timer event into the slow timer corresponding to the queue ordinal number; and a processing module configured to poll the slow timer queues and successively convert each slow timer queue to be processed into a set of fast timers, triggering a timer event in response to a timeout from the polling to the timer event.
In some embodiments, further comprising: and the third judging module is configured to respond to the fact that the timing duration is within a group of fast timers, judge the queue ordinal number of the timing duration in the fast timer queue, and insert the timer event into the fast timer corresponding to the queue ordinal number.
In some embodiments, the third determining module is further configured to: a fast timer queue is polled to trigger a timer event in response to a timeout from polling to the timer event.
In some embodiments, the timer creation module is further configured to: defining a scheduling unit based on a clock of a CPU, and establishing a fast timer and a slow timer by taking the scheduling unit as a basic unit; creating a timer with the length of 1024 basic units as a fast timer, wherein a group of fast timers comprises 128 fast timers; the timer created is 128 x 1024 basic units long is recorded as one slow timer, and a group of fast timers contains 128 slow timers.
In some embodiments, the first determining module is further configured to: defining the difference value between the overtime time and the initial time of the timer event as the timing duration of the timer event; it is determined whether the timing duration of the timer event is within a set of fast timer ranges.
In some embodiments, the processing module is further configured to: in response to the round-robin training to the first slow timer queue, converting the first slow timer queue to a set of fast timer queues; the second slow timer queue is converted to a set of fast timer queues in response to processing completing the set of fast timer queues to which the first slow timer queue is converted.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the timer is organized into a fast timer and a slow timer by taking the CPU clock number as a unit according to the overtime time of the timer, and in the processing process of the round training thread of the timer, the dynamically scheduled timer and the timer scheduled in the mode can realize nanosecond precision, improve the scheduling precision of tasks, reduce errors and improve the efficiency and the real-time property.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram of an embodiment of a method for scheduling a high-precision timer according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a method for high-precision timer scheduling. Fig. 1 is a schematic diagram illustrating an embodiment of a method for scheduling a high-precision timer according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
S1, creating a group of fast timers and a group of slow timers, and enabling the queue duration of each slow timer to be equal to the queue duration of each group of fast timers;
s2, responding to the received command of creating the timer event, and judging whether the timing duration of the timer event is within the range of a group of fast timers;
s3, responding to the fact that the timing duration is not within the range of a group of fast timers, judging the queue ordinal number of the timing duration in the queue of the slow timer, and inserting the timer event into the slow timer corresponding to the queue ordinal number; and
s4, polling the slow timer queues and successively converting each pending slow timer queue into a set of fast timer queues, triggering a timer event in response to a timeout from polling to the timer event.
In this embodiment, with a CPU clock as precision, a scheduling unit is defined as tick, one tick can be defined as several CPU clocks, a group of fast timers and a group of slow timers are created, and each group of timers includes 128 timer queues; in response to receiving the create timer event command, determining whether a timing duration of the timer event is within a set of ticks of a fast timer [0,128 × 1024 ]; if the timing duration is not in the range of ticks of a group of fast timers [0,128 x 1024), judging that the timing duration is in the queue number of the slow timer, if the timing duration is in [0,128 x 1024) ticks, inserting the timing duration into a 1 st slow timer queue, if the timing duration is in [128 x 1024,2 x 128 x 1024) ticks, inserting the timing duration into a 2 nd slow timer queue, and so on; polling the slow timer queues, wherein the timer round training thread is responsible for round training all timers, moving the first slow timer queue to the fast timer queue along with the movement of time points from left to right, and executing a triggered timer event in the circulating processing process.
In some embodiments of the invention, further comprising: responding to the fact that the timing duration is within a group of fast timers, judging a queue ordinal number of the timing duration in a fast timer queue, and inserting a timer event into the fast timer corresponding to the queue ordinal number; a fast timer queue is polled to trigger a timer event in response to a timeout from polling to the timer event.
In this embodiment, if its timing duration is within 0,1024 ticks, the timer is inserted into the 1 st fast timer queue, if the timing duration is within 1024,2048 ticks, the timer is inserted into the 2 nd fast timer queue, and so on.
In some embodiments of the present invention, creating a set of fast timers and a set of slow timers such that one slow timer queue duration is equal to a set of fast timer queue durations comprises: defining a scheduling unit based on a clock of a CPU, and establishing a fast timer and a slow timer by taking the scheduling unit as a basic unit; creating a timer with the length of 1024 basic units as a fast timer, wherein a group of fast timers comprises 128 fast timers; the timer created is 128 x 1024 basic units long is recorded as one slow timer, and a group of fast timers contains 128 slow timers.
Establishing a timer with the length of 1024 basic units as a fast timer, wherein one group of fast timers comprise 128 fast timers, and setting the starting time fast _ start _ time of the fast timers as the clock number of the current CPU; creating a timer with a length of 128 × 1024 basic units as a slow timer, and setting a start time point slow _ start _ time of the slow timer to be +128 × 1024 of the fast timer, wherein a group of fast timers comprises 128 slow timers.
In some embodiments of the present invention, determining whether the timing duration of the timer event is within a set of fast timer ranges comprises: defining the difference value between the overtime time and the initial time of the timer event as the timing duration of the timer event; it is determined whether the timing duration of the timer event is within a set of fast timer ranges.
In this embodiment, the fast timer start time fast _ start _ time is set as the current CPU clock number timer, the fast timer start time is increased by 1024 every time a queue of fast timers is processed when a polling thread polls the timers, and the fast timer start time continuously jumps forward along with the movement of the time, and is increased by 1024 every jump; setting a slow timer starting time point slow _ start _ time as a fast timer starting time point +128 × 1024, increasing the slow timer starting time point by 128 × 1024 every time a queue of slow timers is processed when a polling thread polls the timers, and continuously jumping forward at the fast timer starting time point along with the movement of the time points and increasing by 128 × 1024 every time the queue of slow timers is jumped.
In some embodiments of the invention, successively converting each pending slow timer queue into a set of fast timer queues comprises: in response to the round-robin training to the first slow timer queue, converting the first slow timer queue to a set of fast timer queues; the second slow timer queue is converted to a set of fast timer queues in response to processing completing the set of fast timer queues to which the first slow timer queue is converted.
It should be particularly noted that, the steps in the embodiments of the method for scheduling a high-precision timer can be mutually intersected, replaced, added, and deleted, so that these methods for scheduling a high-precision timer, which are reasonably transformed by permutation and combination, should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the above object, according to a second aspect of the embodiments of the present invention, there is provided an apparatus for scheduling a high-precision timer, including: the timer creating module is configured for creating a group of fast timers and a group of slow timers, so that the queue time of each slow timer is equal to the queue time of each group of fast timers; a first determining module configured to determine whether a timing duration of a timer event is within a set of fast timers in response to receiving a create timer event instruction; the second judging module is configured to respond to the fact that the timing duration is not within the range of the fast timers, judge the queue ordinal number of the timing duration in the queue of the slow timer, and insert the timer event into the slow timer corresponding to the queue ordinal number; and a processing module configured to poll the slow timer queues and successively convert each slow timer queue to be processed into a set of fast timers, triggering a timer event in response to a timeout from the polling to the timer event.
In some embodiments of the invention, further comprising: and the third judging module is configured to respond to the fact that the timing duration is within a group of fast timers, judge the queue ordinal number of the timing duration in the fast timer queue, and insert the timer event into the fast timer corresponding to the queue ordinal number.
In some embodiments of the invention, the third determining module is further configured to: a fast timer queue is polled to trigger a timer event in response to a timeout from polling to the timer event.
In some embodiments of the invention, the timer creation module is further configured to: defining a scheduling unit based on a clock of a CPU, and establishing a fast timer and a slow timer by taking the scheduling unit as a basic unit; creating a timer with the length of 1024 basic units as a fast timer, wherein a group of fast timers comprises 128 fast timers; the timer created is 128 x 1024 basic units long is recorded as one slow timer, and a group of fast timers contains 128 slow timers.
In some embodiments of the invention, the first determining module is further configured to: defining the difference value between the overtime time and the initial time of the timer event as the timing duration of the timer event; it is determined whether the timing duration of the timer event is within a set of fast timer ranges.
In some embodiments of the invention, the processing module is further configured to: in response to the round-robin training to the first slow timer queue, converting the first slow timer queue to a set of fast timer queues; the second slow timer queue is converted to a set of fast timer queues in response to processing completing the set of fast timer queues to which the first slow timer queue is converted.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the above method.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for scheduling a high-precision timer can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for scheduling a high-precision timer is characterized by comprising the following steps:
creating a group of fast timers and a group of slow timers, and enabling the queue duration of each slow timer to be equal to the queue duration of one group of fast timers;
in response to receiving a create timer event instruction, determining whether a timing duration of the timer event is within a set of the fast timer ranges;
responding to the fact that the timing duration is not in the range of a group of fast timers, judging a queue ordinal number of the timing duration in a slow timer queue, and inserting the timer event into a slow timer corresponding to the queue ordinal number; and
Polling the slow timer queues and successively converting each of the slow timer queues to be processed into a set of fast timer queues, triggering the timer event in response to a timeout from polling the timer event.
2. The method for high precision timer scheduling of claim 1, further comprising:
responding to the fact that the timing duration is within a group of fast timers, judging a queue ordinal number of the timing duration in a fast timer queue, and inserting the timer event into the fast timer corresponding to the queue ordinal number;
polling the fast timer queue, triggering the timer event in response to polling the timeout time for the timer event.
3. A method for high accuracy timer scheduling as defined in claim 1 wherein creating a set of fast timers and a set of slow timers such that one of said slow timer queue durations is equal to a set of said fast timer queue durations comprises:
defining a scheduling unit based on a clock of a CPU, and establishing a fast timer and a slow timer by taking the scheduling unit as a basic unit;
creating a timer with the length of 1024 basic units as a fast timer, wherein one group of the fast timers comprises 128 fast timers;
The timer with length of 128 × 1024 basic units is created and recorded as a slow timer, and a group of the fast timers comprises 128 slow timers.
4. A method for high accuracy timer scheduling as defined in claim 1 wherein determining whether the timing duration of the timer event is within a set of the fast timer ranges comprises:
defining the difference value between the overtime time and the starting time of the timer event as the timing duration of the timer event;
and judging whether the timing duration of the timer event is within a group of the fast timers.
5. A method for high precision timer scheduling according to claim 1, wherein successively converting each of the slow timer queues to be processed into a set of fast timer queues comprises:
in response to a round robin to a first slow timer queue, converting the first slow timer queue to the set of fast timer queues;
in response to processing completing the set of fast timer queues to which the first slow timer queue is converted, converting a second slow timer queue to the set of fast timer queues.
6. An apparatus for high precision timer scheduling, comprising:
The timer creating module is configured to create a group of fast timers and a group of slow timers, so that the queue duration of each slow timer is equal to the queue duration of one group of fast timers;
a first determining module configured to determine, in response to receiving a create timer event instruction, whether a timing duration of the timer event is within a set of the fast timer ranges;
a second judging module, configured to respond to that the timing duration is not within a group of fast timers, judge a queue ordinal number of the timing duration in a slow timer queue, and insert the timer event into a slow timer corresponding to the queue ordinal number; and
and the processing module is configured to poll the slow timer queues, successively convert each slow timer queue to be processed into a group of fast timers, and trigger the timer events in response to the timeout time from polling to the timer events.
7. The apparatus for high precision timer scheduling of claim 6, further comprising:
and the third judging module is configured to respond to the fact that the timing duration is within a group of fast timers, judge the queue ordinal number of the timing duration in a fast timer queue, and insert the timer event into the fast timer corresponding to the queue ordinal number.
8. The apparatus for high precision timer scheduling of claim 7, wherein the third determining module is further configured to:
polling the fast timer queue, triggering the timer event in response to polling the timeout time for the timer event.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods 1-5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117056059A (en) * | 2023-10-12 | 2023-11-14 | 常州楠菲微电子有限公司 | Timer realizing method and device, storage medium and electronic equipment |
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| CN1852131A (en) * | 2005-07-06 | 2006-10-25 | 华为技术有限公司 | Timer scheduling method |
| CN109451560A (en) * | 2019-01-08 | 2019-03-08 | 苏州简约纳电子有限公司 | A kind of optimization method at the cell searching interval based on moving velocity of terminal |
| CN110995616A (en) * | 2019-12-06 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Management method and device for large-flow server and readable medium |
| CN111240593A (en) * | 2020-01-06 | 2020-06-05 | 苏州浪潮智能科技有限公司 | Data migration method, device, equipment and medium with dynamic self-adaptive scheduling |
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| CN1852131A (en) * | 2005-07-06 | 2006-10-25 | 华为技术有限公司 | Timer scheduling method |
| CN109451560A (en) * | 2019-01-08 | 2019-03-08 | 苏州简约纳电子有限公司 | A kind of optimization method at the cell searching interval based on moving velocity of terminal |
| CN110995616A (en) * | 2019-12-06 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Management method and device for large-flow server and readable medium |
| CN111240593A (en) * | 2020-01-06 | 2020-06-05 | 苏州浪潮智能科技有限公司 | Data migration method, device, equipment and medium with dynamic self-adaptive scheduling |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117056059A (en) * | 2023-10-12 | 2023-11-14 | 常州楠菲微电子有限公司 | Timer realizing method and device, storage medium and electronic equipment |
| CN117056059B (en) * | 2023-10-12 | 2024-02-02 | 常州楠菲微电子有限公司 | Timer realizing method and device, storage medium and electronic equipment |
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