CN111834467A - Ni compatible with Si processxSiy/Ga2O3Schottky diode and preparation method thereof - Google Patents
Ni compatible with Si processxSiy/Ga2O3Schottky diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims abstract description 107
- 238000000034 method Methods 0.000 claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000010703 silicon Substances 0.000 claims abstract description 52
- 238000000137 annealing Methods 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims abstract description 30
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 24
- 239000003292 glue Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000012298 atmosphere Substances 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 239000010409 thin film Substances 0.000 claims abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 126
- 230000008569 process Effects 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052681 coesite Inorganic materials 0.000 claims description 20
- 229910052906 cristobalite Inorganic materials 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 229910052682 stishovite Inorganic materials 0.000 claims description 20
- 229910052905 tridymite Inorganic materials 0.000 claims description 20
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 238000010894 electron beam technology Methods 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229910017109 AlON Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 239000012300 argon atmosphere Substances 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 3
- 238000000609 electron-beam lithography Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910001020 Au alloy Inorganic materials 0.000 claims description 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims description 2
- 238000000233 ultraviolet lithography Methods 0.000 claims description 2
- 229910000807 Ga alloy Inorganic materials 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 20
- 238000001259 photo etching Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 70
- 238000004151 rapid thermal annealing Methods 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 18
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000012360 testing method Methods 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910007271 Si2O3 Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000003550 marker Substances 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides Ni compatible with Si processxSiy/Ga2O3The Schottky diode and the preparation method thereof are used for forming a Schottky electrode and an ohmic electrode on a marking sheet, the working surface of the marking sheet is provided with a first area, a second area and a third area, and the method comprises the following steps: ga is mixed with2O3A thin film is coated on the first region, and then Ga is coated2O3The surface and the working surface of the film are coated with glue; in Ga2O3Carrying out photoetching and photoresist removal on the surface of the film and the working surface to obtain an anode window; sputtering and depositing Si and Ni at the anode window; rapidly annealing the stripped mark sheet at a preset temperature in an inert atmosphere for a preset time; forming a first region and a third region with Ga2O3Thereby obtaining NixSiy/Ga2O3A schottky diode. Ni produced by the inventionxSiy/Ga2O3The Schottky electrode has lower resistivity and excellent thermal stability, and can prepare Ni with adjustable barrier height under the condition of meeting the compatibility with a silicon processxSiy/Ga2O3The Schottky anode has wide application prospect.
Description
Technical Field
The invention relates to the technical field of ultra-wide bandgap compound semiconductors and the field of Schottky power diodes, in particular to Ni compatible with Si processxSiy/Ga2O3A Schottky diode and a method for manufacturing the same.
Background
In recent years, ultra-wideband gap semiconductor power devices have received increasing attention due to their higher energy conversion efficiency and larger breakdown voltage. And because the Schottky diode has high switching frequency, small forward voltage drop and no reverse recovery time, the Schottky diode can be applied to high-frequency high-power conversion. From Ga2O3Ga made of a material2O3The Schottky diode power device has low conduction loss and switching loss in a high-voltage and high-temperature environment, and therefore has bright application potential. However, most of the reported Ga2O3The Schottky diode power devices all use metal electrodes, and Ga is used2O3The surface forms a metal/semiconductor schottky contact. As compound semiconductor process, Ga2O3The Schottky diode power device only uses metal electrodes with different work functions to contact with the surface of a semiconductor to form an anode and a cathode of the device, and in the manufacturing process of the Schottky anode, the work function of metal is fixed, so that the Schottky barrier is determined to be a fixed value, and the performance improvement of the Schottky diode is limited by fine process adjustment. Ga formed by contacting metal electrode with semiconductor surface2O3The Schottky anode has the defects of higher barrier height, small adjustable range of the barrier height and higher on-state voltage.
Currently, a silicon-based integrated circuit process is the most mature and complex semiconductor manufacturing technology, and if some advantages of the silicon-based integrated circuit process can be applied to a compound process to reconstruct a new structure of a wide bandgap semiconductor device and improve the performance of the device, innovative research work is performed, however, if polysilicon compatible with the silicon process is used as a schottky electrode, the resistivity is greatly improved.
Disclosure of Invention
The present invention has been made to solve the above problems, and an object thereof is to provide Ni compatible with Si processxSiy/Ga2O3Preparation method of Schottky diode and prepared Ni with low barrier heightxSiy/Ga2O3Schottky anode by changing the ratio of Ni to Si in Ga2O3Obtaining Ni of different compositions on the surfacexSiySilicide, and Ga2O3The semiconductor forms a schottky anode with adjustable barrier height.
The invention provides Ni compatible with Si processxSiy/Ga2O3A method for manufacturing a Schottky diode by forming a Schottky electrode and an ohmic electrode on a marking sheet having a first region and a second region adjacent to each other and used for forming the Schottky electrode and a third region adjacent to the first region and forming the ohmic electrode in cooperation with the first region, comprising the steps of:
step one, Ga is mixed2O3A thin film is coated on the first region, and then Ga is coated2O3The surface and the working surface of the film are coated with glue;
step two, in Ga2O3The surface and the working surface of the film are subjected to photoresist removal to obtain an anode window, and a part of the anode window covers Ga2O3An edge portion of the film, another portion covering the second area;
sputtering and depositing silicon on the surface of the anode window to form a silicon layer with a first preset thickness, and then evaporating by using electron beams to form a nickel layer with a second preset thickness on the silicon layer;
step four, removing the glue of the marking sheet;
step five, rapidly annealing the stripped mark sheet for a preset time at a preset temperature in an inert atmosphere so as to form Ni at the anode windowxSiySilicide of the NixSiySilicide and Ga2O3Is formed of NixSiy/Ga2O3The schottky electrode of (1);
step six, manufacturing Ga in the first region and the third region2O3Thereby obtaining NixSiy/Ga2O3A Schottky diode;
wherein, the first preset thickness in the third step is 20 nm-100 nm, the second preset thickness is 40 nm-200 nm, and the first preset thickness is smaller than the second preset thickness.
The preset temperature in the step five is 400-650 ℃, and the preset time is 40-60 s.
The Ni compatible with Si process provided by the inventionxSiy/Ga2O3The method for manufacturing the schottky diode can also have the following characteristics that: wherein has Ga2O3The method for manufacturing the ohmic electrode comprises the following steps:
in the presence of NixSiy/Ga2O3The surface and the working surface of the Schottky electrode are coated with glue, and Ga is coated on the Schottky electrode2O3The surface and the working face of the film are etched to remove the photoresist to obtain a cathode window, and Ga with Ti/Al/Ni/Au alloy is manufactured at the cathode window2O3The cathode window partially covers Ga2O3The edge part of the film and the other part cover the third area.
Ni compatible with Si process provided in the inventionxSiy/Ga2O3The method for manufacturing the schottky diode can also have the following characteristics that: wherein the marking sheet is made of sapphire, Si, Ge, GaN, SiO2/Si、Al2O3/Si、HfO2/Si, AlN/Si, AlON/Si or ZrO2Any one of the following compounds,/Si.
In the inventionProvided Ni compatible with Si processxSiy/Ga2O3The method for manufacturing the schottky diode can also have the following characteristics that: wherein the lithography in step two and in claim 2 is electron beam lithography or ultraviolet lithography.
Ni compatible with Si process provided in the inventionxSiy/Ga2O3The method for manufacturing the schottky diode can also have the following characteristics that: wherein the silicon is polysilicon or amorphous silicon.
Ni compatible with Si process provided in the inventionxSiy/Ga2O3The method for manufacturing the schottky diode can also have the following characteristics that: wherein the predetermined temperature in the step five is 600-650 ℃.
Ni compatible with Si process provided in the inventionxSiy/Ga2O3The method for manufacturing the schottky diode can also have the following characteristics that: wherein the inert atmosphere is nitrogen atmosphere or argon atmosphere.
The invention also provides Ni compatible with Si processxSiy/Ga2O3Schottky diode, characterized by being made of Ni compatible with Si processxSiy/Ga2O3The preparation method of the Schottky diode is provided.
Action and Effect of the invention
Ni compatible with Si process provided according to the inventionxSiy/Ga2O3In the preparation method of the Schottky diode, the first step to the fifth step are used for preparing the Schottky diode with NixSiyNi of silicidexSiy/Ga2O3Schottky electrode of the NixSiy/Ga2O3Schottky acts as an anode with lower resistivity and lower barrier height. In the third step, the thickness of the silicon layer is 20 nm-100 nm, the thickness of the nickel layer is 40 nm-200 nm, and the thickness of the silicon layer is less than that of the nickel layer, so that the silicon can be ensured to be completely combined with the nickel after annealing, and Ga is obtained by adjusting different proportions of Ni and Si2O3Obtaining different components Ni on the surfacexSiySilicide to form Schottky anode with adjustable barrier height, and Ni can be controlled by diffusion of NixSiyIs performed. Compared with a polycrystalline silicon or amorphous silicon schottky electrode, the consumption of silicon is less due to the participation of Ni.
Because the annealing temperature in the fifth step is 400-650 ℃ and the annealing time is 40-60 s, compared with the traditional Schottky electrode, Ni is adoptedxSiy/Ga2O3The Schottky electrode has the advantages of low annealing temperature and high stability.
Preparing ohmic electrode as cathode in the sixth step, and preparing Ni in the first to fifth stepsxSiy/Ga2O3Schottky anodes together forming NixSiy/Ga2O3Schottky diode due to NixSiy/Ga2O3The Schottky anode has low resistivity and low barrier height, so that Ni is added when the resistivity of the ohmic electrode is not changed greatlyxSiy/Ga2O3The Schottky diode has lower on-resistance and excellent thermal stability. In step three in Ga2O3Depositing a silicon layer with a certain thickness on the surface of the film, and depositing a nickel layer with a certain thickness on the silicon layer, thereby realizing NixSiyThe Schottky electrode manufacturing process is compatible with the silicon process, the silicon-based integrated circuit process is the most mature and complicated semiconductor manufacturing technology, and the advantages of the silicon process are applied to Ga2O3In the compound process for manufacturing the Schottky diode, a new structure of the wide bandgap semiconductor device is reconstructed, and the performance of the diode is improved.
Therefore, the invention has the characteristics of cost saving, high process preparation reliability and strong repeatability, and the Ni prepared according to the inventionxSiy/Ga2O3The Schottky electrode has lower resistivity and excellent thermal stability, so that the invention can prepare Ni with adjustable barrier height under the condition of meeting the compatibility with a silicon processxSiy/Ga2O3The Schottky anode has wide application prospect.
Drawings
FIG. 1 shows Ga in example 1 of the present invention2O3With SiO2A position relation diagram of the/Si double-layer mark sheet;
FIG. 2 shows Ga in example 1 of the present invention2O3A picture of anodic exposure;
FIG. 3 shows Ga in example 1 of the present invention2O3Structure change graphs of the laminated anode before and after rapid thermal annealing (RTP);
FIG. 4 shows Ga after rapid thermal annealing in example 1 of the present invention2O3Microscopic electron probe (EDX) spectra of the stacked anodes;
FIG. 5 shows Ga in example 1 of the present invention2O3A picture of the cathode exposure;
FIG. 6 shows Ga in example 1 of the present invention2O3A schematic structural diagram of the laminated cathode before rapid thermal annealing (RTP); and
FIG. 7 shows Ga in example 1 of the present invention2O3Schematic structure of the laminated cathode after rapid thermal annealing (RTP).
Detailed Description
In order to make the technical means, creation features, achievement objects and effects of the present invention easy to understand, the following embodiments and drawings are used to illustrate a Ni compatible with Si process of the present inventionxSiy/Ga2O3The Schottky diode and the method for manufacturing the same are described in detail.
< example 1>
Ni compatible with Si processxSiy/Ga2O3The manufacturing method of the Schottky diode comprises the following steps:
step one, Ga is mixed2O3The film covers the working surface of the marking sheet, and the working surface is completely coated with glue.
In this embodiment, the specific operation of step one is as follows:
selecting SiO2/Si double-layer markThe marking piece of this example was made of SiO2The face serves as a working face having a first region and a second region adjoining each other and a third region adjoining the first region and cooperating therewith.
Will be derived from Ga2O3The area torn off from the single crystal was 3X 20 μm2Ga of (2)2O3Mechanical transfer of the film to an area of 1X 1cm2SiO of (2)2SiO of/Si double-layer marking sheet2On the surface with SiO2Use of/Si bilayer tags as Ga2O3The support body of the film is coated with glue on the working surface uniformly and baked for 2-5min on a hot plate at 140-. Preferably, the baking is carried out on a hotplate at 170 ℃ for 3 min.
In other embodiments, the marker chip may be a single-layer marker chip of any one of sapphire, Si, Ge or GaN, or SiO2/Si、Al2O3/Si、HfO2/Si, AlN/Si, AlON/Si or ZrO2Any one of the two-layer marking sheets of/Si. Wherein, the working surface of the double-layer marking sheet can be SiO2Flour, Al2O3Face, HfO2i-plane, AlN plane, AlON plane or ZrO plane2The surface may be an Si surface.
FIG. 1 shows Ga in example 1 of the present invention2O3With SiO2A positional relationship diagram of the/Si double-layer mark sheet.
As shown in FIG. 1, SiO2SiO of/Si double-layer marking sheet2The surface is a working surface, Ga2O3The film is placed on SiO2SiO of/Si double-layer marking sheet2A first region of the face.
Step two, in Ga2O3The surface and the working surface of the film are subjected to photoresist removal to obtain an anode window, and a part of the anode window covers Ga2O3An edge portion of the film, another portion covering the second area.
In this embodiment, the specific operation of step two is as follows:
in Ga2O3One end of the film is exposed to an area of 3X 3 μm by removing photoresist with electron beam2Of (2)Anode electrode window, also in SiO2SiO of/Si double-layer marking sheet2The photoresist is removed by electron beam on the surface to expose the surface with an area of 100 × 100 μm2The anode test window of the device for testing is formed, and then a rectangular connecting band is formed by using electron beam resist removing exposure to connect the two windows together, thereby forming the anode window. Then the electron beam is used for photoetching the stripped SiO2the/Si bilayer marker plate was immersed in the developer for 1min to develop the anode window, followed by development in isopropanol for 1 min. In this example, the developing solution used was a general commercially available developing solution.
FIG. 2 shows Ga in example 1 of the present invention2O3And (4) anode exposure. Wherein A is a top view after exposure and B is along Ga2O3Cross-sectional view in the direction of the middle line of the short side of the sheet.
As shown in fig. 2, the device anode electrode window is connected with the device anode test window through a rectangular connecting band to form an anode window, the glue coating at the anode window is peeled off, and the rest part of the working surface without photoetching is still covered by the glue coating.
And step three, sputtering and depositing silicon on the surface of the anode window to form a silicon layer with a first preset thickness, and then forming a nickel layer with a second preset thickness on the silicon layer by electron beam evaporation. Wherein the first predetermined thickness is less than the second predetermined thickness.
In this embodiment, the specific operation of step three is as follows:
the developed SiO2the/Si double-layer marking sheet is placed in a physical vapor deposition device, silicon is sputtered and deposited to form a silicon layer with the thickness of 20-100nm, then nickel is immediately evaporated by electron beams, and a nickel layer with the thickness of 40-200nm is formed on the silicon layer, so that the Ni/Si laminated layer is obtained. In the embodiment, the silicon is n-type amorphous silicon, the thickness of the silicon layer is 50nm, and the thickness of the nickel layer is 100 nmn; in other embodiments, the silicon may be p-type amorphous silicon, n-type polycrystalline silicon, or p-type polycrystalline silicon.
And step four, removing the glue of the marking sheet.
In this embodiment, the specific operation of step four is to use SiO2the/Si double-layer mark sheet is stripped by acetone.
Step five, rapidly annealing the stripped mark sheet for a preset time at a preset temperature in an inert atmosphere so as to form Ni at the anode windowxSiySilicide of the NixSiySilicide and Ga2O3Is formed of NixSiy/Ga2O3The schottky electrode of (1).
In this embodiment, the specific operation of step five is as follows:
removing the photoresist from the SiO2Putting the/Si double-layer mark sheet into a rapid thermal annealing furnace, and completely converting the Ni/Si laminated layer into Ni after rapid thermal annealing (RTP) in a nitrogen or argon atmospherexSiySilicide, and it and Ga2O3The semiconductor forms a Schottky contact to obtain Ni as an anodexSiy/Ga2O3Schottky electrode, then measuring NixSiyResistivity measurement of thin films and NixSiy/Ga2O3The barrier height of the Schottky electrode is tested to obtain NixSiyThe resistivity of the film is 3 to 7 omega/□, and the barrier height is 0.7 to 0.8 eV. The annealing temperature is preferably 600-650 ℃, and the annealing time is preferably 40-60 s. More preferably, the annealing temperature is 600 ℃ and the annealing time is 50 s. In this example, Ni was obtained by testingxSiyThe resistivity of the film is 5 omega/□, NixSiy/Ga2O3The barrier height of the schottky electrode was 0.74 eV. In other embodiments, Ga is modified by changing the ratio of Ni to Si2O3Obtaining Ni with different components on the surfacexSiyAnd a compound to form schottky electrodes having different barrier heights.
FIG. 3 shows Ga in example 1 of the present invention2O3Structural change of the laminated anode before and after rapid thermal annealing (RTP). Wherein A is Ga2O3The structure of the laminated anode before RTP is shown in the specification, B is Ga2O3Schematic structural diagrams of the laminated anode before and after RTP.
As shown in A in FIG. 3, before annealing, n-type amorphous silicon is deposited on the anode of the deviceGa of polar window2O3The surface of the amorphous silicon layer is formed with a thickness of 50nm, Ni is deposited on the surface of the amorphous silicon layer to form a nickel layer with a thickness of 100nmn, and the two layers form a Ni/Si laminated layer. After annealing, the Ni/Si stack is converted to NixSiyCompound deposited on Ga2O3With Ga2O3The semiconductor forms a schottky contact.
FIG. 4 shows Ga after rapid thermal annealing in example 1 of the present invention2O3Microscopic electron probe (EDX) spectra of the stacked anodes. Wherein the abscissa represents NixSiyThe thickness direction of the silicide film, and the ordinate, represent the composition of each substance in the silicide film.
As shown in FIG. 4, in RTP rapid thermal annealing, Ni reacts with Si to form Ni at the Ni/Si interfacexSiyOne side of the film is used as an active atom to diffuse into the n-type amorphous silicon layer, the diffusion of the nickel element at high temperature accelerates the combination reaction, the silicon layer with the thickness of only 50nm is quickly consumed by the nickel layer with the thickness of about 100nm, namely after the rapid thermal annealing RTP of 100nmNi/50nm Si, the silicon with the thickness of 50nm does not have the elementary substance state and is completely combined with Ni, thereby ensuring that Ga is combined with Ni completely2O3Only Ni at the surface of the semiconductorxSiy compound material.
Step six, manufacturing Ga in the first region and the third region2O3Thereby obtaining NixSiy/Ga2O3A schottky diode.
In this embodiment, the specific operation of step six is as follows:
in SiO2SiO of/Si double-layer marking sheet2The surface is coated with glue uniformly again and baked for 2-5min on a hot plate at 140-210 ℃. Preferably, the baking is carried out on a hotplate at 170 ℃ for 3 min.
In Ga2O3Exposing the other end of the film with electron beam to remove photoresist to obtain a film with an area of 3 × 3 μm2Cathode window of device in SiO2SiO of/Si double-layer marking sheet2Exposing the surface with electron beam to remove photoresist to obtain a surface area of 100 × 100 μm2Device cathode for testingThe windows are tested and then exposed to an electron beam to remove the photoresist and provide a rectangular connecting strip that connects the two windows together. After electron beam lithography, the marking piece is immersed in a developing solution for 1min to develop a device anode electrode window and a device cathode test window, and then development is carried out in isopropanol for 1 min. In this example, the developing solution used was a general commercially available developing solution.
The SiO after development is carried out2the/Si double-layer marking sheet uses an electron beam evaporation table to evaporate Ti, Al, Ni and Au at a cathode window in sequence by using an electron beam so as to form Ti layer of 20-40nm, aluminum layer of 50-200nm, nickel layer of 20-100nm and Ti/Al/Ni/Au laminated metal of gold layer of 20-100nm, and then the marking sheet is stripped by acetone degumming. In this embodiment, the thicknesses of the titanium layer, the aluminum layer, the nickel layer and the gold layer are 30nm, 100nm, 50nm and 50nm in sequence.
SiO with Ti/Al/Ni/Au laminated metal2the/Si mark sheet is put into a rapid thermal annealing furnace for rapid thermal annealing, the required temperature in the annealing process is set to be 400-600 ℃, the annealing time is set to be 40-90s, and the annealed Ti/Al/Ni/Au laminated metal forms an alloy mutual soluble metal body which is mixed with Ga2O3Ohmic contact is formed by contacting the surface of the semiconductor with Ni as an anodexSiy/Ga2O3Schottky electrodes together forming NixSiy/Ga2O3A schottky diode. The annealing temperature is preferably 470 ℃ and the annealing time is preferably 60 s.
FIG. 5 shows Ga in example 1 of the present invention2O3Cathode exposure pattern. Wherein A is a top view after exposure and B is along Ga2O3Cross-sectional view in the direction of the middle line of the short side of the sheet.
As shown in fig. 5, the device cathode electrode window was joined to the device cathode test window by rectangular joining tape to form a cathode window where the glue layers had all been peeled off and the rest of the non-lithographed work surface was still covered by the glue layer.
FIG. 6 shows Ga in example 1 of the present invention2O3Structure of laminated cathode before rapid thermal annealing (RTP)Intention is.
FIG. 7 shows Ga in example 1 of the present invention2O3Schematic structure of the laminated cathode after rapid thermal annealing (RTP).
As shown in FIGS. 6 and 7, before annealing, a 30nm thick titanium layer, a 100nm thick aluminum layer, a 50nm thick nickel layer and a 50nm thick gold layer were sequentially deposited on Ga in the cathode electrode window of the device2O3The device anode electrode window is a Schottky contact which is formed. After annealing, the stack of Ti/Al/Ni/Au is converted into an alloy and deposited on Ga2O3With Ga2O3The semiconductor forms an ohmic contact while the schottky contact remains a schottky contact.
< comparative example 1>
Si/Ga compatible with Si process2O3In the present comparative example, the steps other than the third step and the fifth step are the same as those in the corresponding step in example 1, and therefore, the method of manufacturing the schottky diode is omitted, and only the third step and the fifth step are described.
And step three, sputtering and depositing silicon on the working surface to form a silicon layer with a third preset thickness.
In this comparative example, the specific operation of step three is as follows:
the developed SiO2the/Si double-layer marking sheet is placed in physical vapor deposition equipment, silicon is sputtered and deposited at an anode window to form a 150nm silicon layer, then nickel is evaporated by electron beams immediately, and a 100 nm-thick nickel layer is deposited and formed on the silicon layer, so that a 100nm Ni/150nm Si laminated structure is obtained. In this comparative example, the silicon is n-type amorphous silicon, and in other comparative examples, the silicon may be p-type amorphous silicon, n-type polycrystalline silicon, or p-type polycrystalline silicon.
Step five, rapidly annealing the stripped mark sheet for a preset time at a preset temperature in an inert atmosphere to form Si/Ga at the anode window2O3A Schottky electrode.
In this comparative example, the specific operation of step five is as follows:
removing the photoresist from the SiO2Putting the/Si double-layer mark sheet into a rapid thermal annealing furnaceAnd performing rapid thermal annealing in a nitrogen or argon atmosphere, wherein the required temperature in the annealing process is set to 400-650 ℃, and the annealing time is set to 60-90 s. After annealing, at the anode window, 100nm Ni/150nm Si laminated structure is annealed to obtain NixSiySilicon compounds and uncombined silicon. After the rapid thermal annealing is finished, the obtained Ni is treatedxSiyAnd (3) measuring the resistivity of the film, wherein the resistivity of the film is more than 50 omega/□. In this comparative example, the annealing temperature is preferably 600 ℃ and the annealing time is 60 seconds.
Because the thickness of Si is 150nm and the thickness of Ni is 100nm, the Si with the thickness of 150nm is not completely consumed in the RTP rapid thermal annealing in the 100nmNi/150nm Si laminated structure except the formed NixSiyThe silicon compound, and also part of the Si present in elemental form, with Ga2O3Together form NiSi/Si/Ga2O3Structure of Si and Ga2O3The interface is a heterojunction and no schottky junction is present.
Effects and effects of the embodiments
Ni compatible with Si Process provided according to the present embodimentxSiy/Ga2O3In the preparation method of the Schottky diode, the first step to the fifth step are used for preparing the Schottky diode with NixSiyNi of silicidexSiy/Ga2O3Schottky electrode of the NixSiy/Ga2O3Schottky acts as an anode with lower resistivity and lower barrier height. In the third step, the thickness of the silicon layer is 20 nm-100 nm, the thickness of the nickel layer is 40 nm-200 nm, and the thickness of the silicon layer is less than that of the nickel layer, so that the silicon can be ensured to be completely combined with the nickel after annealing, and Ga is obtained by adjusting different proportions of Ni and Si2O3Obtaining different components Ni on the surfacexSiySilicide to form Schottky anode with adjustable barrier height, and Ni diffusion to control NixSiyIs performed. Compared with a polycrystalline silicon or amorphous silicon schottky electrode, the consumption of silicon is less due to the participation of Ni.
The annealing temperature in the fifth step is 400-650 DEG CThe annealing time is 40-60 s, so compared with the traditional Schottky electrode, NixSiy/Ga2O3The Schottky electrode has the advantages of low annealing temperature and high stability.
Preparing ohmic electrode as cathode in the sixth step, and preparing Ni in the first to fifth stepsxSiy/Ga2O3Schottky anodes together forming NixSiy/Ga2O3Schottky diode due to NixSiy/Ga2O3The Schottky anode has low resistivity and low barrier height, so that Ni is added when the resistivity of the ohmic electrode is not changed greatlyxSiy/Ga2O3The Schottky diode has lower on-resistance and excellent thermal stability. In step three in Ga2O3Depositing a silicon layer with a certain thickness on the surface of the film, and depositing a nickel layer with a certain thickness on the silicon layer, thereby realizing NixSiyThe Schottky electrode manufacturing process is compatible with the silicon process, the silicon-based integrated circuit process is the most mature and complicated semiconductor manufacturing technology, and the advantages of the silicon process are applied to Ga2O3In the compound process for manufacturing the Schottky diode, a new structure of the wide bandgap semiconductor device is reconstructed, and the performance of the diode is improved.
Therefore, the embodiment has the characteristics of cost saving, high process preparation reliability and strong repeatability, and the Ni prepared by the method provided by the embodimentxSiy/Ga2O3The Schottky electrode has lower resistivity and excellent thermal stability, so that the method provided by the embodiment can prepare Ni with adjustable barrier height under the condition of meeting the compatibility with a silicon processxSiy/Ga2O3The Schottky anode has wide application prospect.
In addition, Ni compares to silicon Schottky electrodexSiy/Ga2O3The Schottky electrode has low resistivity, less Si consumption, and Ni can be controlled by diffusion of NixSiyAnd forming silicide.
In addition, Ni of low barrier height compared to conventional metal Schottky electrodexSiy/Ga2O3Schottky junction is more conventional than Ni/Ga2O3The Schottky junction has lower barrier height, and lower on-resistance can be obtained.
In conclusion, NixSiyThe Schottky electrode can ensure that the working stability, the manufacturing efficiency and the scale of the device are greatly improved under the condition of meeting the lower resistivity.
The above embodiments are preferred examples of the present invention, and are not intended to limit the scope of the present invention.
Claims (8)
1. Ni compatible with Si processxSiy/Ga2O3A method for manufacturing a Schottky diode by forming a Schottky electrode and an ohmic electrode on a marking sheet having a first region and a second region adjacent to each other and forming the Schottky electrode and a third region adjacent to the first region and forming the ohmic electrode in cooperation with the first region, comprising the steps of:
step one, Ga is mixed2O3A thin film is coated on the first region, and then the Ga is coated2O3The surface of the film and the working surface are all coated with glue;
step two, in the Ga2O3The surface of the film and the working surface are subjected to photoresist removal to obtain an anode window, and a part of the anode window covers the Ga2O3An edge portion of the film, another portion covering the second area;
sputtering and depositing silicon on the surface of the anode window to form a silicon layer with a first preset thickness, and then evaporating by using electron beams on the silicon layer to form a nickel layer with a second preset thickness;
step four, removing the glue of the marking sheet;
fifthly, placing the mark sheet after the photoresist is removed in an inert atmosphere at a preset temperatureRapid annealing for a predetermined time to form Ni at the anode windowxSiySilicide of the NixSiySilicide and the Ga2O3Is formed of NixSiy/Ga2O3The schottky electrode of (a);
step six, forming the first region and the third region with the Ga2O3Thereby obtaining NixSiy/Ga2O3A Schottky diode;
wherein, in the third step, the first preset thickness is 20 nm-100 nm, the second preset thickness is 40 nm-200 nm, the first preset thickness is smaller than the second preset thickness,
the preset temperature in the step five is 400-650 ℃, and the preset time is 40-60 s.
2. Ni compatible with Si process according to claim 1xSiy/Ga2O3The preparation method of the Schottky diode is characterized in that:
wherein has the Ga2O3The manufacturing method of the ohmic electrode comprises the following steps:
in the presence of NixSiy/Ga2O3The surface of the Schottky electrode and the working surface are all coated with glue, and the Ga2O3The surface of the film and the working surface are etched and photoresist is removed to obtain a cathode window, and the Ga alloy with the Ti/Al/Ni/Au alloy is manufactured at the cathode window2O3Of the ohmic electrode of (a) a,
a part of the cathode window covers the Ga2O3An edge portion of the film, another portion covering the third area.
3. Ni compatible with Si process according to claim 1xSiy/Ga2O3The preparation method of the Schottky diode is characterized in that:
wherein the marking sheet is made of sapphire, Si, Ge, GaN and SiO2/Si、Al2O3/Si、HfO2/Si, AlN/Si, AlON/Si or ZrO2Any one of the following compounds,/Si.
4. Ni compatible with Si process according to claim 1xSiy/Ga2O3The preparation method of the Schottky diode is characterized in that:
wherein the lithography in the second step and in claim 2 is electron beam lithography or ultraviolet lithography.
5. Ni compatible with Si process according to claim 1xSiy/Ga2O3The preparation method of the Schottky diode is characterized in that:
wherein the silicon is polysilicon or amorphous silicon.
6. Ni compatible with Si process according to claim 1xSiy/Ga2O3The preparation method of the Schottky diode is characterized in that:
wherein the predetermined temperature in the fifth step is 600-650 ℃.
7. Ni compatible with Si process according to claim 1xSiy/Ga2O3The preparation method of the Schottky diode is characterized in that:
wherein the inert atmosphere is nitrogen atmosphere or argon atmosphere.
8. Ni compatible with Si processxSiy/Ga2O3Schottky diode, characterized in that Ni compatible with Si process according to any of claims 1 to 7xSiy/Ga2O3The preparation method of the Schottky diode is provided.
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