CN111834342A - 半导体设备封装及其制造方法 - Google Patents
半导体设备封装及其制造方法 Download PDFInfo
- Publication number
- CN111834342A CN111834342A CN201910514836.6A CN201910514836A CN111834342A CN 111834342 A CN111834342 A CN 111834342A CN 201910514836 A CN201910514836 A CN 201910514836A CN 111834342 A CN111834342 A CN 111834342A
- Authority
- CN
- China
- Prior art keywords
- package
- layer
- antenna
- semiconductor device
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000011521 glass Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 23
- 230000000149 penetrating effect Effects 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000005855 radiation Effects 0.000 claims 3
- 239000010410 layer Substances 0.000 description 228
- 238000002161 passivation Methods 0.000 description 54
- 239000004020 conductor Substances 0.000 description 27
- 239000000463 material Substances 0.000 description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010931 gold Substances 0.000 description 14
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 14
- 238000000465 moulding Methods 0.000 description 14
- 229910045601 alloy Inorganic materials 0.000 description 13
- 239000000956 alloy Substances 0.000 description 13
- 229910052737 gold Inorganic materials 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 229910052763 palladium Inorganic materials 0.000 description 13
- 229910052697 platinum Inorganic materials 0.000 description 13
- 229910052709 silver Inorganic materials 0.000 description 13
- 150000001875 compounds Chemical class 0.000 description 12
- 229910001092 metal group alloy Inorganic materials 0.000 description 12
- 239000010944 silver (metal) Substances 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 7
- 229910001195 gallium oxide Inorganic materials 0.000 description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 description 7
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 7
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 7
- HYXGAEYDKFCVMU-UHFFFAOYSA-N scandium oxide Chemical compound O=[Sc]O[Sc]=O HYXGAEYDKFCVMU-UHFFFAOYSA-N 0.000 description 7
- 229910001928 zirconium oxide Inorganic materials 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- 229920006336 epoxy molding compound Polymers 0.000 description 6
- 239000000945 filler Substances 0.000 description 6
- 150000002989 phenols Chemical class 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 229920002050 silicone resin Polymers 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 208000014903 transposition of the great arteries Diseases 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- -1 prepreg) Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/28—Combinations of substantially independent non-interacting antenna units or systems
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/16—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/214—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
提供了一种半导体设备封装及其制造方法。所述半导体设备封装包含电路层、第一封装体、第一天线和电子部件。所述电路层具有第一表面和与所述第一表面相对的第二表面。所述第一封装体安置在所述电路层的所述第一表面上。所述第一天线穿透所述第一封装体并电连接到所述电路层。所述电子部件安置在所述电路层的所述第二表面上。
Description
技术领域
本公开涉及一种半导体设备封装及其制造方法,并且更具体地涉及包含天线的半导体设备封装及其制造方法。
背景技术
如手机等无线通信设备通常包含用于发射和接收射频(RF)信号的天线。可比较地,无线通信设备包含天线和通信模块,所述天线和所述通信模块各自安置在电路板的不同部分上。在可比较的方法下,天线和通信模块在放置于电路板上之后分开制造并电连接在一起。因此,两个部件可能会引发单独的制造成本。此外,可能难以减小无线通信设备的大小以获得适当紧凑的产品设计。为了降低成本和封装大小,提供了封装天线(AiP)技术。然而,由于工艺限制,难以将偶极天线集成在AiP系统中。
发明内容
根据本公开的一些实施例,一种半导体设备封装包含电路层、第一封装体、第一天线和电子部件。所述电路层具有第一表面和与所述第一表面相对的第二表面。所述第一封装体安置在所述电路层的所述第一表面上。所述第一天线穿透所述第一封装体并电连接到所述电路层。所述电子部件安置在所述电路层的所述第二表面上。
根据本公开的一些实施例,一种半导体设备封装包含导电层、第一封装体以及第一导电元件。所述导电层具有第一表面和与所述第一表面相对的第二表面。所述导电层具有在所述导电层的所述第一表面上的第一天线。所述第一封装体安置在所述导电层的所述第一表面上。所述第一导电元件穿透所述第一封装体并电连接到所述导电层的一部分以限定第二天线。
根据本公开的一些实施例,一种制造光学模块的方法包含:(a)提供载体;(b)在所述载体上方形成具有第一天线的第一导电层;(c)在所述第一导电层上形成导电元件;以及(d)在所述第一导电层上形成第一封装体以覆盖所述导电元件并暴露所述导电元件的顶端。所述导电元件和所述第一导电层的一部分限定第二天线。
附图说明
图1展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图2展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图3展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图4展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图5展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图6A、图6B和图6C展示了根据本公开的一些实施例的半导体制造方法。
图7A、图7B、图7C和图7D展示了根据本公开的一些实施例的半导体制造方法。
图8A、图8B、图8C和图8D展示了根据本公开的一些实施例的半导体制造方法。
贯穿附图和具体实施方式,使用相同的附图标记来指示相同或类似的部件。将从以下结合附图的具体实施方式中容易地理解本公开。
具体实施方式
图1展示了根据本公开的一些实施例的半导体设备封装1的横截面视图。半导体设备封装1包含电路层10、封装体11、12、17、电子部件13以及导电层14、15、16和18。
电路层10包含一或多个互连层(例如,再分布层,RDL)10r和一或多个介电层10d。互连层10r的一部分被介电层10d覆盖或包封,而互连层10r的另一部分从介电层10d暴露以提供电连接。电路层10具有表面101和与表面101相对的表面102。
在一些实施例中,介电层10d可以包含预浸渍复合纤维(例如,预浸料)、硼磷硅酸盐玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂的硅酸盐玻璃(USG)、其两种或两种以上的任何组合等。预浸料的实例可以包含但不限于通过堆叠或层压多种预浸渍材料/片材而形成的多层结构。在一些实施例中,根据设计说明书,可以有任何数量的互连层10r。在一些实施例中,互连层10r由金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、其它一或多种金属或一或多种合金、或其两种或两种以上的组合形成或包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、其它一或多种金属或一或多种合金、或其两种或两种以上的组合。
导电层14安置在电路层10的表面101上并通过连接层10h(例如,焊料)电连接到从介电层10d暴露的互连层10r。导电层14包含互连层14r和覆盖互连层14r的一部分并暴露互连层14r的另一部分以进行电连接的钝化层14p。在一些实施例中,钝化层14p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。互连层14r是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。在一些实施例中,底部填充剂10u安置在电路层10与导电层14之间以覆盖从介电层10d暴露的互连层10r、从钝化层14p暴露的互连层14r以及连接层10h。
封装体11安置在导电层14上。封装体11具有背对导电层14的表面111和与表面111相对的表面112。在一些实施例中,封装体11包含环氧树脂,所述环氧树脂包含填料、模制化合物(例如,环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料、或其组合。一或多个互连结构11p(例如,导电柱或导电元件)穿透封装体11以电连接到导电层14的互连层14r。互连结构11p是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
导电层15安置在封装体11的表面111上并且电连接到互连结构11p。导电层15包含互连层15r1、15r2和钝化层15p。互连层15r1和15r2安置在钝化层15p的表面(所述表面与封装体11的表面111接触)上并且被封装体11覆盖。在一些实施例中,互连层15r1电连接到互连结构11p以限定如偶极天线等天线。在一些实施例中,钝化层15p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。互连层15r2、15r2是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
封装体12安置在导电层15上。封装体12具有背对导电层15的表面121和与表面121相对的表面122。在一些实施例中,封装体12包含环氧树脂,所述环氧树脂包含填料、模制化合物(例如,环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料、或其组合。
在一些实施例中,封装体11的厚度H1大于封装体12的厚度H2。在一些实施例中,封装体11的厚度H1对封装体12的厚度H2的比率约为2:1。在一些实施例中,封装体11的厚度H1等于或大于500微米(μm)。
导电层16安置在封装体12的表面121上。导电层16包含互连层16r和钝化层16p。互连层16r安置在钝化层16p的表面(所述表面与封装体12的表面121接触)上并且被封装体12覆盖。在一些实施例中,互连层16r限定如贴片天线等天线。例如,互连层16r与互连层15r2耦合以在其间进行信号传输。在一些实施例中,钝化层16p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。互连层16r是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
电子部件13安置在电路层10的表面102上。电子部件13可以是如集成电路(IC)芯片或管芯等有源电子部件。在一些实施例中,互连结构10r(例如,RDL)直接地连接到电子部件的有源表面的导电端子(例如,铜柱)。在其它实施例中,电子部件13可以通过倒装芯片或引线结合技术电连接到电路层(例如,电连接到互连层10r)。在一些实施例中,电子部件13的背侧表面通过粘合层(例如,管芯附接薄膜,DAF)结合或附接到导电层18的钝化层18p。
封装体17安置在电路层10的表面102上并且覆盖电子部件13。在一些实施例中,封装体17包含环氧树脂,所述环氧树脂包含填料、模制化合物(例如,环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料、或其组合。一或多个互连结构17p(例如,导电柱或导电元件)穿透封装体17以电连接到电路层10的互连层10r。互连结构17p是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
导电层18安置在封装体17的背对电路层10的表面上。导电层14具有电连接到互连结构17p的互连层18r和覆盖互连层18r的一部分的钝化层18p。互连层18r的另一部分从钝化层18p暴露以进行电连接。在一些实施例中,电触点19安置在从钝化层18p暴露的互连层18r上。在一些实施例中,钝化层18p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。互连层18r是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
在AiP系统中,偶极天线的高度与偶极天线的性能有关。在一些实施例中,高度等于或大于500μm的偶极天线可以满足高性能要求。在一些实施例中,可以通过形成穿透玻璃衬底的一或多个导电通孔(即,玻璃通孔,TGV)来实现AiP系统中的偶极天线。然而,形成TGV的制造成本相对高,并且玻璃衬底的厚度小于300μm。在其它实施例中,可以通过形成穿透硅衬底的一或多个导电通孔(即,硅通孔,TSV)来实现AiP系统中的偶极天线。然而,为了形成具有期望高度的TSV,应该使用多层衬底,这将增加制造成本和设备封装的总厚度。根据图1中所示出的实施例,互连结构11p穿透封装体11(模制通孔,TMV)以限定厚度等于或大于500μm的偶极天线,可以实现具有高性能的偶极天线。
图2展示了根据本公开的一些实施例的半导体设备封装2的横截面视图。半导体设备封装2类似于图1中的半导体设备封装1,并且差别之一在于,在图2中,封装体12由玻璃衬底22取代。
玻璃衬底22安置在导电层15上。玻璃衬底22具有背对电路层15的表面221和与表面221相对的表面222。在一些实施例中,封装体11的厚度H1大于玻璃衬底22的厚度H3。在一些实施例中,封装体11的厚度H1对玻璃衬底的厚度H3的比率约为2:1。
互连层22r安置在玻璃衬底22的表面221上。在一些实施例中,互连层22r限定如贴片天线等天线。互连层22r是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
钝化层22p安置在玻璃衬底22的表面221上以覆盖互连层22r。在一些实施例中,钝化层22p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。
图3展示了根据本公开的一些实施例的半导体设备封装3的横截面视图。半导体设备封装3类似于图1中的半导体设备封装1,并且以下描述了其间的差异。
封装体11安置在电路层10的表面101上。在一些实施例中,封装体11与电路层10接触。封装体11具有背对导电层10的表面111和与表面111相对的表面112。在一些实施例中,封装体11包含环氧树脂,所述环氧树脂包含填料、模制化合物(例如,环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料、或其组合。
一或多个互连结构11p(例如,导电柱或导电元件)穿透封装体11以电连接到电路层10的互连层10r。在一些实施例中,互连结构11p直接地连接到电路层10的互连层10r,并且可以省略图1中所展示的连接层10h和底部填充剂10u。互连结构11p是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
导电层15安置在封装体11的表面111上并且电连接到互连结构11p。导电层15包含互连层15r1、15r2和钝化层15p。互连层15r1和15r2安置在封装体11的表面111上并被钝化层15p覆盖。在一些实施例中,互连层15r1电连接到互连结构11p以限定如偶极天线等天线。在一些实施例中,钝化层15p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。互连层15r2、15r2是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
导电层16安置在封装体12的表面121上。导电层16包含互连层16r和钝化层16p。互连层16r安置在封装体12的表面121上并被钝化层16p覆盖。在一些实施例中,互连层16r限定如贴片天线等天线。例如,互连层16r与互连层15r2耦合以在其间进行信号传输。在一些实施例中,钝化层16p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧或氧化铪。互连层16r是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
图4展示了根据本公开的一些实施例的半导体设备封装4的横截面视图。半导体设备封装4类似于图3中的半导体设备封装3,除了图3中的封装体11可以通过使用两个封装体41和42实施之外。
封装体41安置在电路层10的表面101上。在一些实施例中,封装体41包含环氧树脂,所述环氧树脂包含填料、模制化合物(例如,环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料、或其组合。一或多个互连结构41p(例如,导电柱或导电元件)穿透封装体41以电连接到电路层10的互连层10r。互连结构41p是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
封装体42安置在封装体41上。封装体42与封装体41接触。在一些实施例中,封装体42包含环氧树脂,所述环氧树脂包含填料、模制化合物(例如,环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料、或其组合。一或多个互连结构42p(例如,导电柱或导电元件)穿透封装体42以电连接到互连结构41p和互连层15r1。在一些实施例中,互连层15r1、互连结构41p和互连结构42p电连接以限定如偶极天线等天线。互连结构42p是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd、或其合金。
在一些实施例中,封装体41的厚度与封装体42的厚度的总和H4大于封装体12的厚度H2。在一些实施例中,封装体41的厚度与封装体42的厚度的总和H4对封装体12的厚度H2的比率约为2:1。在一些实施例中,封装体41的厚度与封装体42的厚度的总和H4等于或大于500μm。
图5展示了根据本公开的一些实施例的半导体设备封装5的横截面视图。半导体设备封装5类似于图4中的半导体设备封装4,除了在图5中封装体41通过气隙41g与封装体42间隔开之外。
互连结构41p通过连接层41h(例如,焊料)电连接到互连结构42p。在一些实施例中,互连层15r1、互连结构41p、42p和连接层41h电连接以限定如偶极天线等天线。
在一些实施例中,封装体42的表面421与封装体41的表面412之间的距离H5大于封装体12的厚度H2。在一些实施例中,距离H5对封装体12的厚度H2的比率约为2:1。在一些实施例中,距离H5等于或大于500μm。
图6A、图6B和图6C展示了根据本公开的一些实施例的半导体制造方法。
参照图6A,提供载体69。在一些实施例中,载体69是玻璃载体。在载体69上形成互连层68r,并且然后在载体69上形成钝化层68p。钝化层68p覆盖互连层68r的一部分并暴露互连层68r的另一部分以进行电连接。
参考图6B,在互连层68r上形成一或多个互连结构67p(例如,导电柱),并将所述一或多个互连结构电连接到从钝化层68p暴露的互连层68r的一部分。将电子部件63安置在钝化层68p上。将电子部件63的背侧表面附接到钝化层68p。
仍然参考图6B,在钝化层68p上形成封装体67或者将所述封装体安置在所述钝化层上,并使所述封装体包封电子部件63和互连结构67p。可以通过如传递模制或压缩模制等模制技术来形成或安置封装体67。在一些实施例中,可以形成完全覆盖电子部件63和互连结构67p的封装体67,并且然后通过例如研磨来移除封装体67的一部分以暴露互连结构67p的顶部端子和电子部件63的有源表面。
仍然参考图6B,在封装体67上形成互连层66r,并将所述互连层电连接到从钝化层68p暴露的互连结构67p的一部分和电子部件63的有源表面。在封装体67上形成钝化层66p,并且所述钝化层覆盖互连层66r的一部分并暴露互连层66r的另一部分以进行电连接。
参考图6C,在钝化层68p上形成电路层60,并将所述电路层电连接到从钝化层68p暴露的互连层68r的一部分。电路层60包含互连层60r和覆盖互连层60r的一部分的介电层60d。在一些实施例中,根据设计说明书,可以有任何数量的互连层60r。在从介电层60d暴露的互连层60r上形成连接层60h(例如,焊料或凸块下金属化,UBM)。然后移除载体69以暴露互连层68r和钝化层68p。
图7A、图7B、图7C和图7D展示了根据本公开的一些实施例的半导体制造方法。在一些实施例中,可以使用图7A、图7B、图7C和图7D中的方法来制造图1中的半导体设备封装1。
参照图7A,提供载体79。在一些实施例中,载体79是玻璃载体。在载体79上形成钝化层76p。在钝化层76p上形成互连层76r。在一些实施例中,互连层76r限定如贴片天线等天线。然后,在钝化层76p上形成封装体72或者将所述封装体安置在所述钝化层上,并使所述封装体包封互连层76r。可以通过如传递模制或压缩模制等模制技术来形成或安置封装体72。
参考图7B,在封装体72上形成钝化层75p。在钝化层75p上形成互连层75r1和75r2。在一些实施例中,在互连层75r1上形成互连结构71p(例如,导电柱),并将所述互连结构电连接到互连75r1,并且然后在钝化层75p上形成封装体71以覆盖互连层75r1、75r2和互连结构71p。然后减薄封装体71以暴露互连结构71p的顶部部分以便进行电连接。在其它实施例中,在钝化层75p上形成封装体71,形成穿透封装体71的通孔以暴露互连层75r1,并且然后在通孔内形成互连结构71p。
仍然参考图7B,在封装体71上形成钝化层74p。形成穿透钝化层74p的一或多个开口74h以暴露从封装体71暴露的互连结构71p的顶部部分。
参考图7C,在开口74h内形成互连层74r1以电连接到互连结构71p,并且在钝化层74p上形成互连层74r2。然后,在互连层74r1和74r2上形成连接层70h(例如,焊料或UBM)。
参考图7D,将图6C中所展示的设备封装安置在互连层74r1和74r2上。在一些实施例中,将连接层70h安置在图6C所展示的设备封装的连接层60h上,并且然后在回流过程之后将连接层70h附接到连接层60h。在一些实施例中,通过例如倒装芯片技术将图6C中的设备封装结合到图7C中的设备封装。可以在图6C中的设备封装与图7C中的设备封装之间形成底部填充剂70u以覆盖互连层74r1、74r2、60r和连接层60h、70h。然后,从钝化层76p移除载体79以形成如图1所示出的半导体设备封装1。
图8A、图8B、图8C和图8D展示了根据本公开的一些实施例的半导体制造方法。在一些实施例中,可以使用图8A、图8B、图8C和图8D中的方法来制造图2中的半导体设备封装2。
参考图8A,提供玻璃衬底82。在玻璃衬底82上形成互连层82r,并且然后在玻璃衬底82上形成钝化层82p以覆盖互连层82r。在一些实施例中,互连层82r限定如贴片天线等天线。
参考图8B,提供载体89。在一些实施例中,载体89是玻璃载体。将钝化层82p安置在载体89上。在一些实施例中,移除玻璃衬底82的一部分以减少玻璃衬底82的厚度。在玻璃衬底82上形成钝化层85p,并且然后在钝化层85p上形成导电层85r1和85r2。
在一些实施例中,在互连层85r1上形成互连结构81p(例如,导电柱),并将所述互连结构电连接到互连85r1,并且然后在钝化层85p上形成封装体81以覆盖互连层85r1、85r2和互连结构81p。然后减薄封装体81以暴露互连结构81p的顶部部分以便进行电连接。在其它实施例中,在钝化层85p上形成封装体81,形成穿透封装体81的通孔以暴露互连层85r1,并且然后在通孔内形成互连结构81p。
仍然参考图8B,在封装体81上形成钝化层84p。形成穿透钝化层84p的一或多个开口84h以暴露从封装体81暴露的互连结构81p的顶部部分。
参考图8C,在开口84h内形成互连层84r1以电连接到互连结构81p,并且在钝化层84p上形成互连层84r2。然后,在互连层84r1和84r2上形成连接层80h(例如,焊料或UBM)。
参考图8D,将图6C中所展示的设备封装安置在互连层84r1和84r2上。在一些实施例中,将连接层80h安置在图6C所展示的设备封装的连接层60h上,并且然后在回流过程之后将连接层80h附接到连接层60h。在一些实施例中,通过例如倒装芯片技术将图6C中的设备封装结合到图8C中的设备封装。可以在图6C中的设备封装与图8C中的设备封装之间形成底部填充剂80u以覆盖互连层84r1、84r2、60r和连接层60h、80h。然后,从钝化层82p移除载体89以形成如图2所示出的半导体设备封装2。
如本文所使用的,使用术语“基本上(substantially)”、“基本的(substantial)”、“大约(approximately)”和“约(about)”来表示和解释小的变化。例如,当与数值结合使用时,所述术语可以指代小于或等于所述数值的±10%的变化范围,如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。作为另一个实例,薄膜或层的厚度“基本上一致”可以指代小于或等于薄膜或层的平均厚度的±10%的标准偏差,如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。术语“基本上共面”可以指代沿着同一平面放置的微米范围内的两个表面,如沿着同一平面放置的40μm内、30μm内、20μm内、10μm或1μm内。如果两个表面或部件之间的角度为例如90°±10°,如±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°、或±0.05°,则可以认为两个表面或部件是“基本上垂直的”。当与事件或情况结合使用时,术语“基本上”、“基本的”、“大约”和“约”可以指代事件或情况精确发生的情况以及事件或情况接近发生的情况。
如本文所使用的,除非上下文清楚地另外指明,否则单数术语“一个”、“一种”以及“所述”可以包含复数指示物。在一些实施例的描述中,在另一个部件“上”或“上方”提供的部件可以涵盖前一部件直接在后一部件上(例如,与所述后一部件物理接触)的情况以及一或多个中间部件定位于前一部件与后一部件之间的情况。
如本文所使用的,术语“导电的(conductive)”、“导电的(electricallyconductive)”以及“导电性(electrical conductivity)”指代传输电流的能力。导电材料通常表示对电流流动几乎没有或没有阻碍的那些材料。导电性的一种度量是西门子每米(S/m)。通常,导电材料是导电率大于约104S/m,如至少105S/m或至少106S/m的导电材料。材料的导电性有时可能随温度变化。除非另有说明,否则材料的导电性是在室温下测量的。
另外,数量、比率和其它数值有时以范围格式呈现在本文中。可以理解的是,此些范围格式是为了方便和简洁,并且应该灵活地理解为不仅包含明确指定为范围限制的数值,而且还包含所述范围内涵盖的所有单独数值或子范围,如同每个数值和子范围都是明确指定的一样。
虽然已经参考本公开的具体实施例描述和展示了本公开,但是这些描述和图示不限制本公开。本领域技术人员可以清楚地理解,可以进行各种改变,并且在不脱离如由所附权利要求限定的本公开的真实精神和范围的情况下,可以在实施例内替换等效元件。图示可能不一定按比例绘制。由于制造过程中的变量等,本公开中的艺术再现与实际装置之间可能存在区别。可能存在未具体展示的本公开的其它实施例。说明书和附图应被视为说明性的而非限制性的。可以作出修改以使特定情况、材料、物质构成、方法或过程适应本公开的目标、精神和范围。所有此些修改旨在处于所附权利要求的范围内。尽管已经参考以特定顺序执行的特定操作描述了本文所公开的方法,但是可以理解的是,在不脱离本公开的教导的情况下,可以对这些操作进行组合、细分或重新排序以形成等效方法。因此,除非本文明确指出,否则操作的顺序和分组不受本公开的限制。
Claims (25)
1.一种半导体设备封装,其包括:
电路层,其具有第一表面和与所述第一表面相对的第二表面;
第一封装体,其安置在所述电路层的所述第一表面上;
第一天线,其穿透所述第一封装体并电连接到所述电路层;以及
电子部件,其安置在所述电路层的所述第二表面上。
2.根据权利要求1所述的半导体设备封装,其中所述第一封装体具有背对所述电路层的第一表面和面对所述电路层的第二表面,并且所述第一天线从所述第一封装体的所述第一表面穿透到所述第一封装体的所述第二表面。
3.根据权利要求2所述的半导体设备封装,其进一步包括第一天线辐射方向图,所述第一天线辐射方向图被安置成邻近于所述第一封装体的所述第一表面。
4.根据权利要求1所述的半导体设备封装,其进一步包括
第二封装体,其安置在所述第一封装体上,所述第二封装体具有背对所述第一封装体的第一表面和面对所述第一封装体的第二表面;以及
天线辐射方向图,其被安置成邻近于所述第二封装体的所述第一表面。
5.根据权利要求4所述的半导体设备封装,其中所述第一封装体的厚度大于所述第二封装体的厚度。
6.根据权利要求4所述的半导体设备封装,其进一步包括
第三封装体,其安置在所述第一封装体与所述第二体之间,所述第三封装体与所述第一封装体接触;以及
第二天线,其穿透所述第三封装体并电连接到所述第一天线。
7.根据权利要求6所述的半导体设备封装,其进一步包括:
第四封装体,其安置在所述电路层的所述第二表面上并覆盖所述电子部件;以及
互连结构,其穿透所述第四封装体并电连接到所述电路层。
8.根据权利要求6所述的半导体设备封装,其中所述第一封装体的厚度与所述第三封装体的厚度的总和大于所述第二封装体的厚度。
9.根据权利要求4所述的半导体设备封装,其进一步包括
第三封装体,其安置在所述第一封装体与所述第二体之间;以及
第二天线,其穿透所述第三封装体并电连接到所述第一天线,
其中所述第三封装体通过气隙与所述第一封装间隔开。
10.根据权利要求1所述的半导体设备封装,其中所述电路层进一步包含介电层和互连层,所述互连层安置在所述介电层内并电连接到所述第一天线。
11.根据权利要求1所述的半导体设备封装,其进一步包括:
第三封装体,其安置在所述电路层的所述第二表面上并覆盖所述电子部件;以及
互连结构,其穿透所述第三封装体并电连接到所述电路层。
12.根据权利要求1所述的半导体设备封装,其进一步包括
玻璃衬底,其安置在所述第一封装体上,所述玻璃衬底具有背对所述第一封装体的第一表面和面对所述第一封装体的第二表面;以及
天线辐射方向图,其被安置成邻近于所述玻璃衬底的所述第一表面。
13.根据权利要求12所述的半导体设备封装,其中所述第一封装体的厚度大于所述玻璃衬底的厚度。
14.一种半导体设备封装,其包括:
导电层,其具有第一表面和与所述第一表面相对的第二表面,所述导电层具有在所述导电层的所述第一表面上的第一天线;
第一封装体,其安置在所述导电层的所述第一表面上;以及
第一导电元件,其穿透所述第一封装体并电连接到所述导电层的一部分以限定第二天线。
15.根据权利要求14所述的半导体设备封装,其进一步包括:
第二封装体,其安置在所述导电层的所述第二表面上;以及
第三天线,其被安置成邻近于所述第二封装体的背对所述导电层的表面。
16.根据权利要求14所述的半导体设备封装,其进一步包括电路层,所述电路层安置在所述第一封装体的背对所述导电层的表面上,其中所述电路层具有电连接到所述第一导电元件的互连结构。
17.根据权利要求14所述的半导体设备封装,其进一步包括
玻璃衬底,其安置在所述导电层的所述第二表面上;以及
第三天线,其安置在所述玻璃衬底的背对所述导电层的表面上。
18.根据权利要求14所述的半导体设备封装,其中偶极天线层进一步包括:
第二封装体,其安置在所述第一封装体的背对所述导电层的表面上;以及
第二导电元件,其穿透所述第二封装体并电连接到所述第一导电元件以限定所述第二天线。
19.根据权利要求18所述的半导体设备封装,其中所述第二封装体与所述第一封装体接触。
20.根据权利要求18所述的半导体设备封装,其中所述第二封装体通过气隙与所述第一封装体间隔开。
21.一种制造光学模块的方法,所述方法包括:
(a)提供载体;
(b)在所述载体上方形成具有第一天线的第一导电层;
(c)在所述第一导电层上形成导电元件;以及
(d)在所述第一导电层上形成第一封装体以覆盖所述导电元件并暴露所述导电元件的顶端,
其中所述导电元件和所述第一导电层的一部分限定第二天线。
22.根据权利要求21所述的方法,其中操作(b)进一步包括:
在所述载体上形成第三天线;
形成第二封装体以覆盖所述第三天线;以及
在所述第二封装体上形成所述第一导电层。
23.根据权利要求21所述的方法,其中操作(b)进一步包括:
提供玻璃衬底;
在所述玻璃衬底上形成第三天线;
将所述玻璃衬底放置于所述载体上,使所述第三天线面对所述载体;以及
在所述玻璃衬底上形成所述第一导电层。
24.根据权利要求21所述的方法,其进一步包括将电路层放置于所述第一封装体上以及将所述电路层电连接到所述导电元件的所述顶端。
25.根据权利要求24所述的方法,其中所述电路层具有电子部件,所述电子部件安置在所述电路层的背对所述第一封装体的表面上。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/388,829 US10964652B2 (en) | 2019-04-18 | 2019-04-18 | Semiconductor device package and method of manufacturing the same |
US16/388,829 | 2019-04-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111834342A true CN111834342A (zh) | 2020-10-27 |
Family
ID=72829310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910514836.6A Pending CN111834342A (zh) | 2019-04-18 | 2019-06-14 | 半导体设备封装及其制造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10964652B2 (zh) |
CN (1) | CN111834342A (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10460987B2 (en) * | 2017-05-09 | 2019-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package device with integrated antenna and manufacturing method thereof |
DE102020108280A1 (de) * | 2019-03-26 | 2020-10-01 | Sony Corporation | Mikrowellenantennenvorrichtung |
US11600901B2 (en) * | 2019-07-09 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US11004796B2 (en) * | 2019-07-17 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package |
US11978685B2 (en) * | 2019-07-25 | 2024-05-07 | Intel Corporation | Glass core patch with in situ fabricated fan-out layer to enable die tiling applications |
US20210398904A1 (en) * | 2020-06-19 | 2021-12-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US20220209391A1 (en) * | 2020-12-30 | 2022-06-30 | Texas Instruments Incorporated | Antenna in package having antenna on package substrate |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10157807B2 (en) * | 2016-05-26 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sensor packages and manufacturing mehtods thereof |
KR102334710B1 (ko) * | 2017-03-28 | 2021-12-02 | 삼성전기주식회사 | 전자부품 내장 기판 |
US10325786B1 (en) * | 2017-12-07 | 2019-06-18 | Sj Semiconductor (Jiangyin) Corporation | Double-sided plastic fan-out package structure having antenna and manufacturing method thereof |
US10424550B2 (en) * | 2017-12-19 | 2019-09-24 | National Chung Shan Institute Of Science And Technology | Multi-band antenna package structure, manufacturing method thereof and communication device |
CN207852888U (zh) * | 2017-12-27 | 2018-09-11 | 中芯长电半导体(江阴)有限公司 | 具有天线组件的半导体封装结构 |
CN207852654U (zh) * | 2017-12-27 | 2018-09-11 | 中芯长电半导体(江阴)有限公司 | 具有天线组件的半导体封装结构 |
US10886594B2 (en) * | 2018-03-16 | 2021-01-05 | Sj Semiconductor (Jiangyin) Corporation | Packaging structure and packaging method for antenna |
US10916854B2 (en) * | 2018-03-29 | 2021-02-09 | Mediatek Inc. | Antenna structure with integrated coupling element and semiconductor package using the same |
KR102066904B1 (ko) * | 2018-09-18 | 2020-01-16 | 삼성전자주식회사 | 안테나 모듈 |
-
2019
- 2019-04-18 US US16/388,829 patent/US10964652B2/en active Active
- 2019-06-14 CN CN201910514836.6A patent/CN111834342A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US10964652B2 (en) | 2021-03-30 |
US20200335458A1 (en) | 2020-10-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111834342A (zh) | 半导体设备封装及其制造方法 | |
US9640504B2 (en) | Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core | |
US8072059B2 (en) | Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die | |
US9257356B2 (en) | Semiconductor device and method of forming an IPD beneath a semiconductor die with direct connection to external devices | |
US11605877B2 (en) | Semiconductor device package and method of manufacturing the same | |
CN109755202B (zh) | 电子封装件及其制法 | |
US10741415B2 (en) | Thermosonically bonded connection for flip chip packages | |
US11798859B2 (en) | Electronic device package and method of manufacturing the same | |
US11329015B2 (en) | Semiconductor device package and method of manufacturing the same | |
US10903561B2 (en) | Semiconductor device package and method of manufacturing the same | |
US20220115341A1 (en) | Semiconductor device package and method of manufacturing the same | |
US11538772B2 (en) | Semiconductor device package and method of manufacturing the same | |
US20200075571A1 (en) | Semiconductor device package and method of manufacturing the same | |
US20210398904A1 (en) | Semiconductor device package and method of manufacturing the same | |
US11594660B2 (en) | Semiconductor device package | |
US11329016B2 (en) | Semiconductor device package and method of manufacturing the same | |
US11581273B2 (en) | Semiconductor device package and method of manufacturing the same | |
US11756904B2 (en) | Semiconductor device package and method of manufacturing the same | |
US11515270B2 (en) | Semiconductor device package and method of manufacturing the same | |
US11257788B2 (en) | Semiconductor device package with stacked die having traces on lateral surface | |
CN116994965A (zh) | 形成无基板的SiP模块的半导体器件和方法 | |
CN112310026A (zh) | 半导体装置封装及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |