CN111833826A - Common voltage compensation circuit and display device thereof - Google Patents
Common voltage compensation circuit and display device thereof Download PDFInfo
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- CN111833826A CN111833826A CN202010715787.5A CN202010715787A CN111833826A CN 111833826 A CN111833826 A CN 111833826A CN 202010715787 A CN202010715787 A CN 202010715787A CN 111833826 A CN111833826 A CN 111833826A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The application discloses a public voltage compensation circuit and a display device thereof. The common voltage compensation circuit includes: a first common voltage generating unit providing a first common voltage; a second common voltage generating unit providing a second common voltage; the detection unit detects whether the load of the picture to be displayed exceeds a first preset range or not, and outputs a first common voltage or a second common voltage based on the detection result, and the second common voltage generation unit comprises: the signal generating unit generates an alternating current signal; and the signal adjusting unit adjusts the phase and/or amplitude of the alternating current signal based on the frame data of the picture to be displayed so as to obtain the second common voltage. The uncompensated or compensated common voltage is provided to the display panel through the load of the display surface, and the compensated common voltage is provided to the display panel to offset in-plane coupling ripples through the signal adjusting unit, so that the manufacturing process of the display panel is not required to be modified, and the development cost is saved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a common voltage compensation circuit and a display device thereof.
Background
In the existing display device, the common electrode line in the panel is long and is easy to be coupled with the surrounding data lines. When the display device displays a heavy-duty picture, the picture display may be abnormal due to the coupled common voltage, for example, the picture brightness may be non-uniform.
Fig. 1 shows a schematic diagram of a common voltage waveform of a prior art display device. When the display screen is overloaded, the DATA signal DATA applied to the DATA line may shift the potential of the common voltage VCOM applied to the in-plane common electrode line, and further, the waveform of the in-plane common voltage VCOM may fluctuate. The common voltage VCOM, which has waveform fluctuation, causes non-uniformity of the picture brightness during picture display.
In the prior art, the occurrence of coupling phenomenon is often reduced by improving the glass process, but the cost of the improved process is high and the process is complex.
Therefore, it is an urgent technical problem to be solved by those skilled in the art how to avoid the display failure of the display device caused by the coupling of the in-plane common voltage.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a common voltage compensation method and a display device thereof, so as to provide a compensated common voltage to the display device to avoid a bad display image due to a coupling effect.
According to an aspect of the present invention, there is provided a common voltage compensation circuit including: a first common voltage generating unit providing a first common voltage; a second common voltage generating unit providing a second common voltage; and a detection unit which detects whether the load of the picture to be displayed exceeds a first preset range and outputs a first common voltage or a second common voltage based on the detection result, wherein the second common voltage generation unit comprises: the signal generating unit provides an alternating current signal; and the signal adjusting unit is used for adjusting the phase and/or amplitude of the alternating current signal based on the frame data of the picture to be displayed so as to obtain the second public voltage.
Optionally, the first common voltage is a dc waveform.
Optionally, the signal generating unit obtains the ac signal based on a driving enable signal and with reference to the first common voltage, converts a level state of the ac signal based on a falling edge of the driving enable signal, and provides a source driving signal to the display panel when the falling edge comes.
Optionally, the signal adjusting unit includes: the phase adjusting circuit is used for acquiring data signals of adjacent data lines and adjusting the phase of the alternating current signal based on the data signals of the adjacent data lines to obtain an intermediate public voltage; the amplitude detection circuit is connected with the phase adjustment circuit, obtains compensation quantity based on the middle public voltage and the first public voltage, and judges whether the compensation quantity exceeds a second preset range; the amplitude adjusting circuit is connected between the amplitude detecting circuit and the phase adjusting circuit and is used for adjusting the amplitude of the middle public voltage, wherein the compensation quantity exceeds a second preset range and is used for adjusting the amplitude of the middle public voltage; the compensation amount is within a range, and the intermediate common voltage is output as the second common voltage.
Optionally, the phase adjustment circuit includes: the input end of the first subtracter receives the data signals of the adjacent data lines respectively, and the output end of the first subtracter outputs a first difference signal; the first input end of the trigger is connected with the output end of the first subtracter, and the second input end of the trigger is connected with and receives a clock signal; a control end of the third switching tube is connected with an output end of the trigger, and a first path end of the third switching tube receives the alternating current signal; one end of the phase inverter is connected with the second channel end of the third switching tube; the control end of the fourth switch tube is connected with the output end of the trigger, the first path end of the fourth switch tube receives the alternating current signal, the second path end of the fourth switch tube is connected with the other end of the phase inverter and outputs the middle public voltage, wherein the third switch tube and the fourth switch tube are respectively an N-type transistor and a P-type transistor or respectively a P-type transistor and an N-type transistor.
Optionally, the amplitude detection unit includes: the input end of the second subtractor is respectively connected with the second public voltage generating unit to receive the second public voltage, and the phase adjusting unit to receive the middle public voltage, and the output end of the second subtractor outputs a second difference signal which represents the compensation quantity of the public voltage; and a first comparator, wherein the first input end is connected with the output end of the second subtracter, the second input end is connected with and receives a second reference signal, and the output end outputs a control signal which represents whether the compensation quantity exceeds a second preset range.
Optionally, the amplitude adjustment circuit includes: a counter that increments by one in a case of receiving the intermediate common voltage; and an amplitude adjuster which provides adjustment waveforms of different amplitudes and superimposes the adjustment waveforms on the intermediate common voltage.
Optionally, the detection unit includes: the sampling circuit is used for acquiring power supply voltage and output voltage for picture display to obtain the load quantity of a picture to be displayed and comparing the load quantity with a first reference signal to obtain the detection result; and the processing circuit is respectively connected with the sampling circuit, the first public voltage generating unit and the signal generating unit, and outputs the first public voltage to a display panel or provides the alternating current signal to the signal adjusting unit based on the detection result so as to output the second public voltage to the display panel.
Optionally, the sampling unit includes: the sampling module acquires the power supply voltage and the output voltage; the input end of the third subtracter receives the power supply voltage and the output voltage respectively, and the output end of the third subtracter outputs the load quantity; and a second comparator, wherein a first input end of the second comparator is connected with an output end of the third subtractor, a second input end of the second comparator is connected with and receives the first reference signal, and an output end of the second comparator outputs a detection result which represents whether the load exceeds a first preset range, and the processing circuit comprises: a control end of the first switch tube is connected with an output end of the second comparator, a first path end of the first switch tube is connected with the signal generating unit to receive the alternating current signal, and a second path end of the first switch tube is connected with the phase adjusting circuit to provide the alternating current signal; and a control end of the second switch tube is connected with an output end of the second comparator, a first path end of the second switch tube is connected with the first public voltage generating unit to receive the first public voltage, a second path end of the second switch tube is used for providing the first public voltage, and the first switch tube and the second switch tube are respectively an N-type transistor and a P-type transistor or respectively a P-type transistor and an N-type transistor.
According to another aspect of the present invention, there is provided a display device comprising the common voltage compensation circuit described above.
The common voltage compensation circuit in the display device provided by the invention detects the load of the surface to be displayed and provides uncompensated or compensated common voltage to the display panel based on whether the load exceeds the range. And providing uncompensated common voltage when the load of the picture to be displayed does not exceed the first preset range, and providing compensated common voltage when the load of the picture to be displayed exceeds the first preset range, so that normal picture display can be realized. And the phase and/or amplitude of the alternating current signal are adjusted based on the frame data of the picture to be displayed by arranging the signal adjusting unit, so that the compensated common voltage is provided to the display panel to offset in-plane coupling ripples, and the picture is normally displayed. The problem of poor display caused by in-plane coupling is solved without modifying a front-end process, and the development cost is saved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of an in-plane common voltage waveform for a display device according to the prior art;
fig. 2 illustrates a schematic structural view of a display device according to an embodiment of the present invention;
FIG. 3 shows a schematic diagram of a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 4 shows a circuit schematic of a detection unit in a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a signal generating unit in a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram showing a configuration of a phase adjustment circuit in the common voltage compensation circuit according to the embodiment of the present invention;
FIG. 7 is a circuit diagram showing a phase adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 8a is a timing diagram of a phase adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 8b is a timing diagram of another phase adjustment circuit in the common voltage compensation circuit according to the embodiment of the present invention;
FIG. 9 is a circuit diagram illustrating an amplitude detection circuit in a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 10a is a circuit diagram of an amplitude adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention;
FIG. 10b is a timing diagram of an amplitude adjustment circuit in the common voltage compensation circuit according to an embodiment of the present invention;
FIG. 11a shows a schematic waveform diagram of a display device; fig. 11b shows a schematic waveform diagram of another display device.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 2 shows a schematic structural diagram of a display device according to an embodiment of the present invention.
As shown in fig. 2, the display device includes a panel 100, a gate driver 220, a source driver 210, and a common voltage compensation circuit 300.
The panel 100 in the display device comprises a pixel array, the pixel array comprises a plurality of pixel units 110, each pixel unit 101 is provided with a first substrate, a second substrate and a liquid crystal molecular layer positioned between the first substrate and the second substrate, which are opposite to each other, an electric field is generated between a common electrode and a pixel electrode on the first substrate and the second substrate, and the electric field controls the rotation of the liquid crystal molecules, so that the light transmittance of each pixel unit is changed, and the picture display is realized. The source driver 210 and the gate driver 220 cooperate to write the gray-scale signal DATA into each pixel unit of the pixel electrode, the common voltage compensation circuit 300 selectively provides an uncompensated or compensated common voltage to the common electrode based on the load amount of the picture to be displayed, and the polarity of the voltage generated between the common electrode and the pixel electrode is controlled by a polarity inversion signal output by a timing controller (not shown).
The timing controller outputs a start signal to the gate driver 220, and the timing controller outputs the received initial data to the source driver 210. The gate driver 220 transmits gate driving signals to the panel 100 through the gate lines, and the source driver 210 transmits gray-scale signals DATA to the pixel units 110 of the panel 100 through the DATA lines and writes the gray-scale signals DATA into the pixel electrodes.
The common voltage compensation circuit 300 includes a detection unit 310, a first common voltage generation unit 320, and a second common voltage generation unit 330.
The detecting unit 310 is configured to detect whether a load of the to-be-displayed picture exceeds a first preset range, and directly output the first common voltage or further output the second common voltage by adjusting based on a detection result.
The first common voltage generating unit 320 provides a first common voltage, which is a dc waveform, i.e., a dc voltage provided by the gamma voltage module is written using, for example, an Inter-Integrated Circuit (IIC) interface. When the load of the picture to be displayed does not exceed the first preset range, the picture to be displayed is considered to be a light-load picture, and then the first common voltage is controlled to be output to the display panel.
The second common voltage generating unit 330 includes a signal generating unit 331 and a signal adjusting unit 332. The signal generating unit 331 provides an ac signal, for example, generates an ac signal based on the first common voltage value or other dc voltage values. The signal adjusting unit 332 adjusts the phase and/or amplitude of the ac signal based on the frame data of the picture to be displayed to obtain the second common voltage. When the detection unit 310 detects that the load amount of the to-be-displayed picture exceeds the first preset range, the to-be-displayed picture is considered as a heavy-load picture, and then the alternating current signal provided by the signal generation unit 331 is controlled to be output to the signal adjustment unit 332, so that the compensated second common voltage is obtained, and then the second common voltage is output to the display panel. The second common voltage is input into the display panel to offset the coupling ripple in the surface, thereby avoiding poor display caused by in-plane coupling.
The structures of the detecting unit 310, the second common voltage generating unit 330, and the first common voltage generating unit 320 in the common voltage compensating circuit 300 are explained in detail below.
Fig. 3 shows a schematic structural diagram of a common voltage compensation circuit according to an embodiment of the present invention.
The detection unit 310 includes a sampling circuit 311 and a processing circuit 312. The sampling circuit 311 collects the power supply voltage and the output voltage for displaying the picture to obtain a load of the picture to be displayed, and compares the load with the first reference signal to obtain a detection result, where the detection result represents whether the load of the picture to be displayed exceeds a first preset range. The processing circuit 312 is respectively connected to the sampling circuit 311, the signal generating unit 331 of the first common voltage generating unit 320, and the signal generating unit 331 of the second common voltage generating unit 330, and outputs the first common voltage to the display panel directly or supplies the ac signal V1 to the signal adjusting unit 332 based on the detection result to output the compensated second common voltage to the display panel.
The signal generating unit 331 of the second common voltage generating unit 330 provides an ac signal V1, and when the detection result of the detecting unit 310 indicates that the picture to be displayed is a heavy-load picture, the detecting unit 310 provides the ac signal V1 to the signal adjusting unit 332 to adjust the phase and/or amplitude of the ac signal. Note that the ac signal V1 may be directly supplied to the signal adjustment unit 332 by the signal generation unit 331.
The signal adjusting unit 332 includes a phase adjusting circuit 3221, an amplitude detecting circuit 3222, and an amplitude adjusting circuit 3223. The phase adjustment circuit 3221 collects the data signals on the adjacent data lines, and adjusts the phase of the ac signal V1 based on the data signals of the adjacent data lines to obtain the intermediate common voltage VCOM 3. The amplitude detection circuit 3222 is connected to the phase adjustment circuit 3221, obtains a compensation amount based on the middle common voltage VCOM3 and the first common voltage VCOM1, determines whether the compensation amount exceeds a second preset range, adjusts the amplitude of the middle common voltage VCOM3 by using the amplitude adjustment circuit 3223 when the compensation amount exceeds the second preset range, and continues to provide the compensation amount to the amplitude detection circuit 3222 for detection by the phase adjustment circuit 3221; when the compensation amount is within the range, the intermediate common voltage VCOM3 is used as the second common voltage VCOM2 and is directly supplied to the common voltage line of the display panel for driving the heavy load picture display. The amplitude adjusting circuit 3223 is connected between the amplitude detecting circuit 3222 and the phase adjusting circuit 3221, and is configured to adjust the amplitude of the intermediate common voltage VCOM 3.
Preferably, the second common voltage generation unit 330 further includes a storage circuit 333, which is connected to the amplitude detection circuit 3222 to receive and store the output second common voltage VCOM2 for being called at any time in practical applications.
Fig. 4 shows a circuit schematic diagram of a detection unit in the common voltage compensation circuit according to an embodiment of the present invention.
As shown in fig. 4, the sampling circuit 311 of the detection unit 310 includes a sampling module 3111, a third subtractor 3112, and a second comparator 3113. The sampling module 3111 collects a supply voltage Vin2 and an output voltage Vout. Specifically, the power module 3114 supplies power to the display device, the power module 3114 receives the input voltage Vin1 to operate, and the sampling module 3111 is connected to the power module 3114 to receive the supply voltage Vin2 output by the power module 3114 and the output voltage Vout provided to the data line. The input terminal of the third subtractor 3112 receives the supply voltage Vin2 and the output voltage Vout, respectively, and the output terminal outputs the difference between the supply voltage Vin2 and the output voltage Vout, i.e. the load of the picture to be displayed. The second comparator 3113 has a first input terminal connected to the output terminal of the third subtractor 3112, a second input terminal connected to and receiving the first reference signal Vref1, and an output terminal outputting the detection result. The first reference signal Vref1 represents that the display frame is a threshold of a heavy-loading frame, the display frame is represented as a heavy-loading frame if the load exceeds the threshold, and the display frame is represented as a light-loading frame if the load does not exceed the threshold. The sampling module 3111 may adopt MAX471, for example. The third subtractor may be constructed using an operational amplifier, for example. The first reference signal Vref1 may be adjusted according to actual requirements.
The processing circuit 312 of the detection unit 310 includes a first switch tube 3121 and a second switch tube 3122. The control end of the first switch tube 3121 is connected to the output end of the second comparator 3113, the first path end of the first switch tube 3121 is connected to the signal generating unit 321 for receiving the ac signal V1, and the second path end of the first switch tube 3121 is connected to the phase adjusting circuit 322 for providing the ac signal V1. The control terminal of the second switch tube 3122 is connected to the output terminal of the second comparator 3113, the first path terminal of the second switch tube 3122 is connected to the first common voltage generation unit 320 to receive the first common voltage VCOM1, and the second path terminal of the second switch tube 3122 is used to provide the first common voltage VCOM 1. That is, when the detection result outputted from the sampling circuit 311 indicates that the picture to be displayed is a heavy-loading picture, the first switch tube 3121 is turned on, and the ac signal V1 is further provided to the signal adjusting unit 322, so as to provide the compensated second common voltage VCOM2 to the display panel, so as to suppress the display defect caused by the in-plane coupling, in which case the second switch tube 3122 is turned off. When the detection result output by the sampling circuit 311 indicates that the picture to be displayed is a light-load picture, the second switch tube 3122 is turned on to provide the first common voltage VCOM1 to the display panel, so as to implement light-load picture display, and in this case, the first switch tube 3121 is turned off. The first switch tube 3121 and the second switch tube 3122 are respectively an N-type transistor and a P-type transistor, or respectively a P-type transistor and an N-type transistor.
The control ends of the first switch tube and the second switch tube are gates of the transistors, and the first path end and the second path end are a source and a drain, or a drain and a source of the transistor, respectively.
Fig. 5 shows a timing diagram of a signal generation unit in a common voltage compensation circuit according to an embodiment of the present invention.
As shown in fig. 5, the signal generating unit 331 of the second common voltage generating unit 330 provides an alternating current signal V1. In the present embodiment, the ac signal V1 is generated with reference to the first common voltage VCOM 1. The waveform and the period of the ac signal V1 are determined based on the driving scheme of the driver and the liquid crystal inversion method. Specifically, in this embodiment, the ac signal V1 mainly matches the output of the source driver, and the source driver outputs the source driving signal as the falling edge of the reference driving enable signal TP in the same frame, so the ac signal V1 also needs to refer to the falling edge of the reference driving enable signal TP, and the compensated second common voltage VCOM2 has the same frequency as the data signal provided by the source driver to the data line. The ac signal V1 has an amplitude of, for example, 0.5V with respect to the first common voltage VCOM 1. Subsequently, the signal adjusting unit 332 adjusts the phase and amplitude of the ac signal to obtain a second common voltage VCOM2, which is used to cancel in-plane coupling ripple waves and achieve normal display of the heavy-duty picture. In this embodiment, the ac signal V1 has an amplitude of 0.5V with reference to the first common voltage VCOM1, but the above embodiment is not the only embodiment of the present application.
Fig. 6 shows a schematic structural diagram of a phase adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention, and fig. 7 shows a schematic circuit diagram of a phase adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention.
As shown in fig. 6 and 7, the phase adjustment circuit 3221 includes a first subtractor 3225, a flip-flop 3226, a third switching tube 3227, a fourth switching tube 3228, and an inverter 3229.
The first subtractor 3225 has input terminals respectively receiving the data signals of the adjacent data lines, and an output terminal outputting a first difference signal Vs. Specifically, the first subtractor 3225 includes a first operational amplifier U1, a non-inverting input terminal of the first operational amplifier U1 is connected to the data line Sn through a resistor R1 and collects a data signal on the data line, a non-inverting input terminal of the first operational amplifier U1 is further connected to the ground through a resistor R3, an inverting input terminal of the first operational amplifier U1 is connected to the data line Sn +1 through a resistor R2 and collects a data signal on the data line, and an inverting input terminal of the first operational amplifier U1 is connected to an output terminal of the first operational amplifier U1 through a resistor R4.
A first input terminal of the flip-flop 3226 is connected to the output terminal of the first subtractor 3225, and a second input terminal thereof is connected to and receives the clock signal CLK. Specifically, the flip-flop 3226 is, for example, a D flip-flop U2. The input terminal of the D flip-flop U2 is connected to the output terminal of the first operational amplifier U1 through a resistor R5, the clock terminal of the D flip-flop U2 is connected to receive a clock signal CLK, and the timing of the clock signal CLK is related to the timing of the driving enable signal TP and the signal STV 2. The driving enable signal TP is used as a reference signal output by the source driver, and the source driver outputs a source driving signal when a falling edge of the driving enable signal TP arrives, for example. The signal STV1 is a start signal for each frame picture, and the signal STV2 is a start signal for each frame picture. Specifically, when the STV1 signal is in the active level state, the clock signal CLK is in the inactive level state (for example, low level), and the level state of the clock signal CLK is switched when the falling edge of the drive enable signal TP arrives, and the level state of the clock signal CLK is switched when the STV2 signal indicating the end of the frame is in the active level state.
A control end of the third switching tube 3227 is connected to the output end of the trigger 3226, a first path end of the third switching tube 3227 receives the ac signal V1, and a second path end of the third switching tube 3227 is connected to one end of the inverter 3229. A control terminal of the fourth switching tube 3228 is connected to the output terminal of the flip-flop 3226, a first path terminal of the fourth switching tube 3228 receives the ac signal V1, and a second path terminal of the fourth switching tube is connected to the other terminal of the inverter 3229 and outputs the intermediate common voltage VCOM 3. Specifically, the third switch 3227 is a PMOS transistor Q3, the fourth switch 3228 is an NMOS transistor Q4, and the inverter 3229 is an inverter U3. The control terminals of the PMOS transistor Q3 and the NMOS transistor Q4 are connected to the output terminal of the D flip-flop U2 through a resistor R7. The ac signal V1 is connected to the first path terminal of the PMOS transistor Q3 and the first path terminal of the NMOS transistor Q4, respectively, via the resistor R6. The middle node of the second pass terminal nand gate U3 of the NMOS transistor Q4 outputs an intermediate common voltage VCOM3 via a resistor R8, wherein the resistor R9 is further connected to a capacitor C1 connected to ground.
The transistor types of the third switching tube and the fourth switching tube can be opposite, and then the positive phase input end and the negative phase input end of the first subtracter can also exchange the connected data lines.
FIG. 8a is a timing diagram of a phase adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention; FIG. 8b is a timing diagram of another phase adjustment circuit in the common voltage compensation circuit according to the embodiment of the present invention.
As shown in fig. 8a and 8b, the difference between the phases of the data signals on two adjacent data lines is shown. In the same frame, the phase difference between the data signal on the data line Sn +1 and the data signal on the data line Sn is-180 ° or 180 °, and correspondingly, the phase of the intermediate common voltage VCOM3 should be adjusted, so that the second common voltage VCOM2 obtained after the amplitude is adjusted subsequently can cancel out the in-plane coupling ripple, thereby enabling the display to be normal.
Fig. 9 shows a circuit schematic diagram of an amplitude detection circuit in the common voltage compensation circuit according to an embodiment of the present invention.
As shown in fig. 9, the amplitude detection circuit 3223 in the signal adjustment unit 332 in the second common voltage generation unit 330 includes a second subtractor 32221 and a first comparator 32222.
The second subtractor 32221 has an input terminal connected to the first common voltage generating unit 320 for receiving the first common voltage VCOM1, and an output terminal connected to the phase adjusting unit 3221 for receiving the intermediate common voltage VCOM3 for outputting a second difference signal V2, wherein the second difference signal V2 represents the compensation amount of the common voltage. The first comparator 32222 has a first input terminal connected to the output terminal of the second subtractor 32221, a second input terminal connected to and receiving the second reference signal Vref2, and an output terminal outputting a control signal indicating whether the compensation amount exceeds a second preset range. The second reference signal Vref2 represents a threshold of the compensation amount during reloading of the picture, when the compensation amount exceeds the threshold, the middle common voltage is continuously transmitted to the amplitude adjustment circuit for amplitude adjustment to obtain the second common voltage VCOM2 with better compensation effect, and when the compensation amount does not exceed the threshold, the middle common voltage is directly provided to the display panel as the second common voltage VCOM 2.
The second subtractor may be constructed by, for example, an operational amplifier. The second reference signal may be adjusted according to actual requirements.
Fig. 10a shows a circuit diagram of an amplitude adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention, and fig. 10b shows a timing diagram of an amplitude adjustment circuit in a common voltage compensation circuit according to an embodiment of the present invention.
As shown in fig. 10a and 10b, the amplitude adjusting circuit 3223 includes a counter 32231 and an amplitude adjuster 32232. Counter 32231 is used to record the number of amplitude adjustments, i.e., counter 32231 is incremented by one every time amplitude adjustment circuit 3223 runs. The amplitude adjuster 32231 provides the adjustment waveform V3 of different amplitudes and superimposes the adjustment waveform on the intermediate common voltage VCOM 3. Specifically, for example, V3 is adjusted to a waveform that has the same frequency as the intermediate common voltage VCOM3, is 180 ° out of phase, and can be set in amplitude. The amplitude thereof may be set to other values of 0.1V, 0.01V, etc. Further, after passing through the amplitude adjustment circuit 3223, the amplitude of the intermediate common voltage VCOM3 decreases.
It should be noted that the amplitude adjustment circuit may also provide a waveform with the same frequency, the same phase, and the settable amplitude as the intermediate common voltage VCOM 3. And the intermediate common voltage VCOM3 increases in amplitude after passing through the amplitude adjustment circuit.
FIG. 11a shows a schematic waveform diagram of a display device; fig. 11b shows a schematic waveform diagram of another display device.
As shown in fig. 11a, the common voltage VCOM5 is provided by the second common voltage generation unit in the common voltage compensation circuit, when a heavy loading picture (determined that the loading of the picture is higher than the predetermined threshold value) is displayed, the common electrode line loaded with the common voltage VCOM5 is coupled by the influence of the surrounding data line Sn and the data line Sn +1, and the in-plane common voltage VCOM4 after the coupling effect of the common voltage on the common electrode line is generated can enable the heavy loading picture to be normally displayed.
As shown in fig. 11b, the common voltage VCOM5 is provided by, for example, a first common voltage generation unit in the common voltage compensation circuit in the present application. However, when displaying a heavy-loading picture (after determining that the load of the picture is higher than the predetermined threshold), the common electrode line loaded with the common voltage VCOM5 is coupled by the influence of the surrounding data line Sn and data line Sn +1, and the in-plane common voltage VCOM4 after the common voltage on the common electrode line is coupled will influence the normal display of the heavy-loading picture.
The application also provides a display device, which comprises the common voltage compensation circuit provided by the above, and is used for providing the first common voltage or the second common voltage for the display panel. The technical problem of displaying abnormity is solved, the process of modifying the front-end process is avoided, and the development cost is saved.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A common voltage compensation circuit, comprising:
a first common voltage generating unit providing a first common voltage;
a second common voltage generating unit providing a second common voltage; and
a detection unit for detecting whether the load of the picture to be displayed exceeds a first preset range and outputting a first common voltage or a second common voltage to the display panel based on the detection result,
wherein the second common voltage generating unit includes:
the signal generating unit provides an alternating current signal; and
and the signal adjusting unit adjusts the phase and/or amplitude of the alternating current signal based on the frame data of the picture to be displayed so as to obtain the second common voltage.
2. The common voltage compensation circuit of claim 1, wherein the first common voltage is a dc waveform.
3. The common voltage compensation circuit according to claim 1, wherein the signal generation unit obtains the ac signal based on a drive enable signal with reference to the first common voltage, changes a level state of the ac signal based on a falling edge of the drive enable signal, and supplies a source drive signal to the display panel when the falling edge comes.
4. The common voltage compensation circuit according to claim 3, wherein the signal adjustment unit comprises:
the phase adjusting circuit is used for acquiring data signals of adjacent data lines and adjusting the phase of the alternating current signal based on the data signals of the adjacent data lines to obtain an intermediate public voltage;
the amplitude detection circuit is connected with the phase adjustment circuit, obtains compensation quantity based on the middle public voltage and the first public voltage, and judges whether the compensation quantity exceeds a second preset range; and
an amplitude adjustment circuit connected between the amplitude detection circuit and the phase adjustment circuit for adjusting the amplitude of the intermediate common voltage,
adjusting the amplitude of the intermediate common voltage when the compensation quantity exceeds a second preset range; the compensation amount is within a range, and the intermediate common voltage is output as the second common voltage.
5. The common voltage compensation circuit according to claim 4, wherein the phase adjustment circuit comprises:
the input end of the first subtracter receives the data signals of the adjacent data lines respectively, and the output end of the first subtracter outputs a first difference signal;
the first input end of the trigger is connected with the output end of the first subtracter, and the second input end of the trigger is connected with and receives a clock signal;
a control end of the third switching tube is connected with an output end of the trigger, and a first path end of the third switching tube receives the alternating current signal;
one end of the phase inverter is connected with the second channel end of the third switching tube;
a control end of the fourth switching tube is connected with an output end of the trigger, a first path end of the fourth switching tube receives the alternating current signal, a second path end of the fourth switching tube is connected with the other end of the phase inverter and outputs the middle common voltage,
the third switching tube and the fourth switching tube are respectively an N-type transistor and a P-type transistor, or respectively a P-type transistor and an N-type transistor.
6. The common voltage compensation circuit according to claim 4, wherein the amplitude detection unit comprises:
the input end of the second subtractor is respectively connected with the second public voltage generating unit to receive the second public voltage, and the phase adjusting unit to receive the middle public voltage, and the output end of the second subtractor outputs a second difference signal which represents the compensation quantity of the public voltage; and
and the first input end of the first comparator is connected with the output end of the second subtracter, the second input end of the first comparator is connected with and receives the second reference signal, and the output end of the first comparator outputs a control signal which represents whether the compensation quantity exceeds a second preset range.
7. The common voltage compensation circuit of claim 4, wherein the amplitude adjustment circuit comprises:
a counter that increments by one in a case of receiving the intermediate common voltage; and
and the amplitude adjuster provides adjusting waveforms with different amplitudes and superposes the adjusting waveforms on the middle public voltage.
8. The common voltage compensation circuit according to claim 1, wherein the detection unit comprises:
the sampling circuit is used for acquiring power supply voltage and output voltage for picture display to obtain the load quantity of a picture to be displayed and comparing the load quantity with a first reference signal to obtain the detection result; and
and the processing circuit is respectively connected with the sampling circuit, the first public voltage generating unit and the signal generating unit, and outputs the first public voltage to a display panel or provides the alternating current signal to the signal adjusting unit based on the detection result so as to output the second public voltage to the display panel.
9. The common voltage compensation circuit of claim 8,
the sampling unit includes:
the sampling module acquires the power supply voltage and the output voltage;
the input end of the third subtracter receives the power supply voltage and the output voltage respectively, and the output end of the third subtracter outputs the load quantity; and
a second comparator, the first input end of which is connected with the output end of the third subtracter, the second input end of which is connected with and receives the first reference signal, the output end of which outputs a detection result, the detection result represents whether the load exceeds a first preset range or not,
the processing circuit includes:
a control end of the first switch tube is connected with an output end of the second comparator, a first path end of the first switch tube is connected with the signal generating unit to receive the alternating current signal, and a second path end of the first switch tube is connected with the phase adjusting circuit to provide the alternating current signal; and
a second switch tube, a control end of the second switch tube being connected to an output end of the second comparator, a first path end of the second switch tube being connected to the first common voltage generating unit to receive the first common voltage, a second path end of the second switch tube being used to provide the first common voltage,
the first switch tube and the second switch tube are respectively an N-type transistor and a P-type transistor, or respectively a P-type transistor and an N-type transistor.
10. A display device, comprising:
a common voltage compensation circuit as claimed in any one of claims 1 to 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112562607A (en) * | 2020-12-17 | 2021-03-26 | 昆山龙腾光电股份有限公司 | Common voltage compensation circuit for display panel, compensation method and display device |
| TWI785852B (en) * | 2021-10-20 | 2022-12-01 | 大陸商北京集創北方科技股份有限公司 | Pixel compensation method for self-luminous display panel, flat display device and information processing device |
| CN116704970A (en) * | 2023-08-04 | 2023-09-05 | 南京芯视元电子有限公司 | Correction system and method for display signal processing |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990080840A (en) * | 1998-04-22 | 1999-11-15 | 김영환 | Common power supply automatic setting circuit of liquid crystal display device |
| CN101295110A (en) * | 2007-04-25 | 2008-10-29 | 群康科技(深圳)有限公司 | Crystal display device and driving method thereof |
| CN101645244A (en) * | 2008-08-08 | 2010-02-10 | 乐金显示有限公司 | Liquid crystal display device and driving method thereof |
| CN102842280A (en) * | 2012-08-31 | 2012-12-26 | 京东方科技集团股份有限公司 | Public voltage compensation circuit and method, and liquid crystal display device |
| CN102903344A (en) * | 2012-09-27 | 2013-01-30 | 合肥京东方光电科技有限公司 | Public electrode voltage compensation method and device and time schedule controller |
| US20140340383A1 (en) * | 2011-12-07 | 2014-11-20 | Sharp Kabushiki Kaisha | Display device and electrical apparatus |
| CN104658500A (en) * | 2015-03-04 | 2015-05-27 | 京东方科技集团股份有限公司 | Common voltage compensating method and system |
| CN107437407A (en) * | 2017-08-11 | 2017-12-05 | 昆山龙腾光电有限公司 | Public voltage generating circuit and liquid crystal display device |
| CN109377960A (en) * | 2018-12-14 | 2019-02-22 | 深圳市华星光电半导体显示技术有限公司 | Common electrical voltage regulator circuit and common voltage adjusting method |
| CN109509447A (en) * | 2018-12-19 | 2019-03-22 | 惠科股份有限公司 | Common voltage integrated circuit and display device |
| CN109637429A (en) * | 2019-02-18 | 2019-04-16 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| CN109767737A (en) * | 2019-03-07 | 2019-05-17 | 昆山龙腾光电有限公司 | Common voltage compensation method and its display device |
-
2020
- 2020-07-23 CN CN202010715787.5A patent/CN111833826B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990080840A (en) * | 1998-04-22 | 1999-11-15 | 김영환 | Common power supply automatic setting circuit of liquid crystal display device |
| CN101295110A (en) * | 2007-04-25 | 2008-10-29 | 群康科技(深圳)有限公司 | Crystal display device and driving method thereof |
| CN101645244A (en) * | 2008-08-08 | 2010-02-10 | 乐金显示有限公司 | Liquid crystal display device and driving method thereof |
| US20140340383A1 (en) * | 2011-12-07 | 2014-11-20 | Sharp Kabushiki Kaisha | Display device and electrical apparatus |
| CN102842280A (en) * | 2012-08-31 | 2012-12-26 | 京东方科技集团股份有限公司 | Public voltage compensation circuit and method, and liquid crystal display device |
| CN102903344A (en) * | 2012-09-27 | 2013-01-30 | 合肥京东方光电科技有限公司 | Public electrode voltage compensation method and device and time schedule controller |
| CN104658500A (en) * | 2015-03-04 | 2015-05-27 | 京东方科技集团股份有限公司 | Common voltage compensating method and system |
| CN107437407A (en) * | 2017-08-11 | 2017-12-05 | 昆山龙腾光电有限公司 | Public voltage generating circuit and liquid crystal display device |
| CN109377960A (en) * | 2018-12-14 | 2019-02-22 | 深圳市华星光电半导体显示技术有限公司 | Common electrical voltage regulator circuit and common voltage adjusting method |
| CN109509447A (en) * | 2018-12-19 | 2019-03-22 | 惠科股份有限公司 | Common voltage integrated circuit and display device |
| CN109637429A (en) * | 2019-02-18 | 2019-04-16 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| CN109767737A (en) * | 2019-03-07 | 2019-05-17 | 昆山龙腾光电有限公司 | Common voltage compensation method and its display device |
Non-Patent Citations (1)
| Title |
|---|
| 林鸿涛，陈曦，庄子华，赖意强，袁剑峰，邵喜斌: "TFT-LCD公共电压耦合畸变的影响因素及与线残像关系的研究", 《液晶与显示》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112562607A (en) * | 2020-12-17 | 2021-03-26 | 昆山龙腾光电股份有限公司 | Common voltage compensation circuit for display panel, compensation method and display device |
| CN112562607B (en) * | 2020-12-17 | 2022-05-20 | 昆山龙腾光电股份有限公司 | Common voltage compensation circuit for display panel, compensation method and display device |
| TWI785852B (en) * | 2021-10-20 | 2022-12-01 | 大陸商北京集創北方科技股份有限公司 | Pixel compensation method for self-luminous display panel, flat display device and information processing device |
| CN116704970A (en) * | 2023-08-04 | 2023-09-05 | 南京芯视元电子有限公司 | Correction system and method for display signal processing |
| CN116704970B (en) * | 2023-08-04 | 2023-10-24 | 南京芯视元电子有限公司 | Correction system and method for display signal processing |
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