CN111831045A - An active clamp circuit - Google Patents

Abstract

The invention discloses an active clamping circuit, and belongs to the field of integrated circuit design. The clamping circuit aims at the problems that in the prior art, the clamping circuit is large in power consumption, unstable in performance, long in response time, delayed in work and the like. The invention provides an active clamping circuit, comprising: the input stage consists of two reference voltage sources and is used for providing reference voltage for the operational amplifier; the operational amplifier is used for responding to the reference voltage transmitted by the input stage; and the output stage is used for adjusting the output voltage of the operational amplifier and outputting the clamping voltage. The Zener diode in the traditional scheme is replaced, so that the clamping function of quick response is realized, and the power consumption is low when the clamping device does not work; the stable clamping voltage is output through the response of the open-loop active clamping circuit to different voltages, and the normal work of a follow-up circuit is ensured. The method can also reduce the oscillation of the system, reduce the power consumption of the system and improve the stability of the chip during working.

Description

An active clamp circuit

technical field

The present invention relates to the field of integrated circuit design, and more particularly, to an active clamp circuit.

Background technique

With the popularization of equipment terminals in the era of intelligence, more and more multi-functional integrated circuit units are designed and used. In all integrated circuit units, power is required to drive the chip to work, and a stable voltage needs to be provided for the system to use to ensure that the voltage does not exceed the system withstand voltage and protect the system from working normally. In the actual use of the chip, the withstand voltage value of the chip is generally a few volts. If the input voltage is too large, it cannot directly act on the circuit. The voltage value is reduced to a safe voltage by step-down, and then the driver module controls the chip to work. .

In order to prevent the voltage of the input power supply from exceeding the withstand voltage of the chip, many driver chips are equipped with a control module to reduce the input voltage, and the connection clamp potential control voltage does not exceed the preset value to ensure the normal operation of the chip. The traditional method clamps the voltage through a diode clamping circuit to ensure that the voltage value is the reverse conduction voltage of the Zener diode in the circuit to ensure that the subsequent drive module does not exceed the withstand voltage, but this method also generates electricity when it does not work. A large amount of power consumption will lead to an increase in chip power consumption. Using the reverse characteristics of the Zener diode for voltage clamping needs to reach a certain voltage value before reverse breakdown to ensure the stability of the subsequent voltage. However, in practical applications, if the reverse time is too long, it may be caused by excessive voltage. Subsequent circuits are damaged before the clamping voltage is generated. Therefore, how to achieve fast clamping of the power supply voltage, and maintain a stable voltage after clamping, ensure that the chip system is not damaged, and at the same time reduce the power consumption of the clamping is an important research topic in this field.

After searching, a relatively close Chinese invention patent application was obtained, the name of the invention: clamp circuit for bandgap reference source, publication number CN103853223A, published on June 11, 2014, discloses a clamp for bandgap reference source The circuit is to connect a clamping circuit in series between the power supply voltage of the bandgap reference source and the external power supply voltage. The clamping circuit can effectively suppress the instantaneous jump of the power supply voltage and provide a relatively stable power supply voltage for the bandgap reference source. , so that it outputs a stable reference voltage, thereby suppressing the influence of the instantaneous jump of the power supply voltage on the reference voltage. However, this technical solution has a complicated circuit structure, uses a large number of MOS tubes, cannot effectively control power consumption, and cannot effectively control the response time and oscillation of the system.

SUMMARY OF THE INVENTION

1. Technical problems to be solved

In view of the problem of high input voltage of the clamp circuit in the prior art, the traditional diode clamp circuit consumes a lot of power and has unstable performance, the regulation voltage is greatly affected by the performance of the diode, and the response time is long, and there is a delay in the operation. system may cause damage. The present invention provides an active clamp circuit, which can realize a clamp function with faster response and lower power consumption when it is not working by replacing the Zener diode in the traditional scheme. Through the open-loop active clamp circuit, it responds quickly to high voltages, thereby outputting stable low voltages and ensuring the normal operation of subsequent circuits. It can realize fast clamping of the input voltage, and the open-loop control reduces the oscillation of the system, reduces the power consumption of the system, and improves the stability of the chip.

2. Technical solutions

The object of the present invention is achieved through the following technical solutions.

An active clamp circuit, comprising: an input stage, composed of two reference voltage sources, used to provide a reference voltage for an operational amplifier; the operational amplifier, used to respond to the reference voltage from the input stage; an output stage, used to adjust The output voltage of the op amp and the output clamp voltage.

Further, the input stage includes a first reference voltage source for realizing a fast response of the clamping circuit; a second reference voltage source for realizing a slow response of the clamping circuit; wherein the first reference voltage source is greater than the second reference voltage source reference voltage source. The voltage response of the first reference voltage source V _BE is fast but the accuracy is low. In order to realize the fast response of the clamping system, the response is made in a short time when the system starts to work to ensure that the voltage is clamped; the voltage of the second reference voltage source V _REF is The voltage response is slow but the precision is high. After the clamping system starts to work, in order to ensure the stability of the subsequent clamping.

Further, the two reference voltage sources are respectively connected to the two inverting input ends of the operational amplifier.

Further, the output stage includes: a first transistor and a number of resistors for generating a feedback voltage and inputting it to the forward input terminal of the operational amplifier; an isolation loop consisting of a second transistor and a number of resistors for It receives the output voltage of the operational amplifier and generates an intermediate voltage; the output loop, which is composed of a third transistor and several resistors, is used to receive the intermediate voltage of the isolation loop and generate a clamping voltage.

Further, the feedback loop includes a first PMOS transistor, a resistor R1 and a resistor R2, the gate of the first PMOS transistor is connected to the output end of the operational amplifier, the drain is connected to the voltage V _DD , the source is connected to one end of the resistor R1, and the resistor R1 The other end of , respectively, is connected to the positive input of the operational amplifier and the resistor R2. By controlling the PMOS transistor to be turned on and off to control the operation of the operational amplifier, this ensures that the system can ensure lower power consumption when it is not working, thereby reducing the power consumption of the system. Resistors R1 and R2 in the circuit are used to adjust the output voltage of the op amp to obtain a voltage V ₀ close to the clamp value.

Further, the isolation loop includes a second PMOS transistor, a resistor R3 and a resistor R4, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain is connected to the voltage V _DD , and the source is connected to one end of the resistor R3, The other end of the resistor R3 is connected to the resistor R4. The obtained voltage V1 is the same as the above _- mentioned voltage _V0 . This circuit structure can isolate the feedback loop of the operational amplifier and the subsequent output loop from each other, thereby avoiding the instability of the output voltage caused by the circuit oscillation.

Further, the output loop includes a third PMOS transistor and a resistor Rz, the gate of the third PMOS transistor is connected to the source of the second PMOS transistor, the drain is connected to the voltage V _DD , and the source is connected to the resistor Rz. Among them, although the conduction voltage drop V _TH of the PMOS tube is affected by temperature and process, since V ₁ is larger than V _TH , the external influence can be ignored. The other end of the PMOS tube is connected to the current limiting resistor R _Z to ensure that the system will not damage the chip caused by overcurrent.

Further, the feedback loop includes a first PNP tube, a resistor R1 and a resistor R2, the base of the first PNP tube is connected to the output end of the operational amplifier, the collector is connected to the voltage V _DD , the emitter is connected to one end of the resistor R1, and the resistor R1 The other end of , respectively, is connected to the positive input of the operational amplifier and the resistor R2.

Further, the isolation loop includes a second PNP tube, a resistor R3 and a resistor R4, the base of the second PNP tube is connected to the grid of the first PNP tube, the collector is connected to the voltage V _DD , and the emitter is connected to one end of the resistor R3, The other end of the resistor R3 is connected to the resistor R4.

Further, the output loop includes a third PNP tube and a resistor Rz, the base of the third PNP tube is connected to the emitter of the second PNP tube, the collector is connected to the voltage V _DD , and the emitter is connected to the resistor Rz.

3. Beneficial effects

Compared with the prior art, the advantages of the present invention are:

The invention proposes a brand-new circuit structure of an active clamp circuit. Two reference voltages are set to ensure the fast response of the clamp circuit and the stable output after the clamp work; and the feedback loop is isolated by setting MOS. , so that the open-loop control of the system reduces oscillation; finally, the high-voltage clamping effect can be achieved quickly and stably, and a stable low-voltage value can be output.

Description of drawings

Fig. 1 is the circuit schematic diagram of the present invention;

Fig. 2 is the working characteristic schematic diagram of the present invention;

FIG. 3 is another schematic circuit diagram of the present invention.

Numeral description in the figure: 101. first reference voltage source, 102. second reference voltage source, 103. operational amplifier, 104. first PMOS tube, 105. second PMOS tube, 106. third PMOS tube, 204. first PMOS tube A PNP tube, 205. a second PNP tube, 206. a third PNP tube.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

The active clamp circuit disclosed in the present invention has two paths, namely a fast response path composed of V _BE and a slow response path composed of V _REF , so as to clamp the output voltage and ensure the system stability. Compared with the traditional Zener diode structure, the clamping voltage can be obtained faster and more stably, and the power consumption problem caused by the non-working state is also avoided.

Example 1

As shown in FIG. 1, an active clamp circuit of the present invention includes a fast-path reference voltage source 101, a slow-path reference voltage source 102, an operational amplifier 103, three PMOS transistors 104, 105, 106, and the required Voltage divider resistors R1-R4 and current limiting resistor Rz. The above two reference voltage sources are respectively connected to the two inverting input terminals of the operational amplifier, and the operational amplifier 103 inputs the reference voltages of the feedback loop and the two paths. In the early stage of circuit operation, the fast-path reference voltage V _BE is used as the reference, but since the input fast-path reference voltage V _BE is greater than the slow-path reference voltage V _REF , when the slow-path reference voltage V _REF works, the operational amplifier Operates from the slow-path reference voltage, V _REF . The gate of the first PMOS transistor 104 is connected to the output end of the operational amplifier 103, the drain is connected to the voltage V _DD , the source is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to the forward input end of the operational amplifier and the resistor R2; The feedback loop formed by the amplifier 103, the PMOS tube 104 and the resistors R1 and R2 ensures that the circuit maintains a low power consumption when the circuit is not working by controlling the PMOS tube 104 to be turned on and off. At the same time, the voltage obtained by the resistors R1 and R2 is Adjustments are made to obtain the desired output voltage V ₀ . The gate of the second PMOS transistor 105 is connected to the gate of the first PMOS transistor 104, the drain is connected to the voltage V _DD , the source is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the resistor R4; the PMOS transistor 105 and the resistors R3, R4 An isolation loop is formed, which is used to isolate the interference of the feedback loop to the subsequent output and avoid circuit oscillation. At the same time, the output voltage V ₀ obtained by the feedback loop can be transmitted to obtain V ₁ of the same voltage value. The gate _of the third PMOS transistor 106 is connected to the source of the second PMOS transistor 105 , the drain is connected to the voltage V _DD , and the source is connected to the resistance Rz; The output voltage, that is, the voltage value V _Z of the active clamp, the final voltage value is determined by the feedback voltage V ₁ and the conduction voltage drop V _TH of the PMOS transistor, where V ₁ =V*·(R1+R2) /R2, the turn-on voltage drop V _TH is less than the obtained voltage value, and will not have a great impact on the final voltage result of the circuit. At the same time, the resistance R _Z is the current limiting resistance of the circuit, which controls the output current not to be too high and prevents the output current from causing damage to the subsequent circuit.

When the clamp circuit is working, the fast-path reference voltage V _BE is used as the reference voltage of fast response, and its response time is fast but the precision is low. When the system starts, _VBE can quickly respond to the voltage, make the clamp circuit work, adjust the voltage to the required voltage range, and ensure that the system can operate normally in the early stage of operation, and the system will not be caused by the slow response. If the voltage is too large, it will be damaged. If the ratio of R3/R4 is the same as the ratio of R1/R2, the V _DD clamping voltage during fast startup can be obtained as follows: V _DD =V _TH +V*·(R1+R2 )/R2, the maximum clamping current I _DD =(V _DD -V _DS )/Rz, where V* is the input voltage obtained by the positive terminal of the operational amplifier according to the virtual short principle, at this time the feedback voltage V*=V _BE . V _TH is the threshold voltage of the PMOS transistor 106 , and V _DS is the source-drain voltage of the PMOS transistor 106 . The slow-path reference voltage V _REF is input for a period of time after the system works, and its response time is slow but the accuracy is high. When the system has been started from the fast path, it can clamp the output voltage with a small change. At this time, the function of the slow path reference voltage ensures that the output voltage of the system is more accurate, reduces the voltage fluctuation, and ensures the stability of the system. If the ratio of R3/R4 is the same as the ratio of R1/R2, the V _DD clamping voltage during slow start can be obtained as: V _DD =V _TH +V*·(R1+R2)/R2, the maximum The clamping current I _DD =(V _DD -V _DS )/Rz, and the feedback voltage V*=V _REF at this time.

As shown in Figure 2, the traditional diode clamp circuit uses a Zener diode as a key device. Using its reverse characteristics, after the reverse bias voltage reaches a certain voltage value V _Z , the voltage value will remain relatively constant, which is different from the current flowing through it. The value is irrelevant and will not change even if the current varies over a wide range. When the current value does not exceed the maximum rated current I _Z (max), the voltage will output a fixed value. The invention replaces the Zener diode, and also realizes its reverse characteristic. When the voltage value reaches the preset clamping voltage value Vz, the voltage will be fixed, and a current limiting resistor is set to limit the rated current. The advantage of the present invention is that the forward characteristic of the diode is avoided, and a more stable clamping function is realized.

Example 2

As shown in FIG. 3 , under the condition that other circuit structures remain unchanged, the PMOS transistors 104 , 105 , and 106 in the output stage of the clamp circuit can be replaced with PNP transistors 204 , 205 , and 206 according to actual circuit requirements or design requirements. The feedback loop includes a first PNP tube 204, a resistor R1 and a resistor R2. The base of the first PNP tube 204 is connected to the output end of the operational amplifier, the collector is connected to the voltage V _DD , the emitter is connected to one end of the resistor R1, and the other end of the resistor R1 is connected. One end is respectively connected to the forward input terminal of the operational amplifier and the resistor R2; the isolation loop includes a second PNP tube 205, a resistor R3 and a resistor R4, the base of the second PNP tube 205 is connected to the grid of the first PNP tube, and the collector is connected to the voltage V _DD , the emitter is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the resistor R4; the output loop includes a third PNP tube 206 and a resistor Rz, and the base of the third PNP tube 206 is connected to the emitter of the second PNP tube 205, The collector is connected to the voltage V _DD , and the emitter is connected to the resistor Rz. At this time, the function realized by the circuit remains unchanged, and the circuit also belongs to the protection scope of this patent.

The invention and its embodiments have been described above schematically, and the description is not restrictive. The invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. What is shown in the accompanying drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto, and any reference signs in the claims shall not limit the related claims. Therefore, if those of ordinary skill in the art are inspired by it, and without departing from the purpose of the present invention, any structure and embodiment similar to this technical solution are designed without creativity, which shall belong to the protection scope of this patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of that element. Several elements recited in a product claim can also be implemented by one element by means of software or hardware. The terms first, second, etc. are used to denote names and do not denote any particular order.

Claims (10)

1. An active clamp circuit, characterized in that, comprising: The input stage, consisting of two reference voltage sources, is used to provide the reference voltage for the operational amplifier; Operational amplifier, used to respond to the reference voltage from the input stage; The output stage is used to adjust the output voltage of the op amp and output the clamp voltage. 2 . The active clamp circuit according to claim 1 , wherein the input stage comprises a first reference voltage source for realizing fast response of the clamp circuit; a second reference voltage source for A slow response of the clamping circuit is achieved; wherein the first reference voltage source is larger than the second reference voltage source. 3 . The active clamp circuit according to claim 2 , wherein the two reference voltage sources are respectively connected to two inverting input ends of the operational amplifier. 4 . 4. The active clamp circuit according to claim 1, wherein the output stage comprises: A feedback loop, consisting of a first transistor and a number of resistors, is used to generate a feedback voltage and transmit it to the positive input terminal of the operational amplifier; An isolation loop, consisting of a second transistor and several resistors, is used to receive the output voltage of the operational amplifier and generate an intermediate voltage; The output loop is composed of a third transistor and several resistors, and is used to receive the intermediate voltage of the isolation loop and generate a clamping voltage. 5 . The active clamp circuit according to claim 4 , wherein the feedback loop comprises a first PMOS transistor, a resistor R1 and a resistor R2 , and the gate of the first PMOS transistor is connected to the output end of the operational amplifier 5 . , the drain is connected to the voltage V _DD , the source is connected to one end of the resistor R1 , and the other end of the resistor R1 is connected to the positive input end of the operational amplifier and the resistor R2 respectively. 6 . The active clamp circuit according to claim 5 , wherein the isolation loop comprises a second PMOS transistor, a resistor R3 and a resistor R4 , and the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor. 7 . The gate and the drain are connected to the voltage V _DD , the source is connected to one end of the resistor R3 , and the other end of the resistor R3 is connected to the resistor R4 . 7. The active clamp circuit according to claim 6, wherein the output loop comprises a third PMOS transistor and a resistor Rz, and the gate of the third PMOS transistor is connected to the source of the second PMOS transistor, The drain is connected to the voltage V _DD , and the source is connected to the resistor Rz. 8 . The active clamp circuit according to claim 4 , wherein the feedback loop comprises a first PNP tube, a resistor R1 and a resistor R2 , and the base of the first PNP tube is connected to the output end of the operational amplifier 8 . , the collector is connected to the voltage V _DD , the emitter is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to the forward input end of the operational amplifier and the resistor R2. 9 . The active clamp circuit according to claim 8 , wherein the isolation loop comprises a second PNP tube, a resistor R3 and a resistor R4 , and the base of the second PNP tube is connected to the base of the first PNP tube. 10 . The gate and the collector are connected to the voltage V _DD , the emitter is connected to one end of the resistor R3 , and the other end of the resistor R3 is connected to the resistor R4 . 10. An active clamp circuit according to claim 9, wherein the output loop comprises a third PNP tube and a resistor Rz, the base of the third PNP tube is connected to the emitter of the second PNP tube, and the collector The voltage V _DD is connected, and the emitter is connected to the resistor Rz.

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