CN111831045A

CN111831045A - Active clamping circuit

Info

Publication number: CN111831045A
Application number: CN202010757949.1A
Authority: CN
Inventors: 宋霄; 张若平; 高润芃; 蒋召宇; 何书专; 施云飞
Original assignee: Nanjing Huanxuan Semiconductor Co ltd
Current assignee: Nanjing Huanxuan Semiconductor Co ltd
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2020-10-27

Abstract

The invention discloses an active clamping circuit, and belongs to the field of integrated circuit design. The clamping circuit aims at the problems that in the prior art, the clamping circuit is large in power consumption, unstable in performance, long in response time, delayed in work and the like. The invention provides an active clamping circuit, comprising: the input stage consists of two reference voltage sources and is used for providing reference voltage for the operational amplifier; the operational amplifier is used for responding to the reference voltage transmitted by the input stage; and the output stage is used for adjusting the output voltage of the operational amplifier and outputting the clamping voltage. The Zener diode in the traditional scheme is replaced, so that the clamping function of quick response is realized, and the power consumption is low when the clamping device does not work; the stable clamping voltage is output through the response of the open-loop active clamping circuit to different voltages, and the normal work of a follow-up circuit is ensured. The method can also reduce the oscillation of the system, reduce the power consumption of the system and improve the stability of the chip during working.

Description

Active clamping circuit

Technical Field

The invention relates to the field of integrated circuit design, in particular to an active clamping circuit.

Background

With the popularization of the device terminals in the intelligent era, more and more multifunctional integrated circuit units are designed and used. In all integrated circuit units, a power supply is needed to drive the chip to work, and stable voltage needs to be provided for a system to use so as to ensure that the voltage does not exceed the withstand voltage of the system and protect the normal work of the system. In the use of an actual chip, the withstand voltage value of the chip is generally several volts, if the input voltage is overlarge, the withstand voltage value cannot be directly acted on a circuit, and the voltage value is reduced to the safe voltage by voltage reduction and then the drive module control chip works.

In order to prevent the voltage of an input power supply from exceeding the withstand voltage of the chip, a control module is added in front of a plurality of driving chips to reduce the input voltage, and the clamp potential is connected to control the voltage not to exceed a preset value, so that the normal work of the chip is ensured. In the traditional method, a diode clamping circuit is used for clamping voltage, the voltage value is ensured to be the reverse conducting voltage of a Zener diode in the circuit, and the follow-up driving module is ensured not to exceed withstand voltage. The reverse characteristic of the Zener diode is utilized to clamp the voltage, the reverse breakdown is carried out only when a certain voltage value is reached, the stability of the subsequent voltage is ensured, but in the practical application, if the reverse time is too long, the subsequent circuit is damaged before the clamping voltage is generated due to the overlarge voltage. Therefore, how to realize fast clamping of the power supply voltage and maintain a stable voltage after clamping, so as to ensure that the system on chip is not damaged and reduce the power consumption of clamping is an important research topic in the field.

Through retrieval, a closer Chinese invention patent application is obtained, and the invention name is as follows: a clamping circuit of a band gap reference source is disclosed in CN103853223A, published 2014, 06, 11, and can effectively inhibit the instant jump of a power supply voltage, provide a relatively stable power supply voltage for the band gap reference source, output the stable reference voltage and inhibit the influence of the instant jump of the power supply voltage on the reference voltage. However, the technical scheme has a complex circuit structure, the number of the MOS tubes is large, the power consumption cannot be effectively controlled, and the response time and the oscillation of the system cannot be effectively controlled.

Disclosure of Invention

1. Technical problem to be solved

Aiming at the problem that the input voltage of a clamping circuit is high in the prior art, the traditional diode clamping circuit is high in power consumption and unstable in performance, the influence of the performance of a diode on the regulated voltage is large, the response time is long, work is delayed, and damage to a chip system is possibly caused. The invention provides an active clamping circuit, which realizes a clamping function with quick response by replacing a Zener diode in the traditional scheme and has lower power consumption when not in work. The active clamping circuit with the open loop is used for quickly responding to high voltage, so that stable low voltage is output, and the normal work of a follow-up circuit is guaranteed. The clamp can clamp the input voltage quickly, and the oscillation of the system is reduced due to open-loop control, so that the power consumption of the system is reduced, and the stability of a chip is improved.

2. Technical scheme

The purpose of the invention is realized by the following technical scheme.

An active clamp circuit comprising: the input stage consists of two reference voltage sources and is used for providing reference voltage for the operational amplifier; the operational amplifier is used for responding to the reference voltage transmitted by the input stage; and the output stage is used for adjusting the output voltage of the operational amplifier and outputting the clamping voltage.

Further, the input stage comprises a first reference voltage source for realizing the fast response of the clamping circuit; the second reference voltage source is used for realizing the slow response of the clamping circuit; wherein the first reference voltage source is larger than the second reference voltage source. First reference voltage source V_BEThe voltage response is fast but the precision is low, in order to realize the fast response of the clamping system, the response is carried out in a short time when the system starts to work, and the voltage is ensured to be clamped; a second reference voltage source V_REFHas a slow voltage response but high accuracy in the clamping systemAfter the system starts to work, the stability of subsequent clamping is ensured.

Further, the two reference voltage sources are respectively connected with two inverted input ends of the operational amplifier.

Further, the output stage includes: the operational amplifier consists of a first transistor and a plurality of resistors and is used for generating a feedback voltage and inputting the feedback voltage to a positive input end of the operational amplifier; the isolation loop consists of a second transistor and a plurality of resistors and is used for receiving the output voltage of the operational amplifier and generating an intermediate voltage; and the output loop consists of a third transistor and a plurality of resistors and is used for receiving the intermediate voltage of the isolation loop and generating a clamping voltage.

Further, the feedback loop comprises a first PMOS tube, a resistor R1 and a resistor R2, wherein the gate of the first PMOS tube is connected with the output end of the operational amplifier, and the drain of the first PMOS tube is connected with the voltage V_DDThe source is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to the positive input terminal of the operational amplifier and the resistor R2, respectively. The PMOS tube is controlled to be switched on and off to control the operation of the operational amplifier, so that the system can ensure lower power consumption when not working, and the power consumption of the system is reduced. Resistors R1 and R2 in the circuit are used for adjusting the output voltage of the operational amplifier so as to obtain a voltage V close to the clamp value₀。

Further, the isolation loop comprises a second PMOS tube, a resistor R3 and a resistor R4, wherein the gate of the second PMOS tube is connected with the gate of the first PMOS tube, and the drain of the second PMOS tube is connected with a voltage V_DDThe source is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the resistor R4. To obtain a voltage V₁With the above voltage V₀The same is true. The circuit structure can isolate the feedback loop of the operational amplifier from the subsequent output loop, and avoid unstable output voltage caused by circuit oscillation.

Furthermore, the output loop comprises a third PMOS tube and a resistor Rz, wherein the grid electrode of the third PMOS tube is connected with the source electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with a voltage V_DDAnd the source is connected with a resistor Rz. Wherein the conduction voltage drop V of the PMOS tube_THAlthough affected by temperature and process, due to V₁Phase contrast V_THIs largerThe influence caused by the outside can be ignored. The other end of the PMOS tube and a current-limiting resistor R_ZAnd the system is ensured not to be damaged by the chip caused by overcurrent.

Further, the feedback loop comprises a first PNP tube, a resistor R1 and a resistor R2, wherein the base electrode of the first PNP tube is connected with the output end of the operational amplifier, and the collector electrode of the first PNP tube is connected with the voltage V_DDThe emitter is connected with one end of a resistor R1, and the other end of the resistor R1 is respectively connected with the positive input end of the operational amplifier and the resistor R2.

Further, the isolation loop comprises a second PNP tube, a resistor R3 and a resistor R4, wherein the base electrode of the second PNP tube is connected with the grid electrode of the first PNP tube, and the collector electrode of the second PNP tube is connected with a voltage V_DDThe emitter is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the resistor R4.

Further, the output loop comprises a third PNP tube and a resistor Rz, the base electrode of the third PNP tube is connected with the emitter electrode of the second PNP tube, and the collector electrode is connected with a voltage V_DDAnd an emitter is connected with the resistor Rz.

3. Advantageous effects

Compared with the prior art, the invention has the advantages that:

the invention provides a brand-new circuit structure of an active clamping circuit, which ensures the quick response of the clamping circuit and the stable output after clamping work by setting two reference voltages; the feedback loop is isolated by setting an MOS (metal oxide semiconductor), so that the system is controlled by open loop to reduce oscillation; and finally, the high-voltage clamping effect can be quickly and stably realized, a stable low-voltage value is output, and the current is controlled through the current-limiting resistor to prevent the device from being damaged and protect the stable work of the chip.

Drawings

FIG. 1 is a schematic circuit diagram of the present invention;

FIG. 2 is a schematic representation of the operating characteristics of the present invention;

fig. 3 is another circuit schematic of the present invention.

The reference numbers in the figures illustrate: 101. the PNP circuit comprises a first reference voltage source, 102, a second reference voltage source, 103, an operational amplifier, 104, a first PMOS tube, 105, a second PMOS tube, 106, a third PMOS tube, 204, a first PNP tube, 205, a second PNP tube, 206 and a third PNP tube.

Detailed Description

The invention is described in detail below with reference to the drawings and specific examples.

The active clamping circuit disclosed by the invention has two paths, wherein each path is composed of V_BEComposed fast response path and V_REFAnd the formed slow response path realizes clamping of output voltage and ensures system stability. Compare traditional zener diode structure, can be faster more stable obtain the clamping voltage, also avoid the power consumption problem that non-operating state caused simultaneously.

Example 1

As shown in fig. 1, an active clamp circuit of the present invention includes a fast-path reference voltage source 101, a slow-path reference voltage source 102, an operational amplifier 103, three

PMOS transistors

104, 105, 106, and required voltage dividing resistors R1-R4 and current limiting resistors Rz. The two reference voltage sources are respectively connected with two inverted input ends of the operational amplifier, and the operational amplifier 103 inputs reference voltages of a feedback loop and two paths. At the initial stage of circuit operation, the fast channel reference voltage V with fast response_BEAs a reference, but due to the fast path of the input reference voltage V_BEGreater than the slow path reference voltage V_REFTherefore, at a low-speed passage, the reference voltage V_REFIn operation, the operational amplifier will be at a reference voltage V at a slow pass_REFWork as a benchmark. The gate of the first PMOS transistor 104 is connected to the output terminal of the operational amplifier 103, and the drain is connected to the voltage V_DDThe source electrode is connected with one end of a resistor R1, and the other end of the resistor R1 is respectively connected with the positive input end of the operational amplifier and a resistor R2; the operational amplifier 103, the PMOS transistor 104 and the feedback loop formed by the resistors R1 and R2 ensure that the circuit keeps low power consumption in the non-operating state by controlling the on/off of the PMOS transistor 104, and the obtained voltage is adjusted by the resistors R1 and R2 to obtain the desired output voltage V₀. The grid electrode of the second PMOS tube 105 is connected with the grid electrode of the first PMOS tube 104, and the drain electrode is connected with a voltage V_DDA source connected to one end of a resistor R3 and another resistor R3One end of the resistor is connected with the resistor R4; the PMOS tube 105 and the resistors R3 and R4 form an isolation loop for isolating the interference of the feedback loop on the subsequent output, and the circuit oscillation is avoided. At the same time, the output voltage V obtained by the feedback loop₀Transmitting to obtain V with the same voltage value₁. The grid electrode of the third PMOS tube 106 is connected with the source electrode of the second PMOS tube 105, and the drain electrode is connected with the voltage V_DDThe source electrode is connected with a resistor Rz; PMOS transistor 105 obtains the same voltage V₁Then, the final output voltage, i.e. the voltage value V of the active clamp, is obtained after passing through the PMOS tube 106_ZAnd the final voltage value is the voltage V obtained by feedback₁And conduction voltage drop V of PMOS tube_THDetermination of where V₁V · (R1+ R2)/R2, and a conduction voltage drop V_THAnd the voltage value is smaller than the obtained voltage value, so that the final voltage result of the circuit cannot be greatly influenced. Simultaneous resistance R_ZThe current limiting resistor of the circuit controls the output current not to be too high, and prevents the output current from damaging subsequent circuits.

When the clamping circuit works, the reference voltage V is quickly switched on_BEAs a reference voltage with a fast response, its response time is fast but its accuracy is low. When the system starts, V_BEThe voltage can be quickly responded, the clamping circuit works, the voltage is adjusted to be within the range of the required voltage, the system can be ensured to normally operate in the initial working period, the system voltage cannot be damaged due to overlarge voltage caused by slow response, and if the ratio value of R3/R4 is the same as the ratio value of R1/R2, the V during quick start can be obtained_DDThe clamping voltage is: v_DD＝V_TH+ V · (R1+ R2)/R2, maximum clamping current I_DD＝(V_DD-V_DS) V is input voltage obtained by positive end of operational amplifier according to virtual short principle, and feedback voltage is V ═ V at this time_BE。V_THIs the threshold voltage, V, of the PMOS transistor 106_DSIs the source-drain voltage of the PMOS transistor 106. Reference voltage V of slow-speed passage road_REFThe input is started after a period of time after the system works, and the response time is slow but the precision is high. When the system is started by the fast access, the output voltage with small change amplitude can be clamped, and the action of the reference voltage of the slow access ensures that the system is started by the fast accessThe output voltage of the system is more accurate, the voltage fluctuation is reduced, the system stability is ensured, and if the ratio value of R3/R4 is the same as the ratio value of R1/R2, the V during the slow start can be obtained_DDThe clamping voltage is: v_DD＝V_TH+ V · (R1+ R2)/R2, maximum clamping current I_DD＝(V_DD-V_DS) Rz, when the feedback voltage V ═ V_REF。

Referring to fig. 2, the conventional diode clamp circuit uses a zener diode as a key device, and utilizes its reverse characteristic to bias the zener diode to a certain voltage V in the reverse direction_ZThereafter, the voltage value will remain relatively constant regardless of the value of the flowing current, and will not change even if the current changes over a wide range. At current values not exceeding the maximum rated current I_Z(max), the voltage will output a fixed value. The invention replaces a Zener diode, also realizes the reverse characteristic, when the voltage value reaches the preset clamping voltage value Vz, the voltage is fixed and unchanged, and meanwhile, a current limiting resistor is arranged to limit the rated current. The invention has the advantages of avoiding the forward characteristic of the diode and realizing more stable clamping function.

Example 2

As shown in fig. 3, the

PMOS transistors

104, 105, 106 in the output stage of the clamp circuit can be replaced by

PNP transistors

204, 205, 206 according to actual circuit requirements or design requirements. The feedback loop comprises a first PNP tube 204, a resistor R1 and a resistor R2, wherein the base of the first PNP tube 204 is connected with the output end of the operational amplifier, and the collector is connected with a voltage V_DDThe emitter is connected with one end of a resistor R1, and the other end of the resistor R1 is respectively connected with the positive input end of the operational amplifier and the resistor R2; the isolation loop comprises a second PNP tube 205, a resistor R3 and a resistor R4, wherein the base electrode of the second PNP tube 205 is connected with the grid electrode of the first PNP tube, and the collector electrode of the second PNP tube is connected with a voltage V_DDThe emitter is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the resistor R4; the output loop comprises a third PNP tube 206 and a resistor Rz, the base electrode of the third PNP tube 206 is connected with the emitter electrode of the second PNP tube 205, and the collector electrode is connected with a voltage V_DDAnd an emitter is connected with the resistor Rz. The function realized by the circuit is not changed at the momentThe circuit also belongs to the protection scope of the patent.

The invention and its embodiments have been described above schematically, without limitation, and the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The representation in the drawings is only one of the embodiments of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not limit the claims concerned. Therefore, if a person skilled in the art receives the teachings of the present invention, without inventive design, a similar structure and an embodiment to the above technical solution should be covered by the protection scope of the present patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Several of the elements recited in the product claims may also be implemented by one element in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.

Claims

1. An active clamp circuit, comprising:

the input stage consists of two reference voltage sources and is used for providing reference voltage for the operational amplifier;

the operational amplifier is used for responding to the reference voltage transmitted by the input stage;

and the output stage is used for adjusting the output voltage of the operational amplifier and outputting the clamping voltage.

2. An active clamp circuit according to claim 1, wherein the input stage comprises a first reference voltage source for achieving a fast response of the clamp circuit; the second reference voltage source is used for realizing the slow response of the clamping circuit; wherein the first reference voltage source is larger than the second reference voltage source.

3. The active clamp circuit of claim 2, wherein the two reference voltage sources are respectively connected to two inverting input terminals of the operational amplifier.

4. The active clamp circuit of claim 1, wherein the output stage comprises:

the feedback loop consists of a first transistor and a plurality of resistors and is used for generating a feedback voltage and transmitting the feedback voltage to the positive input end of the operational amplifier;

the isolation loop consists of a second transistor and a plurality of resistors and is used for receiving the output voltage of the operational amplifier and generating an intermediate voltage;

and the output loop consists of a third transistor and a plurality of resistors and is used for receiving the intermediate voltage of the isolation loop and generating a clamping voltage.

5. The active clamp circuit of claim 4, wherein the feedback loop comprises a first PMOS transistor having a gate connected to the output of the operational amplifier and a drain connected to the voltage V, a resistor R1 and a resistor R2_DDThe source is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to the positive input terminal of the operational amplifier and the resistor R2, respectively.

6. The active clamp circuit of claim 5, wherein the isolation loop comprises a second PMOS transistor, a resistor R3 and a resistor R4, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the voltage V_DDThe source is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the resistor R4.

7. The active clamp circuit of claim 6, wherein the output loop comprises a third PMOS transistor and a resistor Rz, wherein a gate of the third PMOS transistor is connected to a source of the second PMOS transistor, and a drain of the third PMOS transistor is connected to a voltage V_DDAnd the source is connected with a resistor Rz.

8. The active clamp circuit of claim 4, wherein the feedback loop comprises a first PNA P tube, a resistor R1 and a resistor R2, wherein the base of the first PNP tube is connected with the output end of the operational amplifier, and the collector is connected with a voltage V_DDThe emitter is connected with one end of a resistor R1, and the other end of the resistor R1 is respectively connected with the positive input end of the operational amplifier and the resistor R2.

9. The active clamp circuit of claim 8, wherein the isolation loop comprises a second PNP transistor, a resistor R3 and a resistor R4, wherein the base of the second PNP transistor is connected to the gate of the first PNP transistor, and the collector of the second PNP transistor is connected to the voltage V_DDThe emitter is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the resistor R4.

10. The active clamp circuit of claim 9, wherein the output loop comprises a third PNP transistor and a resistor Rz, the base of the third PNP transistor is connected to the emitter of the second PNP transistor, and the collector is connected to the voltage V_DDAnd an emitter is connected with the resistor Rz.