CN111829670A - Uncooled infrared focal plane array reading circuit - Google Patents
Uncooled infrared focal plane array reading circuit Download PDFInfo
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- CN111829670A CN111829670A CN201910305921.1A CN201910305921A CN111829670A CN 111829670 A CN111829670 A CN 111829670A CN 201910305921 A CN201910305921 A CN 201910305921A CN 111829670 A CN111829670 A CN 111829670A
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Abstract
This specification provides a non-refrigeration infrared focal plane array readout circuit, readout circuit is including M N array circuit and mirror image circuit, readout circuit still includes: bias voltage generating means for providing dynamic bias voltages to said M x N array circuit and said mirror circuit, respectively, said bias voltage generating means comprising: a sensing resistor, the resistance of which linearly changes with the temperature of the substrate on the readout circuit; and the bias voltage generating module is used for generating dynamic bias voltage related to the resistance value according to preset fixed bias voltage and the resistance value of the sensing resistor so as to provide the dynamic bias voltage for the pixel in the M x N array circuit and two ends of the sensor resistor in the mirror image circuit. Therefore, the influence of the change of the substrate temperature on the response rate of the output voltage of the readout circuit is reduced, and the problem that the output voltage of the uncooled infrared focal plane array detector exceeds the dynamic range at high temperature is solved.
Description
Technical Field
The specification relates to the technical field of infrared imaging, in particular to an uncooled infrared focal plane array reading circuit.
Background
At present, the uncooled infrared imaging technology has important application in the fields of military, industry and agriculture, medicine, astronomy and the like. The infrared focal plane array as the core of the uncooled infrared imaging technology comprises an infrared detector array and a reading circuit. The microbolometer Focal Plane Array (FPA) has high sensitivity, is an uncooled infrared focal plane array which is most widely applied, and has the working principle that the temperature changes after a thermosensitive material absorbs incident infrared radiation, so that the resistance value of the thermosensitive material changes, and the size of an infrared radiation signal is detected by measuring the change of the resistance value.
Microbolometers generally adopt a cantilever beam microbridge structure manufactured by a micromachining technology. The bridge deck is deposited with a layer of thermosensitive material with high Temperature Coefficient of Resistance (TCR), and is supported by two legs with good mechanical properties and plated with conductive material, the contact points of the legs and the substrate are piers, which are electrically connected to a silicon readout circuit (ROIC) under a microbolometer. The thermosensitive material is connected to the electric channel of the reading circuit through the bridge legs and the bridge piers to form a pixel unit sensitive to temperature and connected to the reading circuit.
The sensitive pixel unit is also called as a sensitive micro-bolometer, and two blind micro-bolometers are corresponding to the sensitive pixel unit, wherein one bridge deck and the substrate are in thermal short circuit, and the temperature is constantly equal to the temperature of the substrate, so that the sensitive pixel unit is called as a thermal short-circuit micro-bolometer; the other is a shielded microbolometer, which is identical in structure to the sensitive microbolometer but is shielded so that it cannot sense the target radiation, and is called a shielded microbolometer. The two blind micro bolometers can effectively counteract the output voltage fluctuation caused by the resistance value of the sensitive pixel unit along with the temperature change of the substrate, and realize the function without TEC (thermoelectric cooler).
The read-out circuit is used for processing and reading out the signals of the microbolometer, and has important influence on the performance of the infrared imaging system. In recent years, users have higher and higher requirements on infrared focal plane array detector assemblies, and the infrared focal plane array detector assemblies not only have high requirements on performance, but also have low power consumption, simplicity and easiness in use. The traditional infrared focal plane array detector assembly needs to strictly control the substrate temperature by using a TEC (thermoelectric cooler), so that the performance of the detector is not influenced by the temperature fluctuation of the substrate. However, although the substrate temperature is strictly controlled, the absolute value of the responsivity of the output of the readout circuit increases with the increase of the substrate temperature at high temperature of the probe, which leads to the output voltage exceeding the dynamic range.
Disclosure of Invention
In order to overcome the problems in the related art, the uncooled infrared focal plane array reading circuit provided by the specification reduces the influence of the temperature fluctuation of the substrate on the output response rate of the detector.
According to a first aspect of the embodiments of the present specification, there is provided an uncooled infrared focal plane array readout circuit, the readout circuit including an M × N array circuit for configuring an infrared focal plane array, and a mirror circuit for mirror symmetry with pixels at intersections of rows and columns in the M × N array circuit, the readout circuit further including: bias voltage generating means for providing dynamic bias voltages to any column of the M x N array circuits and the mirror circuits, respectively, the bias voltage generating means comprising:
a sensing resistor, the resistance of which linearly changes with the temperature of the substrate on the readout circuit;
and the bias voltage generating module is used for generating dynamic bias voltage related to the resistance value according to preset fixed bias voltage and the resistance value of the sensing resistor so as to provide the dynamic bias voltage for two ends of the sensor resistor in the M x N array circuit and the mirror image circuit.
The technical scheme provided by the embodiment of the specification can have the following beneficial effects:
in the embodiment of the specification, a bias voltage generating device is designed, and the bias voltage generating device is used for generating a dynamic bias voltage which linearly changes along with the temperature of a substrate; then, an uncooled infrared focal plane array reading circuit is improved, and the obtained dynamic bias voltage is used for obtaining bias voltages at two ends of an auxiliary resistor (dummy resistor) and/or a sensor resistor in the reading circuit. Compared with the prior art (adding a fixed bias voltage at two ends of the dummy resistor and the sensor resistor), the change of the response rate of the output voltage of the reading circuit caused by the temperature change of the substrate is effectively eliminated, and the problem that the output voltage of the infrared focal plane array detector exceeds the dynamic range at high temperature is further avoided. The auxiliary resistor and the sensor resistor are made of the same sensitive material so as to offset the bias current of the sensor resistor and eliminate the change of the output voltage of the reading circuit caused by the temperature change of the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.
Fig. 1 is a circuit schematic diagram of a related art uncooled infrared focal plane array readout circuit.
FIG. 2 is a schematic diagram of a bias voltage generating device shown in accordance with an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic diagram illustrating the components of a bias voltage generating device according to an exemplary embodiment.
Fig. 4 is a circuit connection diagram illustrating a bias voltage generating device according to an exemplary embodiment.
Fig. 5 is another circuit connection diagram of a bias voltage generating device according to another exemplary embodiment.
Figure 6 is a circuit diagram illustrating an uncooled infrared focal plane array readout circuit according to one exemplary embodiment.
Figure 7 is a circuit diagram illustrating another uncooled infrared focal plane array readout circuit in accordance with another exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the appended claims.
The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
As shown in fig. 1, fig. 1 is a circuit schematic diagram of an uncooled infrared focal plane array readout circuit in the prior art. As can be seen from fig. 1, the readout circuit includes a mirror circuit located outside the dashed box, and an M × N array circuit located inside the dashed box. The M-N array circuit can be divided into M rows, and each row is provided with an auxiliary resistor Rd(dummy resistance) and N sensor resistances (sensor resistance), the auxiliary resistance R being in the ith columndA first field effect transistor M is arranged between the sensor resistor and the columnp<i>And a second field effect transistor Mn<i>Since the column circuits in the M x N array circuit are symmetrical to each other, any column is selected to illustrate the scheme of the present application, wherein the first fet and the second fet in the selected column are simply labeled as MpAnd Mn. In the selected row, the first field effect transistor MpAnd the second field effect transistor M in the columnnThe drain electrode of the first field effect transistor MpIs connected to the auxiliary resistor R of the columndSaid second field effect transistor MnIs connected to the sensor resistor R of the columns. Wherein each column also corresponds toThere is an integrating amplifier circuit for outputting the output voltage of the readout circuit. The input end of the integral amplifying circuit obtains the first field effect transistor MpOr the second field effect transistor M of the columnnOf the drain electrode. Each sensor resistor is connected with a gating switch in series, only one sensor resistor in the M x N array is gated each time during work through the control of the gating switch, and a circuit corresponding to a column where the gated sensor resistor is located is symmetrical to a mirror image circuit. That is, there is also a corresponding auxiliary resistor R on the mirror circuitd,chipA first field effect transistor M4A second field effect transistor M3And a sensor resistance Rs,chip(ii) a Because of mirror symmetry, the connection relationship between the components in the mirror circuit is not described in detail. Wherein, the mirror image circuit is in mirror symmetry with the pixel at the intersection of the row and the column in the M x N array circuit, wherein the pixel refers to the sensor resistor R at a certain row and a certain columnsA first field effect transistor MpWith the second field-effect transistor M in the columnnAuxiliary resistor RdAnd a conducting unit configured to sense the response current. By adjusting the resistance values of the auxiliary resistor and the sensor resistor in the mirror circuit, noise can be reduced and the magnitude of the bias voltage can be adjusted.
First field effect transistor M in the mirror image circuit4The grid of the first field effect transistor and the grid of the first field effect transistor corresponding to any column in the M x N array circuit are all input with a fixed bias voltage V generated by a bias voltage generating deviceEBOr, a second field effect transistor M in the mirror circuit3And a second field effect transistor M corresponding to any column in the M x N array circuitnAll the gates of the first and second transistors are inputted with a fixed bias voltage V generated by a bias voltage generating deviceFID。
In practical application, the change of external infrared radiation can cause the resistance value of the sensor resistor to change, the response rate of the output voltage of the reading circuit is in direct proportion to the bias voltage at two ends of the sensor resistor, and in order to obtain relatively high response rate, a large bias voltage needs to be added at two ends of the sensor resistor. Thus, the bias current through the sensor resistor will also be large, causingIt is difficult to accurately and sensitively reflect the change of the output signal caused by the change of the resistance value of the sensor resistor. Therefore, an auxiliary resistor is designed for each column, and the bias current is cancelled by the current flowing through the auxiliary resistor. To ensure the auxiliary resistor R flows throughdThe current of the auxiliary resistor R is consistent with the change of the bias current under different substrate temperaturesdThe same thermosensitive material as the sensor resistor and the sensor resistor R are also adoptedsThe difference is that: by adding reflecting layer or increasing thermal conductance, the resistor R is assisteddIt is insensitive to the infrared radiation of the external detection target (i.e., "shielded microbolometer" in the background art).
As can be seen in the prior art, as the substrate temperature increases, the sensor resistance RsAnd an auxiliary resistor RdThe resistance value of the sensing circuit is reduced by the same amplitude, so that the change of the output voltage of the sensing circuit caused by the temperature change of the substrate is eliminated. However, when the infrared focal plane array detector operates in a high temperature environment, the sensor resistance RsAnd an auxiliary resistor RdThe resistance value of the alloy can be reduced to about 0.3 to 0.5 of the resistance value at normal temperature. The first field effect transistor M corresponding to any column in the M-N array circuitpAnd the second field effect transistor MnThe grid of the sensor is all input with a fixed bias voltage, so that the sensor resistance R of the column where the sensor resistance is gated is positionedsAnd an auxiliary resistor RdWill also remain unchanged, respectively: vb,sAnd Vb,d. Thus, the expression for the output voltage of the sensing circuit is:
wherein, the VoFor the output voltage, the amplification factor of the integrating-amplifying circuit, TintIs the integration time of the integrating and amplifying circuit, CintIs the integrating capacitance of the integrating amplifying circuit.
And the sensor resistance RsAnd an auxiliary resistor RdThe expression containing the resistance temperature coefficient is as follows:
Rd＝Rd0×(1-TCR×TS)
Rs＝Rs0×(1-TCR×TS)×(1-α×TCR×Tt)
wherein R isd0Is the resistance value of the auxiliary resistor at standard temperature, Rs0Is a sensor resistance R at a standard temperaturesThe auxiliary resistor and the sensor resistor have the same temperature coefficient of resistance TCR，TSIs the substrate temperature, TtIs the ambient temperature and alpha is the attenuation coefficient from ambient temperature to the sensor sensing temperature.
From the above formula, the auxiliary resistor RdSensor resistance R sensitive only to substrate temperature changessAffected by both the substrate temperature and the ambient temperature. The sensor resistance RsAnd an auxiliary resistor RdSubstituting the expression of (a) into the expression of the output voltage, and obtaining the response rate of the output voltage. Wherein the responsivity of the output voltage is defined as the output voltage VoAnd (3) carrying out derivation on the ambient temperature, wherein the response rate of the output voltage obtained after derivation is as follows:
from the above equation, as the substrate temperature TS increases, the absolute value of the response rate of the output voltage increases, which causes the problem that the output voltage is easily out of the dynamic range at high temperature of the detector.
In order to solve the problem that the response rate of the output voltage in the uncooled infrared focal plane array reading circuit changes along with the temperature of the substrate, the output voltage of the infrared focal plane array detector is prevented from exceeding a dynamic range at high temperature. The present specification further proposes the following technical solutions, and examples of the present specification will be described in detail below.
As shown in fig. 2, fig. 2 is a schematic diagram of a bias voltage generating device according to an exemplary embodiment shown in the present specification. By the foregoing derivation, it is essentially the response of the sensor resistor at high temperature due to too low a resistance value caused by a change in the substrate temperatureThe rate is increased, and in order to eliminate the influence of the change of the substrate temperature on the response rate, in this embodiment, the fixed bias voltage V of the sensor resistor in the column where the related prior art sensor resistor is located after being gated is setbsIs converted into a compensation voltage V related to the variation of the sensor resistance with the substrate temperaturebs(TS) The compensation voltage is a dynamic bias voltage.
Wherein the converted dynamic bias voltages at the two ends of the sensor resistor are:
Vbs(TS)＝K×(1-TCR×TS)
where K is a constant and can be selected to be a fixed voltage value.
Thus, after the fixed bias voltage of the sensor resistor is converted into the dynamic bias voltage, the obtained response rate expression of the output voltage is as follows:
from the above formula, the dynamic bias voltage compensates the variation of the resistance value of the sensor in the M × N array of the readout circuit with the substrate temperature, so that the response rate of the output voltage of the readout circuit is affected and reduced at higher substrate temperature.
Fig. 3 is a schematic diagram illustrating a bias voltage generating apparatus according to an exemplary embodiment. In this embodiment, a bias voltage generating device is designed to generate the dynamic bias voltage set forth above, where the dynamic bias voltage is used for an uncooled infrared focal plane array readout circuit, and the bias voltage generating device includes:
a sensing resistor, the resistance of which linearly changes with the change of the substrate temperature;
and the bias voltage generating module is used for generating dynamic bias voltage related to the resistance value according to preset fixed bias voltage and the resistance value of the sensing resistor so as to provide the dynamic bias voltage for two ends of the sensor resistor in the M x N array circuit and the mirror image circuit.
The embodiments of the bias voltage generating apparatus proposed in this specification can be implemented by software, or can be implemented by hardware, or by a combination of hardware and software. The software implementation is taken as an example, and as a device in the logic meaning, the current substrate temperature is obtained, a parameter reflecting the substrate temperature change is calculated, and then the dynamic bias voltage linearly changing along with the substrate temperature is calculated according to the parameter and a fixed bias voltage value preset by a system.
From a hardware aspect, the embodiments of the present disclosure provide a circuit implementation manner of a bias voltage generation device, where a resistance value of a sensing resistor in the bias voltage generation device is only affected by a substrate temperature, and the resistance value is a signal reflecting a substrate temperature change. The bias voltage generation module comprises an operational amplification circuit, and the operational amplification circuit is used for outputting dynamic voltage which linearly changes along with the resistance value of the sensing resistor according to input preset fixed bias voltage and power voltage. Usually, the device may be designed or may adopt other circuit connection modes according to the functional implementation of the hardware circuit, which is not described herein again.
In one embodiment, fig. 4 is a circuit diagram illustrating a bias voltage generating device according to an exemplary embodiment. As shown in FIG. 4, the sensing resistor is a resistor Rs1Resistance Rs1Is the same material as the sensor resistor in the M x N array circuit, and the auxiliary resistor RdSimilarly, the resistance is only affected by the substrate temperature and not affected by the ambient temperature, and the expression including the temperature coefficient TCR is:
Rs1＝Rs0×(1-TCR×TS)
wherein, TCRIs Rs1Temperature coefficient of (T)SIs the substrate temperature, Rs0The resistance of the sensing resistor R is the resistance of the sensing resistor R at the standard temperatures1Deriving the substrate temperature to obtain the sensing resistance Rs1The resistance value of the sensing resistor does not change with the ambient temperature and only decreases with the increase of the substrate temperature, namely, the resistance value of the sensing resistor is inversely related to the substrate temperature, and the resistance value of the sensing resistor linearly decreases with the increase of the substrate temperature.
In the present embodiment, the offsetThe voltage generation module comprises a first operational amplifier circuit for generating a predetermined constant bias voltage (V) according to an input voltageFID) To output a first output voltage (V) linearly varying with the resistance of the sensing resistor01). The first operational amplifier circuit further comprises two first resistors R with the same resistance valuePThe first operational amplifier circuit is specifically connected as follows: the preset fixed bias voltage VFIDThrough one of the first resistors RPThe voltage is input to the first input end of the first operational amplifier circuit, the second input end of the first operational amplifier circuit is grounded through another first resistor, the first input end of the first operational amplifier circuit is also grounded through the sensing resistor, and the output end of the first operational amplifier circuit is connected to the second input end of the first operational amplifier circuit through the sensing resistor.
Wherein the first resistor RPIs a Poly resistor in a standard CMOS process, the temperature coefficient of resistance of the Poly resistor and a sensing resistor Rs1The resistance value is regarded as a fixed value when the comparison is negligible. The first resistor may also be other than a Poly resistor according to practical applications, and this is not specifically limited in this application.
According to the specific design of the first operational amplifier circuit in the bias voltage generation module, the formula of the first output voltage can be derived as follows:
will sense the resistance Rs1Substituting an expression containing a temperature coefficient into the formula of the first output voltage, and applying the first output voltage to the substrate temperature TSDerivation, wherein the first output voltage decreases with increasing substrate temperature and is related to Rs1The magnitude of the decrease in resistance is linearly related. Thus, the present embodiment generates the bias voltage linearly dependent on the substrate temperature by the circuit structure, and it can be seen from the figure that the designed circuit structure has a simple connection manner and low implementation complexity.
In one embodiment, the bias voltage V is generated across the sensor resistor in the uncooled infrared focal plane array readout circuitbs(TS) The first output voltage V needs to be compared to linearly decrease with the increase of the substrate temperature01With a dynamic bias voltage V across the sensor resistor to be designedbs(TS) The first output voltage is linearly decreased with the increase of the substrate temperature, and the first output voltage V can be directly adjusted01And the dynamic bias voltages are respectively used as the dynamic bias voltages at two ends of the sensor resistor Rs in the M x N array circuit and the sensor resistor Rs, chip in the mirror image circuit.
In another embodiment, the dynamic bias voltage V is inputted by the gate of the first fet M4 in the mirror circuit and the gate of the corresponding first fet Mp in any column of the M x N array circuitEB(Ts) needs to increase linearly with increasing substrate temperature, with increasing magnitude and ratio and the auxiliary resistor R in the mirror circuitd,chipOr auxiliary resistor R corresponding to column in M x N array circuitdThe reduced ratio is relevant. That is, the dynamic bias voltage VEB(Ts) is added to the gate of the first fet M4 in the mirror circuit and the gate of the corresponding first fet Mp in any column of the M x N array circuit, and when the substrate temperature is high, the auxiliary resistor R in the mirror circuit is connected to the gate of the corresponding first fet Mpd,chipBut the bias voltage V increases due to the substrate temperatureEB(Ts) is also increased synchronously so that the auxiliary resistor R in the mirror circuit is increasedd,chipThe voltage difference across the terminals also maintains the synchronous correlation ratio reduced. Therefore, it is necessary to design a bias voltage generating circuit to generate a dynamic bias voltage V applied to the gate of the first fet M4 in the mirror circuit and the gate of the first fet Mp corresponding to any one column in the M × N array circuitEB(Ts) to ensure that the current of the mirror branch remains unchanged.
To obtain a dynamic bias voltage V applied to the gate of the first FET M4 in the mirror circuit and the gate of the first FET Mp corresponding to any column in the M x N array circuitEB(Ts) The bias voltage generating module comprises a first operational amplifying circuit and a differential amplifier with the amplification factor of 1, wherein the first operational amplifying circuit is used for generating a preset fixed bias voltage (V) according to an input preset fixed bias voltageEB) And the supply voltage (V) of the read-out circuitSK) To output an intermediate output voltage that varies linearly with the resistance of the sensing resistor; the two input ends of the differential amplifier respectively input the power supply voltage and the intermediate output voltage, and the output end outputs a second output voltage.
In one embodiment, as shown in fig. 5, fig. 5 is a circuit connection diagram illustrating a bias voltage generating device according to another exemplary embodiment. In this embodiment, the intermediate output voltage is obtained by the first operational amplifier circuit, wherein the first operational amplifier circuit is specifically connected as follows: the first operational amplifier circuit comprises two first resistors R with the same resistance valuePThe preset fixed bias voltage VEBThrough a first resistor RPThe power supply voltage V is input to a first input end of the first operational amplifier circuitSKThrough a first resistor RPThe output end of the first operational amplifier circuit passes through the sensing resistor Rs1A first input terminal connected to the first operational amplifier circuit, a second input terminal of the first operational amplifier circuit further connected to the sensing resistor Rs1And (4) grounding. The first input terminal or the second input terminal of the first operational amplifier circuit may be a positive input terminal or a negative input terminal of the operational amplifier circuit, and is not limited herein.
Thus, the specific expression of the intermediate output voltage is obtained as follows:
as shown in fig. 5, the specific connections of the differential amplifier are as follows: the intermediate output voltage is input to the first input terminal of the differential amplifier through a second resistor, and the power supply voltage is input to the differential amplifier through a second resistorThe output end of the differential amplifier is connected to the first input end of the differential amplifier through a second resistor, and the second input end of the differential amplifier is grounded through a second resistor. Wherein the resistance of the second resistor can be equal to that of the first resistor RPThe same or different, and is not particularly limited.
As can be seen from the above description, the second output voltage output by the output terminal of the differential amplifier is:
wherein, VSKIs the supply voltage. From the above formula, the second output voltage V is adjustedo2The second output voltage V can be found by taking the derivative of the substrate temperatureo2Increases with the increase of the substrate temperature, and increases in amplitude with the sense resistor Rs1Is correlated with the magnitude of the decrease in.
In the present embodiment, a voltage difference between the power supply voltage and the first output voltage is found by the processing of a differential amplifier. At the second output voltage Vo2After the grid of the first field effect transistor M4 arranged in the mirror image circuit and the grid of the first field effect transistor corresponding to any column in the M x N array circuit are added, the second output voltage V is obtainedo2Supply voltage V incorporating a sensing circuitSKThus eliminating the auxiliary resistor R in the mirror circuitd,chipSupply voltage V in voltage difference between two ends and two ends of auxiliary resistor Rd in M-N array circuitSKComponent to make the two voltage differences not affected by the supply voltage and obtain the auxiliary resistor R in the mirror circuitd,chipThe voltage difference between the two ends and the auxiliary resistor Rd,chipIs proportional to the resistance (i.e., substrate temperature) of the transistor, thereby ensuring that the current I flowing through the mirror circuit is proportional to the voltagemDoes not change with substrate temperature changes. Thus, it can be inferred that the dynamic bias voltage across the sensor resistor Rs in the mirror circuit, chip and M × N array circuit is Vbs(TS)＝Im×Rs,chipFromAt Rs,chipAnd also only linearly changes with the change of the substrate temperature, so the requirements are satisfied.
Therefore, the second output voltage can be used as the dynamic bias voltage to control the voltage difference between the auxiliary resistor Rd in the M × N array circuit and the auxiliary resistor Rd, chip in the mirror circuit to change linearly with the temperature change of the substrate.
In this specification, a bias voltage generating device is designed for the problem, and based on the bias voltage generating device, a non-refrigeration infrared focal plane array readout circuit is also designed, which is modified accordingly, the readout circuit includes an M × N array circuit for forming an infrared focal plane array and a mirror circuit for mirror symmetry with pixels at intersections of rows and columns in the M × N array circuit, and the readout circuit further includes: bias voltage generating means for providing dynamic bias voltages to said pixels and said mirror circuits in said M x N array circuit, respectively, said bias voltage generating means comprising:
a sensing resistor, the resistance of which linearly changes with the temperature of the substrate on the readout circuit;
and the bias voltage generating module is used for generating dynamic bias voltage related to the resistance value according to preset fixed bias voltage and the resistance value of the sensing resistor so as to provide the dynamic bias voltage for two ends of the sensor resistor in the M x N array circuit and the mirror image circuit.
In one embodiment, the dynamic bias voltage is used as the gate input voltage of the first field effect transistor (M4) and the first field effect transistor (Mp), respectively, or the dynamic bias voltage is used as the gate input voltage of the second field effect transistor (M3) and the second field effect transistor (Mn), respectively. Here, that is, as in the connection method of the related art, the dynamic bias voltage is directly input to the gates of the first field effect transistor (M4) and the first field effect transistor (Mp) which are symmetrical, or is input to the gates of the second field effect transistor (M3) and the second field effect transistor (Mn) which are symmetrical.
In one embodiment, the readout circuit further includes a first voltage stabilizing circuit and a second voltage stabilizing circuit, the input ends of the first voltage stabilizing circuit and the second voltage stabilizing circuit both input the dynamic bias voltage, the output end of the first voltage stabilizing circuit is connected to the mirror image circuit and is used for providing the voltage-stabilized dynamic bias voltage to the mirror image circuit, and the output end of the second voltage stabilizing circuit is connected to the M × N array circuit and is used for providing the voltage-stabilized dynamic bias voltage to the M × N array circuit. The two designed voltage stabilizing circuits are respectively connected with the mirror image circuit and the M x N array circuit, and respectively provide the dynamic bias voltage after voltage stabilization for the mirror image circuit and the M x N array circuit, so that the situation that the dynamic bias voltage changes too fast to cause larger fluctuation of sensed signals is prevented.
In one embodiment, the bias voltage generation module includes a first operational amplifier circuit configured to generate a predetermined fixed bias voltage V according to an input signalFIDTo output a first output voltage V linearly varying with the resistance of the sensing resistor01And sending the first output voltage serving as the dynamic bias voltage to the input ends of the two voltage stabilizing circuits. The specific connection of the first operational amplifier circuit is clearly described in the foregoing embodiments, and reference may be made to fig. 4 for details, which are not described herein again.
In one embodiment, as shown in fig. 6, fig. 6 is a circuit diagram of an uncooled infrared focal plane array readout circuit according to an exemplary embodiment. As can be seen from fig. 6, the readout circuit in this embodiment is a significant improvement over the readout circuit in the related art. In this embodiment, the mirror circuit and the M × N array circuit have been clearly described in the foregoing description of fig. 1, and are not repeated herein.
In this embodiment, the first voltage stabilizing circuit includes a first operational amplifier feedback circuit, and the second voltage stabilizing circuit includes a second operational amplifier feedback circuit; taking the first output voltage as the dynamic bias voltage, the mirror circuit comprising a first field effect transistor (M4) and a second field effect transistor (M3); any column of circuits in the M x N array circuit comprises a first field effect transistor (Mp) and a second field effect transistor (Mn); the first operational amplifier feedback circuit and the first operational amplifier feedback circuit of the second operational amplifier feedback circuitThe input ends of the first operational amplifier circuit are connected with the output end of the first operational amplifier circuit and receive the first output voltage Vo1(ii) a The second input end of the first operational amplifier feedback circuit is connected to the source electrode of the second field effect transistor (M3), the second input end of the second operational amplifier feedback circuit is connected to the source electrode of the second field effect transistor (Mn), the output end of the first operational amplifier feedback circuit is connected to the grid electrode of the second field effect transistor (M3), and the output end of the second operational amplifier feedback circuit is connected to the grid electrode of the second field effect transistor (Mn); the gate of the first field effect transistor (M4) is directly connected with the gate of the first field effect transistor (Mp).
Thus, the sensor resistance R in the mirror circuits,chipAnd the dynamic bias voltage at two ends of the sensor resistor Rs in the M x N array circuit is as follows:
that is, the first output voltage is used as the dynamic bias voltage, so that the dynamic bias voltage across the auxiliary resistor Rd in the M × N array circuit can be calculated by calculating the current flowing in the mirror circuit as follows:
due to Rd,chipAnd Rs,chipHave the same temperature coefficient and are only related to the substrate temperature, so that R can be controlledd,chip/Rs,chipIs a constant R independent of temperatureKAs can be seen from the above derived expression of the output voltage of the readout circuit, the expression of the output voltage of the readout circuit after converting the fixed bias voltage into the dynamic bias voltage is:
the above-mentioned R is reacted withd、Rs1、RsIs substituted into the output voltage V0' thereafter, the voltage V will be output0' to ambient temperature TtAnd (3) carrying out derivation, wherein the derivation result is as follows:
it follows that the responsivity of the output voltage is related to the substrate temperature TSIs irrelevant, thereby avoiding the temperature T of the substrateSWhen the output voltage of the detector is increased, the output voltage of the detector is easy to exceed the dynamic range at high temperature.
In another embodiment, the bias voltage generation module includes a first operational amplifier circuit and a differential amplifier with an amplification factor of 1, wherein the first operational amplifier circuit is configured to output a predetermined fixed bias voltage V according to an input signalEBAnd the supply voltage V of the read-out circuitSKTo output an intermediate output voltage that varies linearly with the resistance of the sensing resistor; the two input ends of the differential amplifier respectively input the power supply voltage and the intermediate output voltage, and the output end outputs a second output voltage Vo2The second output voltage V is adjustedo2And the dynamic bias voltage is used as the dynamic bias voltage and sent to the input ends of the two voltage stabilizing circuits.
The specific circuit structures of the first operational amplifier circuit and the differential amplifier for obtaining the intermediate output voltage are already described in the foregoing embodiments, and are not described herein again.
In one embodiment, as shown in fig. 7, fig. 7 is a circuit diagram of another uncooled infrared focal plane array readout circuit according to an exemplary embodiment. As can be seen from fig. 7, in this embodiment, the first voltage stabilizing circuit includes a first operational amplifier feedback circuit, and the second voltage stabilizing circuit includes a second operational amplifier feedback circuit, and the second output voltage is used as a dynamic bias voltage; the mirror circuit comprises a first field effect transistor (M4) and a second field effect transistor (M3); any column circuit in the M x N array circuit comprises a first field effect transistor (Mp) and a second field effect transistor (Mn); first input ends of the first operational amplifier feedback circuit and the second operational amplifier feedback circuit are connected with the output end of the differential amplifier, and receive the second output voltage; the second input end of the first operational amplifier feedback circuit is connected to the source electrode of the first field effect transistor (M4), the second input end of the second operational amplifier feedback circuit is connected to the source electrode of the first field effect transistor (Mp), the output end of the first operational amplifier feedback circuit is connected to the grid electrode of the first field effect transistor (M4), and the output end of the second operational amplifier feedback circuit is connected to the grid electrode of the first field effect transistor (Mp); the grid electrode of the second field effect transistor (M3) is directly connected with the grid electrode of the second field effect transistor (Mn).
Thus, the second output voltage V is adjustedo2As the output of the bias voltage generating device, the source potential of the first field effect transistor (M4) in the mirror image circuit and the source potential of the first field effect transistor (Mp) in the M x N array circuit are stabilized to a second output voltage V by a voltage stabilizing circuito2Thus, the dynamic bias voltages across the auxiliary resistors Rd, chip in the mirror circuit and across the auxiliary resistors Rd in the M × N array circuit are:
it follows that the second output voltage Vo2OfSKWhich exactly cancels the supply voltage in the sensing circuit, so that the dynamic bias voltage across the auxiliary resistor Rd, chip in the mirror circuit is linearly related to the substrate temperature. Calculating the dynamic bias voltage at two ends of the sensor resistor Rs in the M x N array circuit by calculating the current flowing in the mirror image circuit as follows:
also, said Rs,chip/Rd,chipIs a constant 1/R independent of temperatureKAs can be seen from the above derived expression of the output voltage of the readout circuit, in this case, the expression of the output voltage of the readout circuit after converting the fixed bias voltage into the dynamic bias voltage is:
the above-mentioned R is reacted withd、Rs1、RsIs substituted into the output voltage V0"then, the voltage V will be output0"to ambient temperature TtAnd (3) carrying out derivation, wherein the derivation result is as follows:
it can be seen that, in this case, the responsivity of the output voltage is also the same as the substrate temperature TSIs irrelevant, thereby avoiding the temperature T of the substrateSWhen the output voltage is increased, the output voltage of the detector is easy to exceed the dynamic range at high temperature, so that the change rate of the output voltage of the detector is kept stable at high temperature, and the output voltage can be kept within the output dynamic range.
In one embodiment, the M × N array circuits are divided into a plurality of groups according to the number of columns, each group corresponds to one of the bias voltage generating devices, and each of the bias voltage generating devices provides the dynamic bias voltage for the plurality of column circuits in the corresponding group. That is, each group includes a plurality of rows, and each group corresponds to one bias voltage generating device and a corresponding voltage stabilizing circuit. The specific circuit configurations and connection relationships of the bias voltage generating device and the voltage stabilizing circuit can be referred to the description of the previous embodiments. To illustrate, if there are 24 rows in the 24 x 50 array circuit, each row has 50 sensor resistors RsAuxiliary resistor RdThe 24 columns are divided into 6 groups by the first field effect Mp and the second field effect Mn, each group includes 4 columns, and 4 columns in the same group share one bias voltage generating device and a corresponding voltage stabilizing circuit. The 24 × 50 array circuit has 6 bias voltage generating devices and 6 corresponding voltage stabilizing circuits, so that partial circuits in the M × N array circuit can be locally controlled.
In the embodiments of the present specification, a bias voltage generating device for generating a dynamic bias voltage linearly varying with a substrate temperature is devised; then, the uncooled infrared focal plane array reading circuit is improved, and the obtained dynamic bias voltage is added to two ends of an auxiliary resistor (dummy resistor) and/or a sensor resistor in the reading circuit. Compared with the prior art (adding a fixed bias voltage at two ends of the dummy resistor and the sensor resistor), the change of the response rate of the output voltage of the reading circuit caused by the temperature change of the substrate is effectively eliminated, and the problem that the output voltage of the infrared focal plane array detector exceeds the dynamic range at high temperature is further avoided. The auxiliary resistor and the sensor resistor are made of the same sensitive material so as to offset the bias current of the sensor resistor and eliminate the change of the output voltage of the reading circuit caused by the temperature change of the substrate.
The above-described embodiments of the apparatus are merely illustrative, wherein the modules described as separate parts may or may not be physically separate, and the parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution in the specification. One of ordinary skill in the art can understand and implement it without inventive effort.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.
It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
The above description is only a preferred embodiment of the present disclosure, and should not be taken as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. An uncooled infrared focal plane array readout circuit, the readout circuit comprising an M x N array circuit for forming an infrared focal plane array and a mirror circuit for mirror symmetry with pixels at intersections of rows and columns in the M x N array circuit, the readout circuit further comprising: bias voltage generating means for providing dynamic bias voltages to said picture elements and said mirror circuits in the M x N array circuit, respectively, said bias voltage generating means comprising:
a sensing resistor, the resistance of which linearly changes with the temperature of the substrate on the readout circuit;
and the bias voltage generating module is used for generating dynamic bias voltage related to the resistance value according to preset fixed bias voltage and the resistance value of the sensing resistor so as to provide the dynamic bias voltage for the pixel in the M x N array circuit and two ends of the sensor resistor in the mirror image circuit.
2. The uncooled infrared focal plane array readout circuit of claim 1, wherein the M x N array circuits are divided into a plurality of groups according to the number of columns, each group corresponding to one of the bias voltage generating devices, each of the bias voltage generating devices providing the dynamic bias voltage to the plurality of column circuits in the corresponding group.
3. The uncooled infrared focal plane array readout circuit of claim 1, wherein the sensing resistor has the same temperature coefficient of resistance as the sensor resistor in the readout circuit, and the resistance of the sensing resistor decreases linearly with increasing temperature of the substrate.
4. The uncooled infrared focal plane array reading circuit according to claim 1, wherein the mirror circuit includes a first fet (M4) and a second fet (M3) connected in sequence, and each column of the M x N array circuit includes a first fet (Mp) and a second fet (Mn) connected in sequence; the dynamic bias voltages are respectively used as the first field effect transistors (M)4) And a first field effect transistor (M)p) As the second field effect transistor (M), or the dynamic bias voltage, respectively3) And a second field effect transistor (M)n) The gate of (1) inputs the voltage.
5. The uncooled infrared focal plane array readout circuit of claim 1, further comprising a first voltage stabilizing circuit and a second voltage stabilizing circuit, wherein the input terminals of the first voltage stabilizing circuit and the second voltage stabilizing circuit are both inputted with the dynamic bias voltage, the output terminal of the first voltage stabilizing circuit is connected to the mirror image circuit for providing the mirror image circuit with the stabilized dynamic bias voltage, and the output terminal of the second voltage stabilizing circuit is connected to the M x N array circuit for providing the M x N array circuit with the stabilized dynamic bias voltage.
6. The uncooled infrared focal plane array readout circuit of claim 5, wherein the bias voltage generation module comprises a first operational amplifier circuit, and the first operational amplifier circuit is configured to output a first output voltage varying with the resistance of the sensing resistor according to an input preset fixed bias voltage.
7. The uncooled infrared focal plane array reading circuit of claim 6, wherein the first operational amplifier circuit comprises two first resistors with the same resistance, the predetermined fixed bias voltage is inputted to the first input terminal of the first operational amplifier circuit through one of the first resistors, the second input terminal of the first operational amplifier circuit is grounded through the other first resistor, the first input terminal of the first operational amplifier circuit is grounded through the sensing resistor, and the output terminal of the first operational amplifier circuit is connected to the second input terminal of the first operational amplifier circuit through the sensing resistor.
8. The uncooled infrared focal plane array reading circuit according to claim 6, wherein the mirror circuit includes a first fet (M4) and a second fet (M3) connected in sequence, and each column of the M x N array circuit includes a first fet (Mp) and a second fet (Mn) connected in sequence; the first voltage stabilizing circuit comprises a first operational amplifier feedback circuit, the second voltage stabilizing circuit comprises a second operational amplifier feedback circuit, and the first output voltage is used as the dynamic bias voltage and is respectively input to the first input ends of the first operational amplifier feedback circuit and the second operational amplifier feedback circuit; a second input end of the first operational amplifier feedback circuit is connected to the source electrode of the second field effect transistor (M3), and a second input end of the second operational amplifier feedback circuit is connected to the source electrode of the second field effect transistor (Mn); the output end of the first operational amplifier feedback circuit is connected to the grid electrode of the second field effect transistor (M3), and the output end of the second operational amplifier feedback circuit is connected to the grid electrode of the second field effect transistor (Mn).
9. The uncooled infrared focal plane array reading circuit of claim 5, wherein the bias voltage generating module includes a first operational amplifier circuit and a differential amplifier with an amplification factor of 1, the first operational amplifier circuit is configured to output an intermediate output voltage varying with the resistance of the sensing resistor according to an input preset fixed bias voltage and a power supply voltage of the reading circuit; the two input ends of the differential amplifier respectively input the power supply voltage of the readout circuit and the intermediate output voltage, and the output end outputs a second output voltage.
10. The uncooled infrared focal plane array reading circuit of claim 9, wherein the mirror circuit includes a first fet (M4) and a second fet (M3) connected in sequence, and each column of the M x N array circuit includes a first fet (Mp) and a second fet (Mn) connected in sequence; the first voltage stabilizing circuit comprises a first operational amplifier feedback circuit, the second voltage stabilizing circuit comprises a second operational amplifier feedback circuit, and the second output voltage is used as dynamic bias voltage and is respectively input to the first input ends of the first operational amplifier feedback circuit and the second operational amplifier feedback circuit; the second input end of the first operational amplifier feedback circuit is connected to the source electrode of the first field effect transistor (M4), and the second input end of the second operational amplifier feedback circuit is connected to the source electrode of the first field effect transistor (Mp); the output end of the first operational amplifier feedback circuit is connected to the grid electrode of the first field effect transistor (M4), and the output end of the second operational amplifier feedback circuit is connected to the grid electrode of the first field effect transistor (Mp).
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