CN111816623A - Packaged semiconductor device and packaging method thereof - Google Patents

Packaged semiconductor device and packaging method thereof Download PDF

Info

Publication number
CN111816623A
CN111816623A CN202010395716.1A CN202010395716A CN111816623A CN 111816623 A CN111816623 A CN 111816623A CN 202010395716 A CN202010395716 A CN 202010395716A CN 111816623 A CN111816623 A CN 111816623A
Authority
CN
China
Prior art keywords
thermally conductive
metal
power device
electrically insulating
semiconductor power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010395716.1A
Other languages
Chinese (zh)
Inventor
李湛明
傅玥
刘雁飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Quantum Semiconductor Co Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/871,026 external-priority patent/US11107755B2/en
Application filed by Individual filed Critical Individual
Publication of CN111816623A publication Critical patent/CN111816623A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The embodiment of the invention provides a packaged semiconductor device and a packaging method thereof. A packaged semiconductor device, comprising: a lateral semiconductor power device chip including an upper surface including at least two electrodes and a lower surface, wherein the upper and lower surfaces are coplanar; at least one metal lead electrically connected to a first of the at least two electrodes; a back plate; an electrically insulating, thermally conductive adhesive distributed between the lower surface of the lateral semiconductor power device chip and the backplane; wherein at least a portion of the metal of the backplate is electrically connected to a second of the at least two electrodes. The transverse high-voltage gallium nitride device provided by the embodiment of the invention can realize electrical isolation while keeping heat dissipation. The electrical isolation reduces or eliminates vertical leakage current and improves high voltage performance. The packaging technology can use or be compatible with standard formats such as JEDEC, thereby reducing the packaging cost and facilitating the realization of device packaging by using a traditional circuit design method.

Description

Packaged semiconductor device and packaging method thereof
Cross Reference to Related Applications
The present invention relates to the following related applications: 62/846,667, filed on 12.5.2019 and 16871026, filed on 10.5.2020, the contents of which are incorporated herein by reference in their entirety.
Technical Field
The invention relates to packaging of lateral power electronic devices. More particularly, the present invention relates to packaging of lateral power electronic devices that reduces or eliminates vertical leakage current.
Background
Gallium nitride (GaN) power electronic devices have excellent characteristics such as high efficiency, high power density, and the like, and are expected to replace silicon and silicon carbide (SiC) as main power devices. Growing GaN on silicon substrates (GaN/Si) is a very promising technology with the advantage of low cost and high performance.
However, gan power devices using silicon substrates face limitations in implementation, on one hand because the silicon substrate is p-negatively doped and cannot withstand high voltages, especially in the vertical direction (i.e., perpendicular to the plane of the device chip), and when the voltage is high (e.g., greater than 1000V), substrate leakage is significant.
Another limitation is that silicon-substrate gallium nitride power devices are lateral devices in which electrodes (e.g., gate, drain, source of a Field Effect Transistor (FET)) are disposed on the same side (e.g., top) of the device, with current flowing laterally through the device between the electrodes. Therefore, the conventional packaging scheme commonly used for vertical devices cannot be used, i.e. electrodes are arranged on opposite sides (e.g. top and bottom) of the device and current flows through the device in a vertical manner.
Disclosure of Invention
The present disclosure provides a lateral high voltage gallium nitride device and a method for packaging the same to solve the disadvantages of the related art.
One aspect of the present invention provides a packaged semiconductor device, the device comprising: a lateral semiconductor power device chip, which is composed of an upper surface and a lower surface, wherein the upper surface at least comprises two electrodes, and the upper surface and the lower surface are coplanar; at least one metal lead electrically connected to a first one of the upper surface electrodes; a back plate; and an electrically insulating and thermally conductive adhesive distributed between the lower surface of the lateral semiconductor power device chip and the backplane; wherein the back plate comprises a portion of metal electrically connected to the second electrode of the top surface electrode.
Another aspect of the invention relates to a method of packaging a lateral semiconductor power device chip comprised of an upper surface containing at least two electrodes and a lower surface, the upper and lower surfaces being coplanar, said method comprising: electrically connecting a first electrode of the upper surface to a first metal lead of the device package; disposing an electrically insulating and thermally conductive adhesive between a lower surface of the lateral semiconductor power device chip and a backplane of the device package; wherein the back plate comprises a portion of metal electrically connected to the second electrode on the upper surface.
In one embodiment, the backplane includes only a metal portion and is located beneath the lateral semiconductor power device chip; with an electrically insulating and thermally conductive adhesive disposed between the lateral semiconductor power device chip and the backplane.
In an embodiment, the backplate comprises a metal portion and an electrically insulating and thermally conductive portion disposed on the metal portion; wherein the lateral semiconductor power device chip is arranged over the electrically insulating and thermally conducting portion of the backplate; an electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conductive portion of the backplane.
In an embodiment, the electrically insulating and thermally conducting portion of the back plate has an area greater than or equal to the area of the lateral semiconductor power device chip.
In an embodiment, the back plate comprises a metal portion and an electrically insulating and thermally conducting portion arranged in the vicinity of the metal portion; wherein the lateral semiconductor power device chip is disposed on the electrically insulating and thermally conductive portion of the backplate; an electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conductive portion of the backplane.
In an embodiment, the electrically insulating and thermally conductive portion of the backplate has an area greater than or equal to the area of the lateral semiconductor power device chip, and the thickness can extend to the bottom of the packaged semiconductor device.
In one embodiment, the electrical connection between the first and second electrodes, the metal lead and the metal portion of the back plate is achieved by bonding wires.
In one embodiment, a Field Effect Transistor (FET) is a lateral semiconductor power device chip; wherein the first electrode is a gate electrode electrically connected to the first metal lead; the second electrode is a source electrode electrically connected to the metal portion of the back plate; the third electrode is a drain electrode electrically connected to the second metal wire.
In one embodiment, a Field Effect Transistor (FET) is a lateral semiconductor power device chip; wherein the first electrode is a gate electrode electrically connected to the first metal lead; the second electrode is a drain electrode and is electrically connected to the metal part of the back plate; the third electrode is a source electrode and is electrically connected to the second metal lead.
In one embodiment, a lateral semiconductor power device chip includes at least one of: GaN, GaN/Si, or GaN/ceramic.
In one embodiment, the plurality of packages are each compliant with JEDEC standard format.
Another aspect of the invention relates to a packaged semiconductor power device comprising: a lateral conduction type GaN semiconductor chip grown on the silicon; electrically insulating and thermally conductive adhesive for adhering the semiconductor chip to a backing plate, the backing plate being metal; the source electrode of the semiconductor chip is connected to the metal back plate through a bonding wire, and the grid electrode and the drain electrode of the semiconductor chip are connected to the corresponding metal leads through the bonding wire. In one embodiment, the drain is connected to the metal backplane by wire bonds, and the gate and the source are connected to respective metal leads by wire bonds.
Another aspect of the invention relates to a packaged semiconductor power device comprising:
a lateral conduction type GaN semiconductor chip grown on the silicon;
an electrically insulating and thermally conductive adhesive adhering the semiconductor chip to the back plate encapsulating the semiconductor device;
the top of the back plate below the semiconductor chip is composed of an electric insulation and heat conduction material, and the occupied area of the back plate is larger than or equal to the area of the semiconductor chip; the bottom of the back plate comprises metal;
the source electrode of the semiconductor chip is connected with the metal back plate through a bonding wire, and the grid electrode and the drain electrode of the semiconductor chip are connected with corresponding metal leads through bonding wires.
In one embodiment, the drain electrode is connected with the metal back plate through bonding wires, and the gate electrode and the source electrode are connected with the corresponding metal leads through the bonding wires.
Another aspect of the invention relates to a packaged semiconductor power device comprising: a lateral conduction type GaN semiconductor chip grown on the silicon; an electrically insulating and thermally conductive adhesive adhering the semiconductor chip to the back plate of the packaged semiconductor device; wherein a portion of the backplane is below the semiconductor chip, comprises an electrically insulating and thermally conductive material, has an area greater than or equal to an area occupied by the semiconductor chip, and has a thickness extending to a bottom of the device package; the side of the back plate comprises metal; the semiconductor chip is connected with the metal back plate through a bonding wire, and the grid and the drain of the semiconductor chip are connected with the corresponding metal leads through the bonding wires. In one embodiment, the drain electrode is connected with the metal back plate through bonding wires, and the gate electrode and the source electrode are connected with the corresponding metal leads through the bonding wires.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
it can be known from the above embodiments that the lateral high voltage gan device provided by the embodiments of the present invention can achieve electrical isolation while maintaining heat dissipation. The electrical isolation reduces or eliminates vertical leakage current and improves high voltage performance. The packaging technology can use or be compatible with standard formats such as JEDEC, thereby reducing the packaging cost and facilitating the realization of device packaging by using a traditional circuit design method.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1A is a side and top view of a prior art packaged discrete silicon or silicon carbide power FET device.
Fig. 1B is a top view of a prior art packaged discrete silicon or silicon carbide power FET device.
Fig. 2 is a side view of a packaged discrete GaN power FET device according to the prior art.
Fig. 3 is a structural side view of a silicon substrate GaN/Si device with top layer GaN packaged according to the prior art.
Fig. 4 is a side view of an example of a GaN chip package implemented according to the method of the present invention.
Fig. 5 is a side view of another example of a GaN chip package implemented according to the method of the present invention.
Fig. 6 is a side view of another example of a GaN chip package implemented according to the method of the present invention.
Fig. 7 is a side view of another example of a GaN chip package implemented according to the method of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure as recited in the claims below.
The present invention describes a package structure and related methods for lateral power electronic devices, implemented based on, but not limited to, GaN/GaN, GaN/Si, and GaN/ceramic technologies. Examples of power devices include, but are not limited to, transistors (e.g., field effect transistors, FETs), and diodes. The present embodiments overcome the limitations of packaging such devices using prior art techniques.
Fig. 1A and 1B show side and top views, respectively, of discrete silicon and silicon carbide power device structures packaged using prior art techniques. The semiconductor chip is a vertical device, i.e., the electrodes are arranged on opposite planes (i.e., the gate G and source S are arranged on the top surface and the drain is arranged on the bottom surface, based on the direction shown in fig. 1A), and the current flows vertically with respect to the plane of the chip. Many Device packaging formats (e.g., TO220, TO252, TO263 in JEDEC (Joint Electron Device Engineering Council) standards) are based on this arrangement mode. The semiconductor chip 103 shown in fig. 1A and 1B is adhered to a packaged metal backplate 106 with a conductive adhesive 101. Therefore, when the semiconductor chip 103 is adhered to the back plate 106, the back plate becomes a drain. The source and gate electrodes are connected to metal leads 102a and 102b, respectively, by bonding wires 105a and 105b (the offset is shown in fig. 1A for clarity). Some packaging patterns may provide metal leads 108 connected to the metal backplane 106. When used in an external circuit, the package may be soldered to a circuit board through the metal back plate 106 and the metal leads 102a, 102 b. The metal leads 108 (if any) may also be connected to the circuit board and may be selectively connected to one device electrode, depending on the circuit design, or may be removed. The encapsulated device is covered with a molded polymer encapsulant 104, which polymer encapsulant 104 provides access to the metal contacts.
Fig. 2 shows a GaN/Si chip 203 packaged using prior art techniques. In this method, the conductive adhesive 201 connects the GaN/Si chip 203 to a package metal frame, a frame commonly used in the JEDEC standard, using the method in fig. 1A and 1B. However, since the GaN/Si chip is a lateral device, source S is located on the top surface of device 203 and is connected to backplate 206 using wire bonds 205 c. Drain D and gate G electrodes are also located on the top surface of the device and are connected to metal leads 202a and 202b by bonding wires 205a and 205b, respectively (the offset is shown in fig. 2 for clarity). Some package modes may provide metal leads 208 connected to the metal backplane 206. The encapsulated device is covered with a molded polymer encapsulant 204, which polymer encapsulant 204 provides access to the metal contacts.
The approach shown in fig. 2 has at least two limitations. First, this approach allows current to flow vertically through the device (i.e., current flow perpendicular to the device die plane), which is undesirable for lateral devices, and at high power, high voltage (e.g., 1000V and higher), the problem is exacerbated where there is significant substrate leakage of vertical current. Another limitation is that the designation of the backplane 206 as the source electrode makes many JEDEC standard based package frames (e.g., TO263-7) incompatible because these JEDEC standard frames are designed with drains connected TO the backplane.
The vertical leakage current can be explained by considering the structure of the GaN/Si semiconductor device. As illustrated in FIG. 3, the device 300 has a thickness in the range of 200-400 μm and includes a two-dimensional electron gas (2DEG) structure 301 based on a GaN/AlGaN layer arranged on a silicon substrate 302. A buffer material 304 is interposed between the silicon substrate 302 and the metal backplate 306. The source S, gate G and drain D are arranged on the top surface of the chip. The electric field within the silicon substrate 302 is primarily a vertical field due to the large difference between the lateral electrode spacing and the substrate thickness. Such vertical fields exacerbate undesirable vertical substrate leakage. This approach is not suitable for high power lateral devices because the original approach of using a conductive adhesive 201 (as shown in fig. 2) does not prevent vertical leakage currents and may exacerbate vertical leakage currents, resulting in a device structure with a significantly limited breakdown voltage.
In the description of the subsequent embodiments, a FET will be exemplified as a lateral GaN power device, in which electrodes (gate, drain and source) are distributed on the top surface of the device. Similarly, other lateral GaN power devices, such as diodes, may be used, where the electrodes (anode and cathode) are also distributed on the top surface of the device.
Fig. 4 shows another embodiment of the present invention, in which the package structure in fig. 4 is a GaN device chip 403, including: using an electrically insulating and thermally conductive adhesive 401 (e.g.,
Figure BDA0002487493670000071
AblestikTM84-3J Henkel Canada corporation, Missippi, ON or SUMIRESIN
Figure BDA0002487493670000072
CRM-1100 series Sumitomo bakelite co) adheres GaN grown on a silicon substrate (i.e., GaN/Si) to the backplate 406. In this embodiment, the back plate is made entirely of metal. The source S of device 403 is connected to the metal backplate 406 by wire bond 405 c. The drain D and gate G of the device 403 are connected to the metal leads 402a and 402b of the package with bonding wires 405a and 405b, respectively (the offset is shown in fig. 4 for clarity). Metal leads 408 for connection to the metal backplane 406 may be included in the package mode of some embodiments. When used in an external circuit, a package mode may be employed in which the package is soldered to a circuit board through the metal backplane 406 and the metal leads 402a, 402 b. The metal leads 408 (if any) may be attached to the circuit board and wire bonded to an electrode of the device or removed as required by the circuit design. The encapsulated device is covered with a molded polymer encapsulant 404, which polymer encapsulant 404 provides access to the metal contacts. The electrically insulating and thermally conductive adhesive 401 absorbs at least a portion of the voltage drop from the power device substrate, thereby preventing, limiting, or substantially reducingThe substrate leaks current vertically.
In another embodiment, shown in FIG. 5, the package structure is substantially the same as the embodiment of FIG. 4, wherein the GaN device die 503 is formed from GaN on a silicon substrate using an electrically insulating and thermally conductive adhesive 501 (e.g., Ablestik)TM84-3J or SUMIRESIN
Figure BDA0002487493670000073
CRM-1100 series) is adhered to the metal backsheet 506. However, in this embodiment, the drain D of the device 503 is connected to the backplate 506 by a bonding wire 505 c. The source S and gate G of the device are connected to metal leads 502a and 502b by bonding wires 505a and 505b, respectively. Some embodiments may include a package mode connected to the metal backplane 506 by metal leads 508. In different embodiments, the gate metal lead 502b may be selectively electrically connected to the drain metal lead 502a or the backplate 506, or the metal lead 508 (if any), depending on different device configurations. The encapsulated device is covered with a molded polymer encapsulant 504, which polymer encapsulant 504 provides access to the metal contacts. In this embodiment, in addition TO preventing, limiting or significantly reducing substrate vertical leakage current, another advantage is that the configuration of the drain at the bottom of the structure allows the use of a standard JEDEC framework, such as TO263-7, which reduces packaging costs and makes the structure easier for the user TO use, as it facilitates implementation of traditional circuit design methods.
Another embodiment is shown in fig. 6. In this case, the backplane is comprised of a metal portion 606a and an electrically insulating thermally conductive material 606 b. In this embodiment, the GaN device chip 603 is composed of: using an electrically insulating and thermally conductive adhesive 601 (e.g., Ablestik)TM84-3J or SUMIRESIN
Figure BDA0002487493670000082
CRM-1100 series) to adhere a silicon substrate GaN to an electrically insulating and thermally conductive material 606 b. Material 606b may be a ceramic material, such as aluminum nitride (AlN), which has high thermal conductivity and is an electrical insulator. The thickness of material 606b may be close to or less than the thickness of chip 603, e.g., at least 100 μm thick. Ceramic material 606b are disposed over the metal portion 606a of the backplate and may be secured using an electrically insulating and thermally conductive adhesive as described above. In this embodiment, the drain D or the source S of the device 603 is connected to the metal backplate 606a by a bonding wire 605c, and the other of the source S or the drain D and the gate G of the device are connected to the metal leads 602a and 602b by bonding wires 605a and 605b, respectively. Some embodiments may include a package pattern having metal leads 608 connected to the backplane metal portion 606 a. In various embodiments, the gate metal lead 602b may be selectively electrically connected to the metal backplate 606a, the metal lead 602a, or the metal lead 608 (if any), depending on the particular device configuration. As shown in fig. 6, material 606b is located under the semiconductor chip and has an area greater than or equal to the area occupied by the semiconductor chip. The lower portion of the backplate 606a is metal, so that maximum electrical and thermal conduction through the backplate can be achieved, enabling it to be mounted on a circuit board, such as a Printed Circuit Board (PCB). The encapsulated device is covered with a molded polymer encapsulant 604 that provides access to the metal contacts. The partial ceramic structure of this embodiment is suitable for larger package models, such as JEDEC to 263-7. An advantage of this configuration is that the insulating material 606b can provide additional high voltage blocking, which can further reduce or eliminate substrate vertical leakage current.
Another embodiment is shown in fig. 7. In this embodiment, the backplane comprises a metal portion 706a and an electrically insulating and thermally conductive material 706 b. The GaN device core 703 includes: using an electrically insulating and thermally conductive adhesive 701 (e.g., Ablestik)TM84-3J or SUMIRESIN
Figure BDA0002487493670000081
CRM-1100 series) to adhere a silicon substrate GaN to an electrically insulating and thermally conductive material 706 b. Material 706b may be a ceramic material such as AlN. Unlike the embodiment of fig. 6, material 706b in this embodiment has a thickness that extends all the way to the bottom of the package so that it can contact a circuit board (e.g., PCB) on which the entire packaged device is mounted. Material 706b is located under the semiconductor chip and may have an area greater than or equal to the area occupied by semiconductor chip 703. This embodiment includes a metal portion of the backplate 706a, the goldThe metal portions are distributed about material 706b and may be adhered to material 706b using an electrically insulating and thermally conductive adhesive as described above. The metal back plate 706a provides electrical connection to the printed circuit board PCB to which the packaged device is mounted via the drain D or source S. The drain or source of device 703 is a metal portion connected to backplane 706a with bond wire 705 c. The other of the source or drain and the gate are connected to metal leads 702a and 702b by bonding wires 705a, 705b, respectively. Some embodiments may include a package mode with metal leads 708, and the metal leads 708 may be connected to the metal portion 606a of the backplane, or may be floating. In the latter case, the metal lead 708 may be connected to a selected one of the electrodes using a wire bond, depending on the particular device configuration. In various embodiments, the gate metal lead 702b may be selectively electrically connected to the metal lead 702a or the backplane 706a, depending on the particular device configuration. The packaged device is covered with a molded polymer encapsulant 704 that provides access to the metal contacts. This embodiment is suitable for smaller package models, such as lead frame based packages (quad flat no lead (QFN), Chip Scale Package (CSP)), where the insulating material 708 may serve as a creepage distance interval. An advantage of this package is that the insulating material 706b can provide additional high voltage blocking, further reducing or eliminating substrate vertical leakage current.
The above-mentioned embodiments are only for illustrating the technical ideas and features of the present invention, and the purpose of the present invention is to enable one skilled in the art to understand the contents of the present invention and to implement the same, and the scope of the present invention is not limited to the above-mentioned embodiments, i.e. all equivalent changes or modifications made in the spirit of the present invention are covered by the protection scope of the present invention.

Claims (22)

1. A packaged semiconductor device, comprising:
a lateral semiconductor power device chip including an upper surface including at least two electrodes and a lower surface, wherein the upper and lower surfaces are coplanar;
at least one metal lead electrically connected to a first of the at least two electrodes;
a back plate;
an electrically insulating, thermally conductive adhesive distributed between the lower surface of the lateral semiconductor power device chip and the backplane;
wherein at least a portion of the metal of the backplate is electrically connected to a second of the at least two electrodes.
2. The packaged semiconductor device of claim 1,
the back plate only comprises a metal part and is positioned below the transverse semiconductor power device chip;
the electrically insulating thermally conductive adhesive is distributed between the lateral semiconductor power device chip and the backplane.
3. The packaged semiconductor device of claim 2,
the backplate comprises a metal portion and an electrically insulating and thermally conductive portion disposed on the metal portion;
wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conductive portion of the backplate;
wherein an electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conductive portion of the backplane.
4. The packaged semiconductor device of claim 3,
the area of the electrically insulating and thermally conductive portion of the backplate is greater than or equal to the area of the lateral semiconductor power device chip.
5. The packaged semiconductor device of claim 1,
the backplate comprises a metal portion and an electrically insulating and thermally conductive portion disposed adjacent to the metal portion;
wherein the lateral semiconductor power device chip is disposed on the electrically insulating and thermally conductive portion of the backplate;
wherein an electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conductive portion of the backplane.
6. The packaged semiconductor device of claim 5,
the electrically insulating and thermally conductive portion of the backplate has an area greater than or equal to the area of the lateral semiconductor power device chip and has a thickness extending to the bottom of the packaged semiconductor device.
7. The packaged semiconductor device of claim 1,
and the first electrode, the second electrode, the at least one metal lead and the metal part of the back plate are electrically connected through bonding wires.
8. The packaged semiconductor device of claim 1,
the lateral semiconductor power device chip is a Field Effect Transistor (FET);
wherein the first electrode is a gate and the gate is electrically connected to a first metal lead;
the second electrode is a source electrode, and the source electrode is electrically connected to the metal portion of the backplate;
the third electrode is a drain, and the drain is electrically connected to the second metal lead.
9. The packaged semiconductor device of claim 1,
the lateral semiconductor power device chip is a Field Effect Transistor (FET);
wherein the first electrode is a gate and the gate is electrically connected to a first metal lead;
the second electrode is a drain electrode, and the drain electrode is electrically connected to the metal portion of the backplate;
the third electrode is a source electrode, and the source electrode is electrically connected to the second metal lead.
10. The packaged semiconductor device of claim 1,
the lateral semiconductor power device chip comprises at least one of the following: GaN, GaN/Si, or GaN/ceramic.
11. The packaged semiconductor device of claim 1,
the package conforms to the JEDEC standard format.
12. A method of packaging a lateral semiconductor power device die, said lateral semiconductor power device die comprising an upper surface and a lower surface, wherein the upper surface has at least two electrodes disposed thereon and the upper and lower surfaces are coplanar, the method comprising:
electrically connecting a first one of the at least two electrodes to a first metal lead of the device package;
disposing an electrically insulating and thermally conductive adhesive between the lower surface of the lateral semiconductor power device chip and the backplane of the device package;
wherein the back plate comprises at least one metal portion electrically connected to a second of the at least two electrodes.
13. The method of claim 12,
the back plate only comprises a metal part and is positioned below the transverse semiconductor power device chip; and is
An electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the backplane.
14. The method of claim 12, wherein the backing plate comprises a metal portion and an electrically insulating and thermally conductive portion disposed on the metal portion;
wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conductive portion of the backplate;
an electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conductive portion of the backplane.
15. The method of claim 14,
the area of the electrically insulating and thermally conductive portion of the backplate is greater than or equal to the area of the lateral semiconductor power device chip.
16. The method of claim 12,
the backplate comprises a metal portion and an electrically insulating and thermally conductive portion disposed adjacent to the metal portion;
the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conductive portion of the backplate;
an electrically insulating and thermally conductive adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conductive portion of the backplane.
17. The method of claim 16,
the electrically insulating and thermally conductive portion of the backplate has an area greater than or equal to the area of the lateral semiconductor power device chip and has a thickness extending to the bottom of the packaged semiconductor device.
18. The method of claim 12,
and the first electrode, the second electrode, the at least one metal lead and the metal part of the back plate are electrically connected through bonding wires.
19. The method of claim 12,
the lateral semiconductor power device chip is a Field Effect Transistor (FET);
wherein the first electrode is a gate, and the gate is electrically connected to the first metal lead;
the second electrode is a source electrode, and the source electrode is electrically connected to the metal portion of the backplate;
the third electrode is a drain and the drain is electrically connected to a second metal lead of the package.
20. The method of claim 12,
the lateral semiconductor power device chip is a Field Effect Transistor (FET);
wherein the first electrode is a gate and is electrically connected to the first metal lead;
a second electrode is a drain and is electrically connected to the metal portion of the backplate;
the third electrode is a source and is electrically connected to a second metal lead of the package.
21. The method of claim 12,
the lateral semiconductor power device chip includes at least one of: GaN, GaN/Si, or GaN/ceramic.
22. The method of claim 12,
the package conforms to the JEDEC standard format.
CN202010395716.1A 2019-05-12 2020-05-12 Packaged semiconductor device and packaging method thereof Pending CN111816623A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962846667P 2019-05-12 2019-05-12
US62/846,667 2019-05-12
US16/871,026 2020-05-10
US16/871,026 US11107755B2 (en) 2019-05-12 2020-05-10 Packaging for lateral high voltage GaN power devices

Publications (1)

Publication Number Publication Date
CN111816623A true CN111816623A (en) 2020-10-23

Family

ID=72847670

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010395716.1A Pending CN111816623A (en) 2019-05-12 2020-05-12 Packaged semiconductor device and packaging method thereof

Country Status (1)

Country Link
CN (1) CN111816623A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116646256A (en) * 2023-05-26 2023-08-25 苏州量芯微半导体有限公司 Processing method before packaging gallium nitride power device and packaging structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110189821A1 (en) * 2007-06-04 2011-08-04 Infineon Technologies Ag Semiconductor device
CN103367271A (en) * 2012-03-27 2013-10-23 英飞凌科技股份有限公司 Semiconductor packages and methods of formation thereof
US20140284610A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN104716128A (en) * 2013-12-16 2015-06-17 台达电子企业管理（上海）有限公司 Power module, power converter and method for manufacturing power module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110189821A1 (en) * 2007-06-04 2011-08-04 Infineon Technologies Ag Semiconductor device
CN103367271A (en) * 2012-03-27 2013-10-23 英飞凌科技股份有限公司 Semiconductor packages and methods of formation thereof
US20140284610A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN104716128A (en) * 2013-12-16 2015-06-17 台达电子企业管理（上海）有限公司 Power module, power converter and method for manufacturing power module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116646256A (en) * 2023-05-26 2023-08-25 苏州量芯微半导体有限公司 Processing method before packaging gallium nitride power device and packaging structure

Similar Documents

Publication Publication Date Title
US9165871B2 (en) Semiconductor unit and semiconductor device using the same
JP5632416B2 (en) Stacked composite device comprising a III-V transistor and a IV group vertical transistor
JP5526179B2 (en) Stacked composite device comprising a III-V transistor and a IV group lateral transistor
US20150243640A1 (en) Semiconductor device
US8421087B2 (en) Semiconductor module including a switch and non-central diode
US9433075B2 (en) Electric power semiconductor device
CN102005441A (en) Hybrid packaged gate controlled semiconductor switching device and preparing method
US20070229143A1 (en) Power Module
JP5643783B2 (en) Stacked composite device comprising a III-V transistor and a group IV diode
CN103390612A (en) Semiconductor device, semiconductor device module and method of fabricating semiconductor device
JP2021141222A (en) Semiconductor module
US8853707B2 (en) High voltage cascoded III-nitride rectifier package with etched leadframe
JP7428017B2 (en) semiconductor module
CN111816623A (en) Packaged semiconductor device and packaging method thereof
US11107755B2 (en) Packaging for lateral high voltage GaN power devices
EP3297022B1 (en) Top side cooling for gan power device
US20230146758A1 (en) Semiconductor device
JP2021180234A (en) Semiconductor module
JP2021141221A (en) Semiconductor module
US20220406690A1 (en) Semiconductor device
US20240030096A1 (en) Power block based on top-side cool surface-mount discrete devices with double-sided heat sinking
KR102616298B1 (en) Double Side Cooling Power Module And Method For Manufacturing Thereof
WO2021079913A1 (en) Semiconductor device
US20230223331A1 (en) Semiconductor module
CN107706239A (en) Gallium nitride high mobility transistor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210727

Address after: 215125 room f405, No. 388 Ruoshui Road, Suzhou Industrial Park, Suzhou area, China (Jiangsu) pilot Free Trade Zone, Suzhou, Jiangsu

Applicant after: Suzhou Quantum Semiconductor Co., Ltd

Address before: 1064 enhart Road, k7p3c2

Applicant before: Li Zhanming

Applicant before: Fu Yue

Applicant before: Liu Yanfei

SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination