CN111816571A - Semiconductor packaging method - Google Patents

Semiconductor packaging method Download PDF

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Publication number
CN111816571A
CN111816571A CN202010782035.0A CN202010782035A CN111816571A CN 111816571 A CN111816571 A CN 111816571A CN 202010782035 A CN202010782035 A CN 202010782035A CN 111816571 A CN111816571 A CN 111816571A
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CN
China
Prior art keywords
film
chip
plastic package
packaging method
semiconductor packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010782035.0A
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Chinese (zh)
Inventor
彭建军
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Hangzhou Silergy Semiconductor Technology Ltd
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Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN202010782035.0A priority Critical patent/CN111816571A/en
Publication of CN111816571A publication Critical patent/CN111816571A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The invention provides a semiconductor packaging method, which comprises the steps of providing a film, connecting a supporting piece surrounding the film with the periphery of the film, and enclosing the supporting piece and the film to form a patch area; in the patch area, a patch surface of the film has viscosity; and attaching at least one chip on the mounting surface of the mounting area, and carrying out plastic package and cutting twice to form an independent packaging body. The invention adopts the film to replace the substrate in the prior art, and a second plastic package body is formed in the subsequent process as a lining plate on the back of the chip; the packaging method does not need to adopt a binder and a substrate, and can greatly reduce the packaging cost.

Description

Semiconductor packaging method
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging method.
Background
At present, the conventional semiconductor packaging and advanced packaging use a chip mounting technology, which is divided into a glue/solder paste brushing process, a glue/solder paste dispensing process, a glue/solder paste coating process, a glue/solder paste spraying process, a DAF (digital addressable fabrication) process and the like. The carrier for mounting the chip comprises a frame, a base plate, a glass plate, a PCB (printed Circuit Board), a DBC (direct bonded copper) plate and the like. These techniques use a process in which an adhesive is matched to a carrier plate, for example, the adhesive is applied to the carrier plate, and then the chip is attached. The process of mating the adhesive with the carrier plate is an important process step and high cost procedure in the conventional semiconductor package.
Therefore, if a semiconductor packaging method without a process of matching an adhesive with a carrier plate can be provided, the semiconductor packaging cost can be greatly reduced.
Disclosure of Invention
The invention aims to provide a semiconductor packaging method which can greatly reduce the packaging cost.
In order to solve the above problems, the present invention provides a semiconductor packaging method, which includes the steps of: (a) providing a film, wherein a support piece surrounding the film is connected with the periphery of the film, the support piece and the film surround a chip mounting area, and a mounting surface of the film has viscosity in the chip mounting area; (b) attaching at least one chip to the mounting surface of the mounting area, wherein the chip is provided with a front surface and a back surface opposite to the front surface, the front surface is provided with at least one welding pad, and the back surface is attached to the mounting surface of the film; (c) carrying out primary plastic package to form a first plastic package body, wherein the first plastic package body covers the front side of the chip and the patch area; (d) removing the film and the supporting piece to expose the back surface of the chip and the back surface of the first plastic package body; (e) carrying out secondary plastic package to form a second plastic package body, wherein the second plastic package body covers the back surface of the chip, and the welding pad is exposed out of the first plastic package body; (f) and cutting to form independent packaging bodies.
In one embodiment, a surface of the periphery of the film has an adhesive property, and the bottom surface of the support member is joined to the surface having the adhesive property.
In one embodiment, in the step (e), after the second molding, a portion of the first molding is removed to expose the bonding pad.
In one embodiment, after step (e), the method further comprises the following steps: (e1) and forming a conductive layer on the surface of the first plastic package, wherein the conductive layer is electrically connected with the welding pad.
In an embodiment, after the step (e1), the method further includes the following steps: (e2) and forming at least one pin on the conductive layer, wherein the pin is electrically connected with the welding pad through the conductive layer.
In an embodiment, after the step (e2), the method further includes the following steps: (e3) and plastically packaging the pin to form a third plastic packaging body, wherein the surface of the pin departing from the chip is exposed on one surface of the third plastic packaging body.
In an embodiment, after the step (e3), the method further includes the following steps: (e4) and planting balls on the surface of the pin or forming a metal layer to be used as a connection point for electrically connecting the chip with an external structure.
In an embodiment, the first molding compound and the second molding compound are made of the same material.
The invention has the advantages that the semiconductor packaging method of the invention abandons the substrate, adopts the film to replace the substrate in the prior art, the film only plays the function of a disposable carrier in the packaging process, and a second plastic package body is formed in the subsequent process as the lining plate of the back of the chip. Compared with the prior art, the chip is usually adhered to a substrate by adopting an adhesive and the like, and then subsequent packaging is carried out, wherein in the structure of the finally formed packaging body, the substrate is used as a lining plate on the back surface of the chip, and the price of the adhesive is high, so that the cost of the semiconductor is increased; the packaging method does not need to adopt a substrate and a binder, saves the manufacturing of the substrate and the binder, and greatly saves the cost. Particularly, the price of the film in the packaging method is 1/50-1/10 of the adhesive, so that the packaging method greatly saves the cost.
Drawings
FIG. 1 is a schematic step diagram illustrating an embodiment of a semiconductor packaging method according to the present invention;
fig. 2A to 2J are process flow diagrams of the semiconductor packaging method of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The terms "first," "second," "third," and the like in the description and in the claims of the present application and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The following describes in detail a specific embodiment of the semiconductor packaging method according to the present invention with reference to the drawings.
The invention provides a semiconductor packaging method. Fig. 1 is a schematic step diagram of a semiconductor packaging method according to an embodiment of the invention. Referring to fig. 1, the semiconductor packaging method of the present invention includes the following steps: step S10, providing a film, wherein a support piece surrounding the film is connected with the periphery of the film, the support piece and the film enclose a patch area, and a mounting surface of the film has viscosity in the patch area; step S11, attaching at least one chip on the mounting surface of the mounting area, wherein the chip is provided with a front surface and a back surface opposite to the front surface, the front surface is provided with at least one welding pad, and the back surface is adhered to the mounting surface of the film; step S12, carrying out primary plastic package to form a first plastic package body, wherein the first plastic package body covers the front surface of the chip and the patch area; step S13, removing the film and the supporting piece to expose the back surface of the chip and the back surface of the first plastic package body; step S14, carrying out secondary plastic package to form a second plastic package body, wherein the second plastic package body covers the back surface of the chip, and the welding pad is exposed out of the first plastic package body; and step S15, cutting to form an independent packaging body.
Fig. 2A to 2J are process flow diagrams of the semiconductor packaging method of the present invention.
Referring to step S10 and fig. 2A, a film 200 is provided, and a supporting member 201 surrounding the film 200 is connected to the periphery of the film 200 to prevent the film 200 from deforming; the support member 201 and the film 200 enclose a mounting area a, and a mounting surface 202 of the film 200 has adhesiveness in the mounting area a.
Specifically, the thin film 200 includes, but is not limited to, a high temperature film, a dry film, a front film, and the like, which are conventionally used in semiconductor packages. The support 201 is capable of supporting and fixing the film 200 to prevent the film 200 from deforming or shrinking, thereby affecting subsequent packaging. In this embodiment, a surface of the periphery of the film 200 has a sticky property, and the bottom surface of the supporting member 201 is adhered to the sticky surface, so as to connect the film 200 and the supporting member 201. The material of the supporting member 201 includes, but is not limited to, metal or other materials that can support and resist high temperature. The support member 201 is preferably in a closed figure, for example, in a general shape such as a ring shape, a rectangular box shape, etc., and an area surrounded by the support member 201 is the patch area a. In this embodiment, the supporting member 201 is a metal ring. The area surrounded by the ring is the patch area A.
Referring to step S11 and fig. 2B, at least one chip 203 is attached on the mounting surface 202 of the mounting area a. Wherein two chips 203 are schematically depicted in the figure. The chip 203 has a front side 203A and a back side 203B opposite the front side 203A. The front surface 203A has at least one pad 204, and the pad 204 is connected to the circuit of the chip 203, wherein the pad 204 includes, but is not limited to, a metal pillar. The back surface 203B is adhered to the mounting surface 202 of the film 200. Since the mounting surface 202 of the film 200 is self-adhesive, the chip 203 can be directly adhered to the film 200 without the need of performing a step of dispensing or gluing in advance in this step.
Referring to step S12 and fig. 2C, a first plastic package is performed to form a first plastic package body 205, and the first plastic package body 205 covers the front surface 203A of the chip 203 and the chip mounting area a. Specifically, the structure in step S11 may be placed in a conventional mold filled with a molding compound for plastic molding, so as to form the first plastic package body 205. The first plastic package body 205 covers the front surface 203A of the chip 203 and the mounting surface 202 of the mounting region a, that is, the first plastic package body 205 does not cover the supporting member 201 and the back surface of the film 200. In this step, the first molding compound 205 covers the pad 204, and in other embodiments of the present invention, the first molding compound 205 may not cover the surface of the pad 204, so as to avoid the subsequent process of exposing the surface of the pad 204.
Referring to step S13 and fig. 2D, the film 200 and the supporting member 201 are removed to expose the back surface 203B of the chip 203 and the back surface of the first plastic package body 205. Specifically, the thin film 200 and the support 201 may be removed by a conventional method such as mechanical peeling, chemical dissolution, or the like.
Further, a step (not shown in the drawings) of punching positioning holes for positioning the respective components with respect to the external device is also included after step S13.
Further, a surface roughening process is also included after step S13. Specifically, the structure formed in step S13 is cleaned physically or chemically by plasma cleaning, etching, etc. to facilitate the subsequent plastic packaging process.
Referring to step S14 and fig. 2E, a second molding process is performed to form a second molding compound 206, the second molding compound 206 covers the back surface 203B of the chip 203, and the bonding pads 204 are exposed outside the first molding compound 205. Specifically, in this step, first, a second plastic package is performed to form the second plastic package body 206; in this embodiment, the method of the second plastic package is the same as that of the first plastic package, and the material of the first plastic package body 205 is the same as that of the second plastic package body 206. Removing part of the first plastic package body 205 to expose the surface of the pad 204; wherein, a portion of the first molding compound 205 can be removed by grinding, etching or drilling, etc., to expose the surface of the pad 204. For example, in the present embodiment, a grinding method is used to remove a portion of the first molding compound 205, exposing the surface of the pad 204. The pad 204 can be used as a connection point for connecting the chip 203 with the outside.
Further, referring to fig. 2F, after step S14, the method further includes the following steps: a conductive layer 207 is formed on the surface of the first molding compound 205, wherein the conductive layer 207 is electrically connected to the pad 204. The conductive layer 207 may be a patterned metal layer. This step is an optional step.
Further, referring to fig. 2G, after step S14 or the step of forming the conductive layer 207, the method further includes the following steps: at least one pin 208 is formed on the conductive layer 207 or the surface of the first molding compound 205, and the pin 208 is electrically connected to the pad 204. In this embodiment, a pin 208 is formed on the conductive layer 207, and the pin 208 is electrically connected to the pad 204 through the conductive layer 207. Wherein the conductive layer 207 can be patterned before the leads 208 are formed, so that the conductive layer 207 remains only at the positions where the leads 208 are formed. The pins 208 may serve as connection points for the chip 203 to connect with the outside, and the pins 208 fan out the pads 204 of the chip 203 to increase the connection distance. This step is an optional step.
Further, referring to fig. 2H, after the pins 208 are formed, the pins 208 are plastic-molded to form a third plastic-molded body 209, and a surface of the pins 208, which is away from the chip 203, is exposed to a surface of the third plastic-molded body 209. The third plastic package body 209 protects the pins 208, and the material of the third plastic package body 209 may be the same as the material of the first plastic package body 205. The method for exposing the surface of the pin 208, which faces away from the chip 203, to a surface of the third molding compound 209 includes: the third molding compound 209 is polished to expose the leads 208. This step is an optional step.
Further, referring to fig. 2I, after the leads 208 are formed, balls are implanted on the surfaces of the leads 208 or metal layers are formed to serve as connection points for electrically connecting the chip 203 with an external structure. Specifically, in the present embodiment, a metal ball 210 is embedded on the surface of the lead 208, and the metal ball 210 serves as a connection point for electrically connecting the chip 203 with an external structure. The material of the metal ball 210 includes, but is not limited to, nickel, gold, tin, etc. This step is an optional step.
Referring to step S15 and fig. 2J, a separate package is formed by dicing. Specifically, the structure is cut by a laser cutting method or a mechanical cutting method to form an independent packaging body.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (8)

1. A semiconductor packaging method, comprising the steps of:
(a) providing a film, wherein a support piece surrounding the film is connected with the periphery of the film, the support piece and the film surround a chip mounting area, and a mounting surface of the film has viscosity in the chip mounting area;
(b) attaching at least one chip to the mounting surface of the mounting area, wherein the chip is provided with a front surface and a back surface opposite to the front surface, the front surface is provided with at least one welding pad, and the back surface is attached to the mounting surface of the film;
(c) carrying out primary plastic package to form a first plastic package body, wherein the first plastic package body covers the front side of the chip and the patch area;
(d) removing the film and the supporting piece to expose the back surface of the chip and the back surface of the first plastic package body;
(e) carrying out secondary plastic package to form a second plastic package body, wherein the second plastic package body covers the back surface of the chip, and the welding pad is exposed out of the first plastic package body;
(f) and cutting to form independent packaging bodies.
2. The semiconductor packaging method according to claim 1, wherein a surface of an outer periphery of the film has an adhesive property, and a bottom surface of the support is connected to the surface having the adhesive property.
3. The semiconductor packaging method of claim 1, wherein in the step (e), after the second molding, a portion of the first molding is removed to expose the bonding pads.
4. The semiconductor packaging method according to claim 1, further comprising, after the step (e), the steps of: (e1) and forming a conductive layer on the surface of the first plastic package, wherein the conductive layer is electrically connected with the welding pad.
5. The semiconductor packaging method according to claim 4, further comprising, after the step (e1), the steps of: (e2) and forming at least one pin on the conductive layer, wherein the pin is electrically connected with the welding pad through the conductive layer.
6. The semiconductor packaging method according to claim 5, further comprising, after the step (e2), the steps of: (e3) and plastically packaging the pin to form a third plastic packaging body, wherein the surface of the pin departing from the chip is exposed on one surface of the third plastic packaging body.
7. The semiconductor packaging method according to claim 6, further comprising, after the step (e3), the steps of: (e4) and planting balls on the surface of the pin or forming a metal layer to be used as a connection point for electrically connecting the chip with an external structure.
8. The semiconductor packaging method of claim 1, wherein the first molding compound and the second molding compound are made of the same material.
CN202010782035.0A 2020-08-06 2020-08-06 Semiconductor packaging method Pending CN111816571A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010782035.0A CN111816571A (en) 2020-08-06 2020-08-06 Semiconductor packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010782035.0A CN111816571A (en) 2020-08-06 2020-08-06 Semiconductor packaging method

Publications (1)

Publication Number Publication Date
CN111816571A true CN111816571A (en) 2020-10-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010782035.0A Pending CN111816571A (en) 2020-08-06 2020-08-06 Semiconductor packaging method

Country Status (1)

Country Link
CN (1) CN111816571A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113270331A (en) * 2021-05-12 2021-08-17 湖南越摩先进半导体有限公司 Packaging method and packaging structure of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113270331A (en) * 2021-05-12 2021-08-17 湖南越摩先进半导体有限公司 Packaging method and packaging structure of semiconductor device
CN113270331B (en) * 2021-05-12 2023-12-01 湖南越摩先进半导体有限公司 Packaging method and packaging structure of semiconductor device

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Application publication date: 20201023