CN111816225B - Memory device and adjusting method of reading reference voltage thereof - Google Patents
Memory device and adjusting method of reading reference voltage thereof Download PDFInfo
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Abstract
The invention provides a memory device and an adjusting method of a reading reference voltage thereof. The adjusting method of the reading reference voltage comprises the following steps: obtaining a plurality of count values of the memory cells with the set logic level, wherein the count values respectively correspond to a plurality of reading steps; calculating a plurality of counting difference values according to the counting value, generating an average difference value according to the counting difference values, and generating a critical value according to the average difference value; calculating a balance count value of the storage unit; respectively obtaining a first reference count value and a second reference count value according to the first reading step and the second reading step, and calculating a reference count difference value; and setting a voltage adjustment value according to the reference count difference value, the critical value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value to generate an adjusted reference voltage.
Description
Technical Field
The present invention relates to a memory device and a method for adjusting a read reference voltage thereof, and more particularly, to a memory device and a method for adjusting a read reference voltage thereof.
Background
In the field of flash memory technology, in order to determine the logic level of data stored in a memory cell, one or more read reference voltages are set, and the logic level of the data stored in the memory cell is determined by comparing the threshold voltage of the memory cell with the read reference voltage. However, after the flash memory is used for a long time, the characteristics of the memory cells may change after a plurality of program/erase cycles or a long time of data storage. In this way, the memory cell will drift according to the characteristics of the threshold voltage exhibited by the stored data. Under such conditions, the data read operation of the memory cell is performed using the read reference voltage that is originally set, and the read data may be incorrect.
Disclosure of Invention
The invention provides a memory device and a method for adjusting read reference voltage thereof, which can improve the correctness of read data.
The adjusting method of the reading reference voltage comprises the following steps: reading a plurality of reading steps aiming at a plurality of storage units of the memory, and respectively obtaining a plurality of count values of the storage units with set logic levels, wherein the count values respectively correspond to the reading steps; calculating a plurality of counting difference values according to the counting value, generating an average difference value according to the counting difference values, and generating a critical value according to the average difference value; calculating a balance count value for the memory cell, wherein the balance count value is equal to a number of memory cells programmed to set logic levels; setting a first reading step and a second reading step according to the reading reference voltage, respectively obtaining a first reference count value and a second reference count value of a storage unit with a set logic level, and calculating a reference count difference value of the first reference count value and the second reference count value; and setting a voltage adjustment value according to the reference count difference value, the critical value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value to generate an adjusted reference voltage.
The memory device comprises a memory, a memory controller and a host end. The memory controller is coupled to the memory. The host end is coupled with the memory controller. The host end is used for: reading a plurality of reading steps aiming at a plurality of storage units of the memory, and respectively obtaining a plurality of count values of the storage units with set logic levels, wherein the count values respectively correspond to the reading steps; calculating a plurality of counting difference values according to the counting value, generating an average difference value according to the counting difference values, and generating a critical value according to the average difference value; a balance count value for the memory cell is calculated, where the balance count value is equal to the number of memory cells programmed to set logic levels. The memory controller is used for setting a first reading step and a second reading step according to the reading reference voltage, respectively obtaining a first reference count value and a second reference count value of the memory unit with the set logic level, and calculating a reference count difference value of the first reference count value and the second reference count value; and setting a voltage adjustment value according to the reference count difference value, the critical value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value to generate an adjusted reference voltage.
Based on the above, the present invention calculates the variation states of the plurality of count values corresponding to the plurality of reading steps in the storage unit, and distinguishes the three distribution areas according to the variation states of the count values. The accuracy of the extracted data is improved by calculating the distribution area where the current reading reference voltage is located and adjusting the voltage value of the reading reference voltage accordingly.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a flow chart illustrating a method for adjusting a read reference voltage according to an embodiment of the invention;
FIG. 2A is a graph illustrating a count value versus read step for an embodiment of the present invention;
FIG. 2B is a graph showing a count difference versus read step for an embodiment of the present invention;
FIGS. 3A and 3B are schematic diagrams illustrating a reference voltage adjustment operation according to an embodiment of the invention;
FIG. 4A and FIG. 4B are schematic diagrams illustrating another embodiment of a reference voltage adjustment operation according to an embodiment of the present invention;
FIG. 5 shows a schematic diagram of a memory device of an embodiment of the invention;
FIG. 6 is a schematic diagram illustrating an operation of a read reference voltage adjustment method according to an embodiment of the invention.
The reference numbers illustrate:
s110 to S150, S610 to S630: read reference voltage adjustment step
210. 220, and (2) a step of: curve line
Z21, Z22, Z21A, Z22A: region(s)
RS1, RS2, RRS1, RRS 2: read step
A. B, C: distribution area
Cn, Cn + 1: reference count value
TH: critical value
RV: reading reference voltage
TRV: adjusted read reference voltage
500: memory device
512: memory device
511: memory controller
513: host computer terminal
510: memory card
Detailed Description
Referring to fig. 1, fig. 1 is a flowchart illustrating a read reference voltage adjustment method according to an embodiment of the invention. The method for adjusting the read reference voltage of FIG. 1 is suitable for the read operation of the memory. In this embodiment, the memory may be a non-volatile memory, such as a flash memory. In fig. 1, step S110 performs a plurality of reading steps on a plurality of memory cells of the memory, and obtains a plurality of count values of the memory cells with a set logic level, wherein the count values correspond to the plurality of reading steps. Please refer to fig. 1 and fig. 2A synchronously, wherein fig. 2A is a graph illustrating a relationship between a count value and a read step according to an embodiment of the present invention. In this embodiment, the set logic level is, for example, logic level 1. For example, the read step of the first step may correspond to a read reference voltage equal to a first voltage value, and the read step of the second step may correspond to a read reference voltage equal to a second voltage value, wherein the second voltage value is greater than the first voltage value, and the second voltage value may be equal to the first voltage value incremented by a step value dV. In this way, the order of the read step may increase as the read reference voltage increases, and the voltage value of the read reference voltage corresponding to the nth read step may be equal to the first voltage value + (n-1) × dV.
The curve 210 shown in fig. 2A can be obtained by sequentially increasing the read steps to read the memory cells in the memory, and calculating a plurality of count values of logic level 1 of the data stored in the memory cells when the read steps correspond to a plurality of read steps. Wherein the curve 210 is a continuously increasing curve, and in the zones Z21, Z22, the curve 210 has a relatively large rising slope.
Referring to fig. 1 again, in step S120, a plurality of count differences are calculated according to the count values in step S110, an average difference is generated according to the count differences, and a threshold is generated according to the average difference. In detail, a subtraction operation is performed on two count values corresponding to adjacent reading steps, and an absolute value of the subtraction operation is taken, so that a plurality of count difference values can be obtained. The counting difference is used for reflecting the change state of the counting value. Then, all count differences are summed and the result of the summation is divided by the total number of read steps to produce an average difference. In addition, the average difference is multiplied by a constant k to generate the threshold, wherein the constant k is a predetermined value and is a real number greater than 1.
Please refer to fig. 1, fig. 2A and fig. 2B synchronously, wherein fig. 2B shows a graph of a relationship between a count difference and a read step according to an embodiment of the present invention. In fig. 2B, a plurality of count difference values form a curve 220. The threshold value TH may be generated by summing all count differences, dividing the sum by the total number of read steps to generate an average difference, and multiplying the average difference by a constant k. In fig. 2B, by comparing the threshold TH with the plurality of count differences in the curve 220, the read steps RS1, RS2, the read steps RS1, RS2 can be obtained, and all the read steps can be divided into three distribution regions A, B, C. Wherein, the reading step of the distribution area A is smaller than the reading step RS 1; the reading step of the distribution region B is between the reading steps RS1 and RS 2; and, the read step of distribution region C is greater than read step RS 2.
Note that in fig. 2B, there are regions Z21A and Z22A corresponding to regions Z21 and Z22, respectively, in fig. 2A. Among them, the regions Z21, Z22 in fig. 2A having relatively large changing count values correspond to the regions Z21A, Z22A in fig. 2B having relatively large count difference values.
Continuing with the above description, step S130 calculates a balance count value of the memory cell, wherein the balance count value is equal to the number of the memory cells programmed to set logic levels (e.g., logic level 1). Taking a memory cell with 16K bytes (byte) for example, when half of the memory cells are programmed to logic level 1, the balanced count value is 16384 × 8/2-65536.
Next, step S140 sets a first read step and a second read step according to the read reference voltage, respectively obtains a first reference count value and a second reference count value of the memory cell with a set logic level according to the first read step and the second read step, and calculates a reference count difference between the first reference count value and the second reference count value. Please refer to fig. 1, fig. 3A and fig. 3B synchronously. Fig. 3A and 3B are schematic diagrams illustrating a reference voltage adjusting operation according to an embodiment of the invention. In fig. 3A, the first reference count value Cn and the second reference count value Cn +1 of the memory cells at the set logic level are obtained by the first read step RRS1 and the second read step RRS2, respectively. In the present embodiment, the first reference count value Cn and the second reference count value Cn +1 are 73370 and 70580, respectively. Then, the first reference count value Cn and the second reference count value Cn +1 are subtracted from each other, and the absolute value of the result is taken, whereby the reference count difference dn is 2750.
Next, step S150 sets a voltage adjustment value according to the reference count difference dn, the threshold TH and the balance count value B, and adjusts the read reference voltage according to the voltage adjustment value to generate an adjusted reference voltage. Continuing with the embodiment of fig. 3A and 3B, the threshold TH may be equal to 1000 × 2-2000, taking the average value equal to 1000, the constant k equal to 2, the step number of the first read step equal to 2, and the balance count value B equal to 65536 as examples. In this way, the reference count difference dn (2750) is greater than the threshold TH, and the difference (B-Cn) between the balance count value B and the first reference count value Cn is greater than the product (n × TH) of the threshold and the step number of the first read step, which indicates that the currently set read step falls in the area a or the area C (in this embodiment, the area a). Therefore, the difference between the balance count value B and the first reference count value Cn is divided by the average difference dn to obtain a voltage adjustment value, and the read reference voltage RV is adjusted according to the calculated voltage adjustment value to generate the adjusted read reference voltage TRV.
As shown in fig. 3B, it can be found that, by the adjustment of the reading reference voltage, the adjusted reading reference voltage TRV can fall on the central portion of the curve, and the accuracy of reading data is improved.
Please refer to fig. 4A and 4B. Fig. 4A and 4B are schematic diagrams illustrating another embodiment of the reference voltage adjusting operation according to the embodiment of the invention. In fig. 4A, the first reference count value Cn and the second reference count value Cn +1 of the memory cells at the set logic level are obtained by the first read step RRS1 and the second read step RRS2, respectively. In the present embodiment, the first reference count value Cn and the second reference count value Cn +1 are 68680 and 67340, respectively. Then, the first reference count value Cn and the second reference count value Cn +1 are subtracted from each other, and the absolute value of the subtracted value is taken, whereby the reference count difference dn is 1340. Based on the reference count difference dn being smaller than the threshold TH (2000), it indicates that the currently set read step falls in the region B. Therefore, the difference between the balance count value B and the first reference count value Cn is divided by the reference count difference dn to obtain a voltage adjustment value, and the read reference voltage RV is adjusted according to the calculated voltage adjustment value to generate the adjusted read reference voltage TRV.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a memory device according to an embodiment of the invention. The memory device 500 includes a memory 512, a memory controller 511, and a host 513. The memory controller 511 is coupled to the memory 512 and may be integrated into a memory card 510. The host 513 is connected to the memory card 510 and coupled to the memory controller 511. In the present embodiment, the host 513 can be configured to perform the steps S110 to S130 as shown in the embodiment of fig. 1 to obtain the average difference value, the threshold value and the balance count value. The memory controller 511 can execute the steps S140 to S150 of the embodiment shown in fig. 1 to adjust the reference read voltage.
The details of the implementation of steps S110 to S150 have been described in the foregoing embodiments, and are not repeated herein.
Incidentally, the host 513 may be a computer device or any electronic device with computing capability. The host 513 can be used to connect to the memory card 510 and obtain the average difference, the threshold and the balance count. The host 513 may further store the average difference, the threshold, and the balance count in the memory card 510. Under the condition that the host 513 is offline (disconnected) from the memory card 510, the memory card controller 511 can adjust the read reference voltage during the reading operation of the value type memory 512 to maintain the correctness of the read data.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating an operation of a read reference voltage adjusting method according to an embodiment of the invention. In conjunction with the memory device 500 of fig. 5, in step S610, the host 513 may perform initialization setting by performing steps S110 to S130, and obtain the balance count value B and the average difference value Avg. Next, when the data reading operation is performed on the memory 512, the Error Check and Correction (ECC) check operation of step S620 may be performed. When the ECC check is passed, the data reading operation can be continued. When the ECC check fails, the tracking process may be executed through step S630. Here, the tracking process of step S630 can be executed through steps S140 to S150, and the read reference voltage is adjusted accordingly.
Through the tracking process of step S630, the read reference voltage can be adaptively adjusted, the data reading accuracy can be maintained, and the utilization efficiency of the memory can be improved.
In summary, the present invention performs the adjustment operation of the read reference voltage by calculating the variation states of the count values corresponding to the read steps. Therefore, when the characteristics of the memory cells change, the corresponding read reference voltage can still be effectively set so as to improve the accuracy of the read data.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (6)
1. A method for adjusting a read reference voltage, which is suitable for a memory, comprises the following steps:
performing a plurality of read steps on a plurality of memory cells of the memory, and reading the number of the plurality of memory cells with a set logic level in the plurality of memory cells by calculating the number of the plurality of memory cells corresponding to the plurality of read steps to obtain a plurality of count values respectively corresponding to the plurality of read steps;
calculating a plurality of count difference values according to the plurality of count values, generating an average difference value according to the plurality of count difference values, and generating a critical value according to the average difference value;
calculating a balanced count value for the plurality of memory cells, wherein the balanced count value is equal to a number of the plurality of memory cells programmed to the set logic level;
setting a first reading step and a second reading step according to the reading reference voltage, respectively obtaining a first reference count value and a second reference count value of the memory unit with the set logic level, and calculating a reference count difference value of the first reference count value and the second reference count value; and
setting a voltage adjustment value according to the reference count difference, the threshold value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value to generate an adjusted read reference voltage, wherein the step of calculating the count differences according to the count values comprises:
calculating a difference between two count values corresponding to adjacent reading steps to obtain each count difference value, wherein the step of generating the threshold value according to the average difference value comprises:
multiplying the average difference by a constant to generate the threshold, wherein the constant is a real number greater than 1, wherein setting the voltage adjustment value according to the reference count difference, the threshold, and the balance count value comprises:
dividing the difference between the balanced count value and the first reference count value by the average difference to obtain the voltage adjustment value when the reference count difference is greater than the critical value and the difference between the balanced count value and the first reference count value is greater than the product of the critical value and the step number of the first reading step; and
when the reference count difference is less than the critical value, dividing the difference between the balance count value and the first reference count value by the reference count difference to obtain the voltage adjustment value.
2. The method according to claim 1, wherein the set logic level is a logic level 1.
3. The method of adjusting a read reference voltage according to claim 1, wherein the balanced count value is half of a total number of the plurality of memory cells.
4. A memory device comprises
A memory;
a memory controller coupled to the memory; and
a host coupled to the memory controller, wherein the host is configured to:
performing a plurality of read steps on a plurality of memory cells of the memory, and reading the number of the plurality of memory cells with a set logic level in the plurality of memory cells by calculating the number of the plurality of memory cells corresponding to the plurality of read steps to obtain a plurality of count values respectively corresponding to the plurality of read steps;
calculating a plurality of count difference values according to the plurality of count values, generating an average difference value according to the plurality of count difference values, and generating a critical value according to the average difference value; and
calculating a balanced count value for the plurality of memory cells, wherein the balanced count value is equal to a number of the plurality of memory cells programmed to the set logic level;
the memory controller is to:
setting a first reading step and a second reading step according to a reading reference voltage, respectively obtaining a first reference count value and a second reference count value of the memory unit with the set logic level, and calculating a reference count difference value of the first reference count value and the second reference count value;
setting a voltage adjustment value according to the reference count difference value, the critical value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value to generate an adjusted reference voltage;
calculating the difference of two counting values corresponding to adjacent reading steps to obtain each counting difference value;
multiplying the average difference value by a constant to generate the critical value, wherein the constant is a real number greater than 1;
when the reference count difference is greater than the threshold and the difference between the balanced count value and the first reference count value is greater than the product of the threshold and the step number of the first read step, dividing the difference between the balanced count value and the first reference count value by the average difference to obtain the voltage adjustment value; and
when the reference count difference is less than the critical value, dividing the difference between the balance count value and the first reference count value by the reference count difference to obtain the voltage adjustment value.
5. The memory device of claim 4, wherein the set logic level is a logic level 1.
6. The memory device of claim 4, wherein the host side is further to:
making the balanced count value equal to half of a total number of the plurality of memory cells.
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| JP5497754B2 (en) * | 2008-06-23 | 2014-05-21 | サンディスク アイエル リミテッド | Ad hoc flash memory reference cell |
| US7907449B2 (en) * | 2009-04-09 | 2011-03-15 | Sandisk Corporation | Two pass erase for non-volatile storage |
| US9633740B1 (en) * | 2016-02-11 | 2017-04-25 | Seagate Technology Llc | Read retry operations where likelihood value assignments change sign at different read voltages for each read retry |
| KR20150144147A (en) * | 2014-06-16 | 2015-12-24 | 에스케이하이닉스 주식회사 | Semiconductor device and operation method for the same |
| US20190304556A1 (en) * | 2018-03-29 | 2019-10-03 | Macronix International Co., Ltd. | Method for programming non-volatile memory and memory system |
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| CN103778962A (en) * | 2012-10-25 | 2014-05-07 | 三星电子株式会社 | Semiconductor memory system using regression analysis and read method thereof |
| CN103985415A (en) * | 2013-02-10 | 2014-08-13 | Lsi公司 | Retention-drift-history-based non-volatile memory read threshold optimization |
| CN105324819A (en) * | 2013-05-31 | 2016-02-10 | 西部数据技术公司 | Reading voltage calculation in solid-state storage devices |
| TW201913678A (en) * | 2017-09-08 | 2019-04-01 | 旺宏電子股份有限公司 | Method for programming non-volatile memory and memory system |
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| CN111816225A (en) | 2020-10-23 |
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