CN108133730B - Reading control method of flash memory, memory reading device and memory system - Google Patents
Reading control method of flash memory, memory reading device and memory system Download PDFInfo
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- CN108133730B CN108133730B CN201711404456.4A CN201711404456A CN108133730B CN 108133730 B CN108133730 B CN 108133730B CN 201711404456 A CN201711404456 A CN 201711404456A CN 108133730 B CN108133730 B CN 108133730B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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Abstract
The application provides a read control method of a flash memory, wherein the flash memory comprises a plurality of memory units, and the method comprises the following steps: acquiring a plurality of detection voltage values, wherein each detection voltage value is equal to the sum of default voltage and bias voltage, and the bias voltage is equal to integral multiple of unit offset; applying a plurality of detection voltages to the memory cells of the flash memory according to the plurality of detection voltage values, respectively, to perform a plurality of data read operations; obtaining a plurality of difference values, wherein the difference values represent data variation of two adjacent reading operations; determining an optimal detection voltage according to the plurality of difference values; and storing the optimal detection voltage for a subsequent data read operation of the flash memory. The reading control method can acquire the optimal detection voltage and perform data reading operation based on the optimal detection voltage. A memory reading device and a memory system are also provided.
Description
Technical Field
The invention relates to a reading control method of a flash memory, a memory reading device and a memory system.
Background
Flash memory is a nonvolatile memory, and is widely used in electronic devices such as memory cards, solid state disks, and portable multimedia players (portable multimedia players).
Flash memory can be divided into N0R type flash memory and NAND type flash memory.
Compared with the N0R flash memory, the NAND flash memory has better storage density and lower cost, so it is more widely used. In the NAND type flash memory, a plurality of memory cells each composed of a floating gate transistor are included, and generally, each memory cell can store 1 bit of data, but as the manufacturing process advances, a single memory cell can store more than 1 bit of data. When a default voltage (default sensing voltage) is applied to the control gate of the floating-gate transistor, the data of the bit stored in each memory cell is determined by the conduction state of the floating-gate transistor.
However, various operations of the flash memory, such as writing, reading, and saving, may generate noise that affects the number of electrons in the floating gate of the floating gate transistor, causing the value of the default voltage of the control gate of the floating gate transistor to change. Due to the change of the default voltage, it is possible to correctly obtain the data of the bit stored in the flash memory by supplying the default voltage to the control gate.
Disclosure of Invention
In view of this, the read control method of the flash memory according to the embodiment of the invention reduces the probability of data read errors of the entire flash memory by correcting the detection voltage applied to the memory cell of the flash memory.
According to a first aspect of the present invention, there is provided a read control method of a flash memory, wherein the flash memory includes a plurality of memory cells, each of the memory cells having at least one default voltage, the method comprising:
acquiring a plurality of detection voltage values, wherein each detection voltage value is equal to the sum of default voltage and bias voltage, and the bias voltage is equal to integral multiple of unit offset;
applying a plurality of detection voltages to the memory cells of the flash memory according to the plurality of detection voltage values, respectively, to perform a plurality of data read operations;
obtaining a plurality of difference values, wherein the difference values represent the data variation of two adjacent reading operations;
determining an optimal detection voltage according to the plurality of difference values;
and
and storing the optimal detection voltage for a data reading operation of the flash memory.
Preferably, the plurality of detection voltage values are obtained based on a default voltage uniform bias.
Preferably, the determining an optimal detection voltage according to the plurality of difference values:
and taking the detection voltage value corresponding to the minimum difference value as the optimal detection voltage.
Preferably, the plurality of detection voltage values are obtained based on a default voltage non-uniform bias.
Preferably, the determining an optimal detection voltage according to the plurality of difference values includes:
calculating a plurality of average values according to the plurality of difference values;
comparing the plurality of average values; and
and obtaining the optimal detection voltage in the detection voltage value interval corresponding to the minimum average value.
Preferably, a full voltage scan is performed between detection voltage values corresponding to the minimum average value to obtain the optimal detection voltage.
Preferably, obtaining the optimal detection voltage within the detection voltage value interval corresponding to the minimum average value comprises:
the estimated value is calculated by the following formula,
wherein v2 represents the minimum average value, start (v2) represents the start value of the numerical interval in which the minimum average value is located, length (v2) represents the number of unit offsets contained in the detection voltage value interval corresponding to the minimum average value, and v1 and v3 represent the average values corresponding to two detection voltage values adjacent to the minimum average value, respectively; and
and judging the optimal detection voltage according to the estimated value.
Preferably, the unit offset is related to a default voltage.
Preferably, the method further comprises the following steps: the read control method of claim 1 is performed when the ECC module cannot correct the data read from the flash memory or the ECC module determines that the error rate exceeds a certain threshold.
According to a second aspect of the present invention, there is provided a memory reading apparatus for reading data in a flash memory, wherein the flash memory includes a plurality of memory cells, each of the memory cells has at least a default voltage, the memory reading apparatus includes a voltage adjustment module and a control unit,
the voltage adjustment module includes:
an offset generating unit for acquiring a plurality of detection voltage values, each detection voltage value being equal to a sum of a default voltage and an offset voltage, the offset voltages being equal to integer multiples of a unit offset amount;
the reading unit executes data reading operation for multiple times according to the detection voltage values respectively;
the calculating unit is used for obtaining a plurality of difference values, and the difference values represent the data variation of two adjacent reading operations;
a determination unit configured to determine an optimal detection voltage according to the plurality of difference values;
the control unit is used for controlling the starting and the closing of the voltage adjusting module and applying a plurality of detection voltages to a part of memory cells of the flash memory according to the plurality of detection voltage values.
Preferably, the bias generating unit includes a first bias generating unit for obtaining the plurality of detection voltage values based on a default voltage uniform bias.
Preferably, the determination unit includes a first determination unit including:
and taking the detection voltage value corresponding to the minimum difference value as the optimal detection voltage.
Preferably, the bias generating unit includes a second bias generating unit for obtaining the plurality of detection voltage values based on a default voltage non-uniform bias.
Preferably, the determination unit includes: and calculating a plurality of average values according to the plurality of difference values, and obtaining the optimal detection voltage in the detection voltage value interval corresponding to the minimum average value, wherein the average value is the difference value obtained by each reading operation divided by the number of unit offsets contained in the corresponding detection voltage value interval.
Preferably, the determination unit includes:
the estimated value is calculated by the following formula,
wherein v2 represents the minimum average value, start (v2) represents the start value of the numerical interval in which the minimum average value is located, length (v2) represents the number of unit offsets contained in the detection voltage value interval corresponding to the minimum average value, and v1 and v3 represent the average values corresponding to two detection voltage values adjacent to the minimum average value, respectively; and
and judging the optimal detection voltage according to the estimated value.
Preferably, the unit offset is related to a default voltage.
Preferably, the method further comprises the following steps: and the control module starts the voltage adjusting module when the ECC circuit cannot correct the data read from the flash memory or the ECC module judges that the error rate exceeds a specific threshold value.
According to a third aspect of the present invention, there is provided a memory system comprising a flash memory including a plurality of memory cells, and each of the memory cells having at least a default voltage,
the memory system further comprises a memory controller, and the memory controller further comprises any one of the memory reading devices.
The read control method of the flash memory provided by the embodiment of the invention sets the unit offset, performs uniform or non-uniform offset based on the unit offset to obtain a plurality of detection voltage values, executes read operation according to the detection voltage values, calculates difference values according to read data, further determines the optimal detection voltage, and stores the optimal detection voltage for later data reading. The read control method reduces read-out error data by correcting the detection voltage.
In a further embodiment, the read control method obtains a plurality of detection voltage values in a non-uniform offset manner, calculates an average value according to the counted number of memory cells with the same data, judges a value interval where the optimal detection voltage is located according to the average value, and finally determines the optimal detection voltage. The offset times are reduced in a non-uniform manner to save execution time.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing embodiments of the present invention with reference to the following drawings, in which:
FIG. 1 is a block diagram of a flash memory system;
FIG. 2 is a block diagram of a memory reading device according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a first embodiment of a voltage adjustment module of a memory reading device;
FIG. 4 is a diagram illustrating statistical results of the voltage adjustment module according to the first embodiment;
FIG. 5 is a diagram illustrating a second embodiment of a voltage adjustment module of a memory reading apparatus;
FIG. 6 is a diagram illustrating statistical results of a voltage adjustment module according to a second embodiment;
FIG. 7 is a flow chart of a read control method according to an embodiment of the invention;
fig. 8 is a comparison graph of the decoding effect of the ECC circuit after the adjustment method of the detection voltage provided by the prior art and the present invention is adopted.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Fig. 1 is a structural diagram of a flash memory system.
The flash memory system 100 is, for example, a computer system using a Solid State Disk (SSD). The computer system includes a host 130. The solid state disk includes a flash memory 110 and a memory control device 120.
The host 130 accesses the memory 110 via the memory controller 120. In the flash memory system, the storage data is encoded data generated by encoding original data, and the original data can be obtained only by decoding the storage data in the reading process. The host 130 includes, for example, a processor. In the use state, the processor loads programs or reads data from the memory 110, and writes data to the memory 110.
The flash memory 110 is composed of a plurality of memory pages P _0 to P _ N, each of which includes a plurality of memory cells M _0 to M _ K composed of floating gate transistors, each of which stores data of one or more bits (bits). The memory controller 120 reads the data stored by the memory cells by providing the appropriate sense voltage to the control gates of the transistors. For example, if the memory cell M _0 stores 3 bits of data, i.e. the binary data that can be stored is 000,001,010,011,100,101,110,111(23), the memory controller 120 needs to set 8 detection voltages and read the binary data stored in the memory cell based on the 8 detection voltages. This assumption is for illustrative purposes only and is not intended to be limiting.
The memory controller 120 is, for example, a separate integrated circuit chip including a memory reading device (not shown) and a write control device (not shown) for controlling reading and writing of the flash memory 110, respectively. During a write operation, the write controller LDPC-encodes the original data to generate the storage data, thereby writing the storage data in the flash memory 110. During a read operation, the read controller retrieves the stored data from the flash memory 110 and then performs LDPC decoding to obtain the original data.
FIG. 2 is a block diagram of a memory reading apparatus according to an embodiment of the invention.
The memory reading device 121 includes a receiving module 1220, a control unit 1213 and an ecc (error checking and correction) circuit 1211. The control unit 1213 is responsible for logical control of the entire memory control device. The receiving module 1220 is used for receiving data stored in the memory unit. The ECC circuit 1211 acquires data stored in the memory cell from the receiving module 1220, and performs data error correction processing. As described above, the default voltage of the memory cell 1110 of the flash memory 110 may be changed due to some factors, such as read disturb, write/program disturb, and/or save disturb, which may cause the read data to be incorrect, and this may require the ECC circuit to perform error correction processing. A portion of memory cells 1110 in each memory page typically stores ECC codewords. Generally, ECC circuit 1211 is capable of performing error correction processing based on ECC codewords. Specifically, the ECC circuit detects the read data, confirms whether the read data is correct, and thereby detects the presence of erroneous data. When error data is detected, the error data included in the read-out is corrected by a corrector. However, when the amount of error data present exceeds the maximum amount that the ECC circuitry can correct, the ECC circuitry will identify error data that cannot be corrected. At this time, the control unit 1213 will invoke the voltage adjustment module 1212 to adjust the detection voltage.
The voltage adjustment module 1212 includes a reading unit 12121, a calculation unit 12122, a determination unit 12123, and a bias generation unit 12124. The reading unit 12121 is configured to read data from the receiving module, and the calculating unit 12122 is configured to perform calculation to obtain a plurality of disparity values, where the disparity values represent data variation amounts of two adjacent reading operations. For example, after each read operation, the number of memory cells whose data is a bit value "0" is counted, and then the number of memory cells whose data is a bit value "0" of the last read operation is subtracted, and the absolute value of the difference is taken as the difference value. Or after each reading operation, counting the number of memory cells of which the data is a bit value of "1", and then subtracting the number of memory cells of which the data of the last reading operation is a bit value of "1", and taking the absolute value of the difference as the difference value. The determination unit 12123 is used for determining the range of the optimal detection voltage and the optimal detection voltage (best sensing voltage) according to the difference value. Specifically, when the voltage adjustment module starts to operate, the offset generation unit 12124 performs offset based on the default voltage to generate a plurality of detection voltages, the control unit applies the detection voltages to the memory cells respectively, the reading unit 12121 reads data in the corresponding memory cells directly or indirectly, and the calculation unit 12122 performs multiple times of statistics to obtain a plurality of difference values. The determination unit 12123 determines the optimum detection voltage from the plurality of difference values. The finally determined optimal detection voltage is stored in a certain static storage space of the memory controller so as to facilitate data reading operation at a later date.
The reading control method calculates the data variation in multiple reading operations under different detection voltages, and determines the optimal detection voltage based on the data variation. Since the amount of change in data in the plurality of read operations is due to different bias voltages, an optimum bias voltage and a corresponding optimum detection voltage can be found based on the amount of change.
FIG. 3 is a schematic structural diagram of a voltage adjustment module of a memory reading apparatus according to a first embodiment.
Referring to fig. 3, the voltage adjustment module 1212 includes a reading unit 12121, a calculating unit 12122, a first determining unit 121231, and a first bias generating unit 121241. The first bias generation unit 121241 is used to uniformly bias, obtaining a plurality of detection voltages, each detection voltage being equal to the sum of the default voltage and the bias voltage, which are applied to the memory cell for multiple reads of data. The reading unit 12121 is used to read data from the receiving module. The calculation unit 12122 performs addition statistical calculation based on the data read each time. The calculation unit 12122 may be an adder for the accumulation calculation. The first determination unit 121231 is used to determine the optimum detection voltage based on the statistical calculation result.
Specifically, when the voltage adjustment module 1212 operates, the first offset generation unit 121241 generates a first detection voltage value, in this example, a unit offset of a fixed value is adopted, and each offset is an integer multiple of the unit offset. For example, if the default voltage is 2.10E-0.3V and the unit offset is 0.1E-0.3V, the first offset is one unit offset to obtain a detection voltage of 2.20E-0.3V. The control unit 1213 applies a detection voltage corresponding to the detection voltage value to each memory cell to perform a read operation. The reading unit 12121 reads data from the receiving module. The calculation unit 12122 performs a counting operation based on the read data to finally obtain an accumulated value. For example, the number of memory cells with data of "1" is counted, so that an accumulated value sum1 is obtained. Then, a second detected voltage value is generated, which may be generated based on the default voltage and the double unit offset. For example, based on the previous example, an offset of 2 x 0.1E-0.3V results in a detected voltage value of 2.30E-0.3V. The control unit 1213 applies a detection voltage corresponding to the detection voltage value to each memory cell to read data stored in each memory cell and store the data in the storage device. The calculation unit 12122 obtains data from the storage device, and performs a counting operation based on the data value to obtain an accumulated value. For example, the number of memory cells with data of "1" is counted, so that an accumulated value sum2 is obtained, and then the absolute values of sum2-sum1 are calculated to obtain a difference value. And so on until obtaining a plurality of difference values. The final first determination unit 121231 determines the detection voltage corresponding to the minimum difference value as the optimum detection voltage.
Fig. 4 is a diagram illustrating statistical results of the voltage adjustment module according to the first embodiment.
In fig. 4, V0 to V23 represent the detection voltages after being biased, and the bar graph represents the number of memory cells having the same data at the detection voltages. In this example, the detection voltages V0-V23 are obtained based on uniform shifts of the default voltages, each of which is shifted by an equal amount. The default voltage may be obtained by shifting in both positive and negative directions, for example, assuming that the default voltage is the middle value of V9 in the above figure, V0-V8 and V10-V23 are obtained by shifting in positive or negative directions. It should be noted that uniform shifting does not mean that only one unit shift amount can be shifted at a time, but a plurality of unit shift amounts can be shifted at a time. For example, the default voltage is 2.10E-0.3V, the unit offset is 0.1E-0.3V, 2.20E-0.3V is obtained by positively offsetting one unit offset, 2.00E-0.3V is obtained by negatively offsetting one unit offset, 2.30E-0.3V is obtained by positively offsetting two unit offsets, 1.90E-0.3V is obtained by negatively offsetting two unit offsets, and the like. The unit offset is related to the default voltage and the number of memory cells. In real-world operation, different unit offsets are determined according to the default voltage of the memory cell.
It should be noted that, since one memory cell can store data of a plurality of bits, one memory cell can have a plurality of default voltages, and thus the above steps can be performed on the basis of each default voltage to find an optimal detection voltage corresponding to each default voltage. Finally, a plurality of optimal detection voltages of the memory cell at a time are obtained.
In this embodiment, the default voltage is uniformly shifted to obtain a plurality of detection voltage values, and the reading operation is performed based on the detection voltage values to obtain a plurality of difference values, so as to determine the optimal detection voltage. Since the offset is a fixed value every time, if a large detection voltage is reached, the offset must be performed multiple times and data reading operations must be performed multiple times, which results in a long execution time and a reduced user experience.
FIG. 5 is a diagram illustrating a second embodiment of a voltage adjustment module of a memory reading apparatus.
In fig. 5, the voltage adjustment module 1212 includes a reading module 12121, a calculation unit 12122, a second determination unit 12417, and a second bias generation unit 12416. The second bias generation unit 12416 is configured to obtain a plurality of detection voltages in a non-uniform bias manner, each detection voltage being equal to a sum of a default voltage and a bias voltage, the plurality of detection voltages being applied to the memory cell for a plurality of reads of data. The calculating unit 12122 is configured to read data from the receiving module, and calculate a disparity value according to the data read each time to obtain a plurality of disparity values. The second determining unit 12417 is configured to perform estimation according to the difference value, and determine an optimal detection voltage interval and an optimal detection voltage.
Specifically, when a read operation is performed, a first detection voltage value is first generated by the second bias generation unit 12416, and the detection voltage value is generated based on a default sensing voltage (default sensing voltage), a multiple value, and a unit offset. For example, if the default voltage is 2.10E-0.3V, the unit offset is 0.1E-0.3V, and the multiplier is 1, the detection voltage value is 2.20E-0.3V. The control unit 1213 applies the detection voltages to the respective memory cells to perform a data read operation. The computing unit 12122 obtains data from the receiving module and performs a counting operation to obtain an accumulated value. Then, a second detection voltage value is generated according to the second bias generation unit 12416. For example, based on the previous example, with a unit offset of 0.1E-0.3V and a multiplier set to 5, a detected voltage value of 2.10E-0.3V +5 x 0.1E-0.3V-2.6E-0.3V is obtained. The control unit 1213 applies a detection voltage corresponding to the detection voltage value to each memory cell to read data. The calculating unit 12122 obtains data from the receiving module, performs a counting operation to obtain an accumulated value, and subtracts the accumulated value of the two reading operations to obtain an absolute value, thereby obtaining a difference value. And so on until obtaining a plurality of difference values. The second determining unit 12417 calculates an average value according to the difference value and the number of unit offsets included in the corresponding detection voltage interval, and obtains an optimal detection voltage in the detection voltage interval corresponding to the minimum average value, for a subsequent data reading operation of the flash memory.
The second determination unit 12417 is specifically described in a bar chart shown in fig. 6. Fig. 6 is a diagram illustrating statistical results of the voltage adjustment module according to the second embodiment.
As shown in fig. 6, the sensing voltages V0-V5 and V18-V23 each correspond to a numerical range of one unit offset, while V9, V14 and V17 each correspond to a numerical range of a plurality of unit offsets, respectively, V6-V9, V10-V14 and V15-V17, and the bar graphs show the respective corresponding difference values.
Based on the second embodiment, the second determining unit 12417 needs to calculate the average value first, that is, the average value corresponding to V9 is Sum' 1/4 ═ 111/4 ═ 27; v14 corresponds to an average of Sum' 2/5-84/5-17; the average value for V17 is Sum' 3/4-125/3-31. Then, the detection voltage interval in which the minimum average value is located is found as the interval in which the optimum detection voltage is located. The minimum average value is 17, it is judged that the optimum detection voltage should fall within the detection voltage interval of V10-V14. In an alternative embodiment, a Full voltage scanning or explosion force method may be performed in the interval to search for the optimal detection voltage. The full voltage scanning method means that as many values as possible are selected as the detection voltage in the interval to be tested so as to obtain the optimal detection voltage. For example, the interval is divided into a plurality of sub-intervals, and a test is performed with the boundary value of each sub-interval as a detection voltage to approximate to an optimum detection voltage.
In another alternative embodiment, a weighted interpolation (voltage prediction by cyclic interpolation) method may be used to estimate the optimal detection voltage. For example, an estimated value is first obtained by using the following formula:
where v2 represents the minimum average value, start (v2) represents the left boundary value of the detection voltage interval in which the minimum average value is located, length (v2) represents the number of unit offsets included in the detection voltage interval in which the minimum average value is located, and v1 and v3 represent the average values corresponding to the adjacent detection voltage intervals, respectively.
Substituting the correlation value into the above equation according to the example of fig. 6 finally obtains:
the estimated value V' is 10+5 × 27/(27+42) 11.95.
Then, based on the estimated value V', an optimum detection voltage is determined. For example, if the optimal detection voltage is determined to be V11 or V12 in the above example, V11 or V12 may be selected as the optimal detection voltage.
FIG. 7 is a flowchart illustrating a read control method of a flash memory according to an embodiment of the present invention.
The sequence of the steps in the flowchart is an exemplary embodiment of the present invention, but is for illustrative purposes only and is not limited thereto. Flowchart 700 includes the following steps.
In step 701, a plurality of detected voltage values are acquired. The plurality of detection voltage values are obtained by default voltage offset, and may be uniformly offset, for example, offset by one unit offset amount at a time, or non-uniformly offset, and the number of unit offset amounts at each offset is not limited.
In step 702, a plurality of detection voltages are applied to the memory cells of the flash memory according to a plurality of detection voltage values, respectively, to perform a plurality of data read operations. The specific sense voltage applied to which memory cells is determined here by the default voltage.
In step 703, a plurality of difference values are obtained. The difference value represents the data variation of two adjacent reading operations.
In step 704, an optimal detection voltage is determined according to the plurality of difference values.
In step 705, the optimal detection voltage is stored for a subsequent data read operation of the flash memory. The optimum detection voltage is used for a subsequent data read operation to reduce the amount of erroneous data read from the flash memory.
In a further embodiment, a plurality of detection voltage values are obtained in a non-uniform offset manner, an average value is calculated according to the counted number of memory cells with the same data, a value interval in which the optimal detection voltage is located is judged according to the average value, and the optimal detection voltage is finally determined. The offset times are reduced in a non-uniform manner to save execution time.
The reading control method of the flash memory is suitable for correcting the detection voltage of the flash memory after a period of time. As operations of reading, writing, and storing the flash memory increase, the default voltage of the memory cell changes, resulting in an increase in the error amount of data read based on the default voltage, and further resulting in the inability of the ECC circuit to correct the data read from the flash memory. The reading control method of the invention can obtain the optimal detection voltage and update the default voltage stored in the memory based on the optimal detection voltage so as to better perform data reading operation.
Fig. 8 is a comparison graph of the decoding effect of the ECC circuit after the adjustment method of the detection voltage provided by the prior art and the present invention is adopted.
Fig. 8 is a comparison graph of the decoding effect of the ECC circuit after the adjustment method of the detection voltage provided by the prior art and the present invention is adopted. Wherein, the X-axis represents the data amount of Error correction decoded by the ECC circuit, the Y-axis represents the Error data amount (Error Bits) decoded by the ECC circuit, X1 represents the effect diagram of the prior art, and X2 represents the effect diagram after the detection voltage adjustment of the present invention. It can be seen that the amount of erroneous data is significantly reduced after the detection voltage is adjusted. For example, a point a on X1 and a point B on X2 each correspond to a coordinate point on the X axis of greater than 14.8K, and the ratio of the error data amounts is approximately 6: 1.
Although the preferred embodiments of the present invention have been disclosed in the foregoing description, it should be understood that they are not intended to limit the scope of the claims appended hereto, and that various changes and modifications may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A read control method of a flash memory, wherein the flash memory includes a plurality of memory cells, each of the memory cells having at least one default voltage, the method comprising:
acquiring a plurality of detection voltage values, wherein each detection voltage value is equal to the sum of default voltage and bias voltage, and the bias voltage is equal to integral multiple of unit offset;
applying a plurality of detection voltages to the memory cells of the flash memory according to the plurality of detection voltage values, respectively, to perform a plurality of data read operations;
obtaining a plurality of difference values, wherein the difference values represent the data variation of two adjacent reading operations;
determining an optimal detection voltage according to the plurality of difference values;
and
storing the optimal detection voltage for a subsequent data read operation of the flash memory,
wherein the determining an optimal detection voltage according to the plurality of disparity values comprises:
calculating a plurality of average values according to the plurality of difference values, wherein the average value is the number of unit offsets contained in the difference value obtained by each reading operation divided by the corresponding detection voltage value interval;
comparing the plurality of average values; and
and obtaining the optimal detection voltage in the detection voltage value interval corresponding to the minimum average value.
2. The read control method of claim 1, wherein the plurality of detection voltage values are obtained based on a default voltage uniform bias.
3. The read control method of claim 1, wherein the plurality of detection voltage values are obtained based on a default voltage non-uniform bias.
4. The read control method according to claim 1, wherein a full voltage scan is performed between detection voltage values corresponding to the minimum average value to obtain the optimal detection voltage.
5. The read control method of claim 1, wherein obtaining the optimal detection voltage within a detection voltage value interval corresponding to a minimum average value comprises:
the estimated value is calculated by the following formula,
wherein v2 represents the minimum average value, start (v2) represents the start value of the numerical interval in which the minimum average value is located, length (v2) represents the number of unit offsets contained in the detection voltage value interval corresponding to the minimum average value, and v1 and v3 represent the average values corresponding to two detection voltage values adjacent to the minimum average value, respectively; and
and judging the optimal detection voltage according to the estimated value.
6. The read control method of claim 1, wherein the unit offset is related to a default voltage.
7. The read control method of claim 1, further comprising: the read control method of claim 1 is performed when the ECC module cannot correct data read from the flash memory or the ECC module determines that the error rate exceeds a certain threshold.
8. A memory reading device for reading data in a flash memory, wherein the flash memory comprises a plurality of memory cells, each of the memory cells has at least a default voltage, the memory reading device comprises a voltage adjustment module and a control unit,
the voltage adjustment module includes:
an offset generating unit for acquiring a plurality of detection voltage values, each detection voltage value being equal to a sum of a default voltage and an offset voltage, the offset voltages being equal to integer multiples of a unit offset amount;
the reading unit executes data reading operation for multiple times according to the detection voltage values respectively;
the calculating unit is used for obtaining a plurality of difference values, and the difference values represent the data variation of two adjacent reading operations;
a determination unit configured to determine an optimal detection voltage according to the plurality of difference values;
the control unit is used for controlling the starting and the closing of the voltage adjusting module and applying a plurality of detection voltages to a part of memory cells of the flash memory according to the detection voltage values,
wherein the determination unit includes: and calculating a plurality of average values according to the plurality of difference values, and obtaining the optimal detection voltage in the detection voltage value interval corresponding to the minimum average value, wherein the average value is the difference value obtained by each reading operation divided by the number of unit offsets contained in the corresponding detection voltage value interval.
9. The memory reading device according to claim 8, wherein the bias generation unit includes a first bias generation unit configured to obtain the plurality of detection voltage values based on a default voltage uniform bias.
10. The memory reading device of claim 8, wherein the bias generation unit comprises a second bias generation unit to obtain the plurality of detection voltage values based on a default voltage non-uniform bias.
11. The memory reading device according to claim 8, wherein the determination unit includes:
the estimated value is calculated by the following formula,
wherein v2 represents the minimum average value, start (v2) represents the start value of the numerical interval in which the minimum average value is located, length (v2) represents the number of unit offsets contained in the detection voltage value interval corresponding to the minimum average value, and v1 and v3 represent the average values corresponding to two detection voltage values adjacent to the minimum average value, respectively; and
and judging the optimal detection voltage according to the estimated value.
12. The memory read device of claim 8, wherein the unit offset is related to a default voltage.
13. The memory reading device of claim 8, further comprising: and the control unit starts the voltage adjusting module when the ECC circuit cannot correct the data read from the flash memory or the ECC module judges that the error rate exceeds a specific threshold value.
14. A memory system includes a flash memory including a plurality of memory cells, and each of the memory cells having at least a default voltage,
the memory system further comprises a memory controller, the memory controller further comprising the memory reading apparatus of any one of claims 8 to 13.
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| CN110189788A (en) * | 2019-04-24 | 2019-08-30 | 深圳市金泰克半导体有限公司 | The read voltage of flash memory determines method, apparatus, computer equipment and storage medium |
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| CN113223593B (en) * | 2021-04-23 | 2023-04-11 | 联芸科技(杭州)股份有限公司 | Method for optimizing reading voltage of memory cell, controller of 3D memory and operation method thereof |
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