TWI690929B - Memory apparatus and method for adjusting reading reference voltage thereof - Google Patents

Abstract

A memory apparatus and a method for adjusting reading reference voltage thereof are provided. The method includes: obtaining a plurality counting numbers of memory cells which are set to a setting logic level, where the counting numbers are respectively correspond to a plurality of reading steps; calculating a plurality of counting difference values according to the counting number, generating an average difference value according to the counting difference values, and generating a threshold value according to the average difference value; calculating a balance counting value of the memory cells; respectively obtaining a first reference counting value and second reference counting value according to a first reading step and a second reading step, and calculating a reference counting difference value; and, setting a voltage adjusting value according to the reference counting difference value, the threshold value, and the balance counting value, and adjusting the reading reference voltage to generate an adjusted reading reference voltage according to the voltage adjusting value.

Description

Memory device and adjustment method for reading reference voltage

The invention relates to a memory device and an adjustment method for reading a reference voltage, and particularly relates to a memory device and an adjustment method for dynamically adjusting the reading reference voltage.

In the technical field of flash memory, in order to determine the logical level of the data stored in the memory cell, one or more read reference voltages need to be set, and the threshold voltage of the memory cell and the read reference voltage Compare to determine the logical level of the data stored in the memory cell. However, after the flash memory has been used for a longer period of time, the characteristics of the memory cell may change after repeated programming/erasing cycles or long-term data storage. In this way, the memory cell will drift according to the characteristics of the threshold voltage presented by the stored data. Under such conditions, using the originally set reading reference voltage to perform the data reading operation of the memory cell will result in the situation where the reading data is incorrect.

The invention provides a memory device and a method for adjusting the reading reference voltage, which can improve the accuracy of reading data.

The method for adjusting the reading reference voltage of the present invention includes: performing a plurality of reading steps of reading steps on a plurality of memory cells of the memory, and obtaining a plurality of count values for the memory cells with set logic levels, respectively The values correspond to the reading steps respectively; multiple count differences are calculated based on the count value, an average difference is generated based on the count difference, and a critical value is generated based on the average difference; the balance count value of the memory cell is calculated, where balance The count value is equal to the number of memory cells programmed to set the logic level; the first reading step and the second reading step are set according to the reading reference voltage to obtain the first reference of the memory cell setting the logic level, respectively The count value and the second reference count value, and calculate the reference count difference between the first reference count value and the second reference count value; and, according to the reference count difference value, the threshold value, and the balance count value to set the voltage adjustment value, and The read reference voltage is adjusted according to the voltage adjustment value to generate the adjusted reference voltage.

The memory device of the present invention includes a memory, a memory controller, and a host. The memory controller is coupled to the memory. The host is coupled to the memory controller. The host is used to: perform multiple reading steps for multiple memory cells of the memory, and obtain multiple count values of the memory cells with set logic levels respectively, and the count values respectively correspond to the reading steps Calculate multiple count differences based on the count value, generate an average difference based on the count difference, and generate a critical value based on the average difference; calculate the balance count value of the memory cell, where the balance count value is equal to the memory cell is programmed Into the number of set logic levels. The memory controller is used to set the first reading step and the second reading step according to the reading reference voltage, respectively obtain the first reference count value and the second reference count value of the memory cell for setting the logic level, and calculate Generating a reference count difference between the first reference count value and the second reference count value; and, setting the voltage adjustment value according to the reference count difference value, the threshold value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value The adjusted reference voltage is generated.

Based on the above, the present invention calculates the change state of multiple count values corresponding to multiple reading steps in the memory cell, and distinguishes three distribution areas according to the change state of the count value. By calculating the distribution area where the current reading reference voltage is located, and adjusting the voltage value of the reading reference voltage accordingly, the accuracy of the extracted data is improved.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Please refer to FIG. 1, which is a flowchart of an adjustment method for reading a reference voltage according to an embodiment of the present invention. The method for adjusting the reading reference voltage in FIG. 1 is suitable for the reading operation of the memory. In this embodiment, the memory may be a non-volatile memory, such as flash memory. In FIG. 1, step S110 performs a plurality of reading steps on a plurality of memory cells of the memory, and obtains a plurality of count values for a memory cell with a set logic level, wherein the count values are respectively Corresponding to the above multiple reading steps. Please refer to FIG. 1 and FIG. 2A at the same time. FIG. 2A is a graph showing the relationship between the count value and the reading step according to an embodiment of the present invention. In this embodiment, the logic level is set to logic level 1, for example. The reading step corresponds to reading the reference voltage. For example, the first reading step may correspond to the reading reference voltage equal to the first voltage value, and the second reading step may correspond to the second voltage. The reference voltage of the value is read, wherein the second voltage value is greater than the first voltage value, and the second voltage value may be equal to the first voltage value by one step value dV. By analogy, the number of reading steps can increase as the reading reference voltage increases, and the voltage value of the reading reference voltage corresponding to the nth reading step can be equal to the first voltage value + (n -1) × dV.

By sequentially increasing the reading steps, the reading operation is performed on the memory cells in the memory, and by calculating the corresponding multiple reading steps, the data stored in the memory cells is read as the logic level 1 For each count value, the curve 210 shown in FIG. 2A can be obtained. Among them, the curve 210 is a continuously increasing curve, and in the zones Z21 and Z22, the curve 210 has a relatively large rising slope.

Please refer to FIG. 1 again. In step S120, a plurality of count differences are calculated according to the count value in step S110, an average difference is generated according to the count difference, and a threshold value is generated based on the average difference. In detail, a subtraction action is performed on the two count values corresponding to the adjacent two reading steps, and the absolute value is taken to obtain multiple count difference values. The count difference is used to reflect the changing state of the count value. Then, all the difference counts are added up, and the totaled result is divided by the total number of reading steps to produce an average difference. In addition, the average difference is multiplied by a constant k to generate a critical value, where the constant k is a preset value and is a real number greater than 1.

Please refer to FIG. 1, FIG. 2A and FIG. 2B simultaneously. FIG. 2B is a graph showing the relationship between the count difference and the reading step according to an embodiment of the present invention. In FIG. 2B, a plurality of count differences constitute a curve 220. The threshold value TH can be generated by summing all the count differences, dividing the total result by the total number of reading steps to generate an average difference, and multiplying the average difference by a constant k. In FIG. 2B, by comparing the threshold value TH with a plurality of count differences in the curve 220, the reading steps RS1, RS2 can be obtained, and the reading steps RS1, RS2 can be divided into all the reading steps Three distribution areas A, B, C. Among them, the reading step of the distribution area A is smaller than the reading step RS1; the reading step of the distribution area B is between the reading steps RS1 and RS2; and, the reading step of the distribution area C is larger than the reading step Order RS2.

It is worth noting that in FIG. 2B, there are regions Z21A and Z22A corresponding to the regions Z21 and Z22 in FIG. 2A, respectively. Among them, the regions Z21 and Z22 in FIG. 2A with relatively large count values correspond to the regions Z21A and Z22A in FIG. 2B with relatively large count differences.

Following the above description, step S130 calculates a balance count value of the memory cell, where the balance count value is equal to the number of memory cells programmed to set a logic level (eg, logic level 1). Taking a memory cell with 16K bytes as a van Lee, when half of the memory cells are programmed to logical level 1, the balance count value is equal to 16384 × 8/2 = 65536.

Next, in step S140, the first reading step and the second reading step are set according to the reading reference voltage, and the memory cells are set as the logic level according to the first reading step and the second reading step, respectively. The first reference count value and the second reference count value, and calculate the reference count difference between the first reference count value and the second reference count value. Please refer to FIG. 1, FIG. 3A and FIG. 3B simultaneously. FIG. 3A and FIG. 3B are schematic diagrams illustrating the adjustment operation of the reference voltage according to an embodiment of the invention. In FIG. 3A, the first reference count value Cn and the second reference count value Cn+1 of the memory cell for setting the logic level are obtained by the first reading step RRS1 and the second reading step RRS2, respectively . In this embodiment, the first reference count value Cn and the second reference count value Cn+1 are 73370 and 70580, respectively. Moreover, by subtracting the first reference count value Cn and the second reference count value Cn+1 and taking the absolute value thereof, the reference count difference value dn = 2750 can be obtained.

Next, step S150 sets a voltage adjustment value according to the reference count difference dn, the threshold value TH, and the balance count value B, and adjusts the read reference voltage according to the voltage adjustment value to generate the adjusted reference voltage. Continuing with the embodiments of FIGS. 3A and 3B, where the average value is equal to 1000, the constant k is equal to 2, the number of steps of the first reading step is equal to 2, and the balance count value B is equal to 65536, the threshold value TH can be Equal to 1000 × 2 = 2000. In this way, the reference count difference dn (=2750) is greater than the threshold TH, and the difference (B-Cn) between the balance count B and the first reference count Cn is greater than the threshold and the step of the first reading step The product of the order (n × TH) indicates that the currently set reading step falls in the area A or the area C (in this embodiment, it falls in the area A). Therefore, the difference between the balance count value B and the first reference count value Cn can be divided by the average difference value dn to obtain the voltage adjustment value, and the read reference voltage RV can be adjusted according to the calculated voltage adjustment value to generate the adjusted read Take the reference voltage TRV.

It can be found from the drawing of FIG. 3B that, through the adjustment operation of reading the reference voltage, the adjusted reading reference voltage TRV can fall in the center of the curve to improve the accuracy of reading the data.

Please refer to FIGS. 4A and 4B here. 4A and 4B are schematic diagrams illustrating another implementation manner of the reference voltage adjustment operation according to an embodiment of the present invention. In FIG. 4A, the first reference count value Cn and the second reference count value Cn+1 of the memory cell for setting the logic level are obtained by the first reading step RRS1 and the second reading step RRS2, respectively . In this embodiment, the first reference count value Cn and the second reference count value Cn+1 are 68680 and 67340, respectively. Moreover, by subtracting the first reference count value Cn and the second reference count value Cn+1 and taking the absolute value thereof, the reference count difference value dn=1340 can be obtained. Based on that the reference count difference dn is less than the critical value TH (=2000), it indicates that the currently set reading step falls in area B. Therefore, the difference between the balance count value B and the first reference count value Cn can be divided by the reference count difference value dn to obtain the voltage adjustment value, and the read reference voltage RV can be adjusted according to the calculated voltage adjustment value to generate the adjustment Read the reference voltage TRV.

Please refer to FIG. 5, which is a schematic diagram of a memory device according to an embodiment of the invention. The memory device 500 includes a memory 512, a memory controller 511, and a host 520. The memory controller 511 is coupled to the memory 512 and can be integrated into a memory card 510. The host terminal 513 is connected to the memory card 510 and is coupled to the memory controller 511. In this embodiment, the host 513 can be used to perform steps S110-S130 as shown in the embodiment of FIG. 1 to obtain the average difference value, the threshold value, and the balance count value. The memory controller 511 can be used to execute steps S140-S150 shown in the embodiment of FIG. 1 to perform the adjustment operation of the reference read voltage.

Regarding the implementation details of the above steps S110-S150, detailed descriptions have been given in the foregoing embodiments, and will not be repeated here.

Incidentally, the host 513 may be a computer device, or any electronic device with computing capability. The host 513 can be used to connect to the memory card 510 and obtain information such as average difference, threshold, and balance count. The host 513 can also store information such as the average difference value, the threshold value, and the balance count value in the memory card 510. Under the condition that the host 513 and the memory card 510 are offline (not connected), the memory card controller 511 can adjust the reading reference voltage during the reading operation of the value memory 512 to maintain the correctness of the read data Sex.

Please refer to FIG. 6, which is a schematic diagram illustrating the operation of the method for reading the reference voltage according to an embodiment of the present invention. In conjunction with the memory device 500 of FIG. 5, in step S610, the host 513 can perform initialization settings by executing steps S110-S130, and obtain the balance count value B and the average difference Avg. Next, when a data reading operation is performed on the memory 512, an error checking and correction (ECC) check operation of step S620 may be performed. When the ECC check is passed, the data reading operation can be continued. When the ECC check fails, the tracking process can be performed through step S630. Here, the tracking process of step S630 can be performed through steps S140-S150, and the read reference voltage can be adjusted accordingly.

Through the tracking process of step S630, the reading reference voltage can be adjusted adaptively, and the accuracy of data reading can be maintained to improve the use efficiency of the memory.

In summary, the present invention performs the adjustment operation of reading the reference voltage by calculating the change states of the multiple count values corresponding to the multiple reading steps. In this way, when the characteristics of the memory cell change, the corresponding reading reference voltage can still be effectively set to improve the accuracy of reading data.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

S110~S150, S610~S630: Adjustment steps for reading reference voltage 210, 220: curve Z21, Z22, Z21A, Z22A: area RS1, RS2, RRS1, RRS2: read step A, B, C: distribution area Cn, Cn+1: reference count value TH: critical value RV: read reference voltage TRV: Read the reference voltage after adjustment 500: memory device 512: memory 511: memory controller 520: Host side 510: memory card

FIG. 1 is a flowchart of an adjustment method for reading a reference voltage according to an embodiment of the invention. FIG. 2A is a graph showing the relationship between the count value and the reading step according to an embodiment of the invention. FIG. 2B is a graph showing the relationship between the count difference and the reading step according to an embodiment of the invention. FIG. 3A and FIG. 3B are schematic diagrams illustrating the adjustment operation of the reference voltage according to an embodiment of the invention. 4A and 4B are schematic diagrams illustrating another implementation manner of the reference voltage adjustment operation according to an embodiment of the present invention. 5 is a schematic diagram of a memory device according to an embodiment of the invention. FIG. 6 is a schematic diagram illustrating the operation of the read reference voltage adjustment method according to an embodiment of the invention.

S110~S150: Adjustment steps for reading reference voltage

Claims (11)

An adjustment method for reading a reference voltage is applicable to a memory, including: performing a plurality of reading steps for a plurality of memory cells of the memory, and respectively obtaining a memory cell with a set logic level A plurality of count values corresponding to the reading steps; based on the count values, a plurality of count difference values are calculated, based on the count difference values, an average difference value is generated, and based on the average value The difference is used to generate a critical value; a balance count value of the memory cells is calculated, wherein the balance count value is equal to the number of memory cells programmed to the set logic level; a first reference is set according to a read reference voltage A reading step and a second reading step, respectively obtaining a first reference count value and a second reference count value of the memory cell for which the logic level is set, and calculating the first reference count value and A reference count difference of the second reference count value; and setting a voltage adjustment value according to the reference count difference value, the threshold value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value After generating an adjustment, the reference voltage is read. The method for adjusting the read reference voltage as described in item 1 of the patent application scope, wherein the set logic level is logic level 1. The adjustment method for reading a reference voltage as described in item 1 of the patent application scope, wherein the step of setting the voltage adjustment value according to the reference count difference, the threshold value and the balance count value includes: When the reference count difference is greater than the critical value, and the difference between the balance count value and the first reference count value is greater than the product of the critical value and the number of steps of the first reading step, the balance The difference between the value and the first reference count value is divided by the average difference to obtain the voltage adjustment value; and when the difference between the reference count value and the threshold value is less than the critical value, the balance count value and the first reference count value The difference is divided by the reference count difference to obtain the voltage adjustment value. The method for adjusting the reading reference voltage as described in item 1 of the patent application scope, wherein the step of calculating the count difference based on the count values includes: calculating the second count value corresponding to the adjacent reading step Difference to obtain the difference between the counts. The adjustment method for reading a reference voltage as described in item 1 of the patent application scope, wherein the step of generating the threshold based on the average difference includes: multiplying the average difference by a constant to generate the threshold, wherein This constant is a real number greater than 1. The adjustment method for reading the reference voltage as described in item 1 of the patent application scope, wherein the balance count value is half of the total number of the memory cells. A memory device includes a memory; a memory controller coupled to the memory; and a host terminal coupled to the memory controller, wherein the host terminal is used to: Perform multiple reading steps of reading steps on the plurality of memory cells of the memory, and obtain a plurality of count values of a memory cell with a set logic level, and the count values respectively correspond to the reading steps Calculate multiple count differences based on the count values, generate an average difference based on the count differences, and generate a critical value based on the average difference; and calculate a balance of the memory cells Count value, wherein the balance count value is equal to the number of the memory cells programmed into the set logic level; the memory controller is used to: set a first reading step and a second according to a reading reference voltage Read the steps to obtain a first reference count value and a second reference count value for the memory cell of the set logic level, and calculate a reference for the first reference count value and the second reference count value Counting difference; and setting a voltage adjustment value according to the reference counting difference, the threshold value and the balance count value, and adjusting the read reference voltage according to the voltage adjustment value to generate an adjusted reference voltage. The memory device as described in item 7 of the patent application range, wherein the set logic level is logic level 1. The memory device as described in item 7 of the patent application range, wherein the memory controller is further used to: when the reference count difference is greater than the critical value, and the difference between the balance count value and the first reference count value Multiplied by the threshold value and the number of steps of the first reading step During the product, the difference between the balance count value and the first reference count value is divided by the average difference value to obtain the voltage adjustment value; and when the reference count difference value is less than the critical value, the balance count value is equal to The difference between the first reference count value is divided by the reference count difference to obtain the voltage adjustment value. The memory device as described in item 7 of the patent application range, wherein the host end is further used to: calculate a difference between two count values corresponding to adjacent reading steps to obtain each count difference. The memory device as described in item 7 of the patent application range, wherein the host side is further used to: multiply the average difference by a constant to generate the critical value, wherein the constant is a real number greater than 1; and to balance the The count value is equal to half of the total number of memory cells.

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