CN111799186A - Method for bonding chip to wafer and wafer with chip - Google Patents
Method for bonding chip to wafer and wafer with chip Download PDFInfo
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- CN111799186A CN111799186A CN202010679712.6A CN202010679712A CN111799186A CN 111799186 A CN111799186 A CN 111799186A CN 202010679712 A CN202010679712 A CN 202010679712A CN 111799186 A CN111799186 A CN 111799186A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Abstract
The invention provides a method for attaching chips to a wafer and the wafer with the chips. The method comprises the following steps: providing a first alignment pattern on at least one chip, the first alignment pattern including at least one criss-cross-shaped protrusion/recess; arranging a second alignment graph on a wafer, wherein the second alignment graph comprises at least one concave/convex corresponding to the first alignment graph; and taking the first alignment pattern and the second alignment pattern as alignment marks to attach the chip to the wafer. The invention can improve the manufacturing precision.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for attaching chips to a wafer and the wafer with the chips.
Background
With the increasing integration level of integrated circuits, three-dimensional integrated circuit technology has gained more and more attention. The logic circuit is cut into chips and attached to a whole wafer with a memory circuit in a patch mode to form a finished memory, which is a common packaging form in the prior art. The packaging form has high requirement on the alignment between the logic circuit chip and the memory wafer, and the prior art can only achieve the alignment precision of tens of microns and can not meet the packaging requirement.
Therefore, how to improve the alignment accuracy between the chip and the wafer in the process of bonding the chip to the wafer is a problem to be solved in the prior art.
Disclosure of Invention
The invention aims to provide a method for bonding a chip and a wafer, which can improve the precision between the chip and the wafer.
In order to solve the above problems, the present invention provides a method for bonding a chip and a wafer, comprising the following steps: providing a first alignment pattern on at least one chip, the first alignment pattern including at least one criss-cross-shaped protrusion/recess; arranging a second alignment graph on a wafer, wherein the second alignment graph comprises at least one concave/convex corresponding to the first alignment graph; and taking the first alignment pattern and the second alignment pattern as alignment marks to attach the chip to the wafer.
Optionally, the chip is a logic circuit chip, and the wafer is a memory wafer.
Optionally, the first alignment pattern and the second alignment pattern are in a shape of a Chinese character 'jing'.
Optionally, a plurality of second alignment patterns are disposed on the wafer, so that a plurality of chips can be attached to each other.
Optionally, the first alignment pattern is disposed in a nitride or oxide layer on the surface of the chip, the recess depth/protrusion height is 0.5-50 μm, the second alignment pattern is disposed in the nitride or oxide layer on the surface of the wafer, and the recess depth/protrusion height is 0.5-50 μm.
The invention also provides a wafer pasted with a chip, wherein the chip is provided with a first alignment pattern, and the first alignment pattern comprises at least one criss-cross-shaped bulge/recess; a second alignment pattern is arranged on the wafer, and the second alignment pattern comprises at least one concave/convex corresponding to the first alignment pattern; the first alignment pattern and the second alignment pattern are aligned to overlap each other.
Optionally, the chip is a logic circuit chip, and the wafer is a memory wafer.
Optionally, the first alignment pattern and the second alignment pattern are in a shape of a Chinese character 'jing'.
Optionally, the wafer has a plurality of second alignment patterns and is attached with a plurality of chips, and each chip is provided with a first alignment pattern on which the second alignment patterns are overlapped and aligned with each other.
Optionally, the first alignment pattern is disposed in a nitride or oxide layer on the surface of the chip, the recess depth/protrusion height is 0.5-50 μm, the second alignment pattern is disposed in the nitride or oxide layer on the surface of the wafer, and the recess depth/protrusion height is 0.5-50 μm.
The invention improves the alignment precision by arranging the first alignment graph of the concave/convex on the chip and arranging the corresponding convex/concave on the wafer.
Drawings
Fig. 1 is a schematic diagram illustrating an implementation procedure of a bonding method between a chip and a wafer according to an embodiment of the present invention.
FIGS. 2A-2C are schematic process diagrams of the steps illustrated in FIG. 1.
Fig. 3 is a schematic diagram illustrating an implementation procedure of a bonding method between a chip and a wafer according to an embodiment of the present invention.
FIGS. 4A-4C are schematic process diagrams illustrating the steps of FIG. 3.
Detailed Description
The following describes a method for bonding chips to a wafer and a wafer with chips according to embodiments of the present invention in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating an implementation procedure of a bonding method between a chip and a wafer according to an embodiment of the present invention. In the present embodiment, the chip is a logic circuit chip, and the wafer is a memory wafer. Attaching logic circuit chips to a memory wafer is a typical process scenario for chip-to-wafer attachment. Of course, the methods described in this and the following embodiments are also applicable to other types of die and wafer bonding, and various common alternatives to die and wafer types should be considered as the scope of the present invention.
As shown in fig. 1, the method comprises the following steps: step S10, arranging a first alignment pattern on at least one chip, wherein the first alignment pattern is a cross-shaped protrusion; step S11, disposing a second alignment pattern on the wafer, wherein the second alignment pattern includes at least one recess corresponding to the first alignment pattern; and step S12, using the first alignment pattern and the second alignment pattern as alignment marks, and attaching the chip to the wafer.
FIGS. 2A to 2C are schematic views of the above steps.
Referring to step S10, as shown in fig. 2A, a first alignment pattern 201 is provided on the chip 20, the first alignment pattern 201 being a cross-shaped projection. In the present embodiment, the number of the chips 20 is 5 as an example. In other embodiments, the number of chips 20 can be arbitrarily set. While the present embodiment has been described with reference to a cross-shaped projection, in other embodiments, a cross-shaped recess may be used instead of a projection as the alignment. In the present embodiment, as a preferable technical solution, an oxide layer 203 is formed on the surface of the chip 20, and the first alignment pattern 201 is disposed on the oxide layer 203 on the surface. In other embodiments, the oxide layer 203 may be a nitride layer. The first alignment pattern 201 preferably has a protrusion height at a longitudinal distance of 0.5 to 50 μm from the surface.
Referring to step S11, as shown in fig. 2B, a second alignment pattern 302 is disposed on the wafer 30, wherein the second alignment pattern 302 includes at least one recess corresponding to the cross-shaped protrusion on the wafer 30. Since the first alignment pattern 201 is convex, the corresponding second alignment pattern 302 is concave. Conversely, in the embodiment where the cross shape on the chip 20 is concave, the corresponding protrusion on the wafer is replaced by a cross shape. In this embodiment, as a preferred technical solution, an oxide layer 303 is formed on the surface of the wafer 30, and the second alignment pattern 302 is disposed in the oxide layer 303 on the surface. In other embodiments, the oxide layer 303 may be a nitride layer. The depth of the recess of the second alignment pattern 302 is preferably 0.5 to 50 μm in a longitudinal distance from the surface.
Referring to step S12, referring to fig. 2C, the first alignment pattern 201 and the second alignment pattern 302 are used as alignment marks to attach the chip 20 to the wafer 30. Since the first alignment pattern 201 is formed in advance on the chip 20 and the second alignment pattern 302 is formed in advance on the wafer 30, the alignment accuracy between the two can be improved in this step.
The surface of the wafer 30 obtained after the above steps is completed has a plurality of bonded chips 20, the chips 20 have first alignment patterns 201, and the first alignment patterns 201 are cross-shaped protrusions; the wafer 30 has a second alignment pattern 302, and the second alignment pattern 302 is a recess corresponding to the first alignment pattern 201; the first alignment pattern 201 and the second alignment pattern 302 are aligned to overlap each other.
Fig. 3 is a schematic diagram illustrating an implementation procedure of a bonding method between a chip and a wafer according to an embodiment of the present invention. The method comprises the following steps: step S30, providing a first alignment pattern on at least one chip, wherein the first alignment pattern is a well-shaped recess; step S31, disposing a second alignment pattern on the wafer, wherein the second alignment pattern includes at least one protrusion corresponding to the first alignment pattern; and step S32, using the first alignment pattern and the second alignment pattern as alignment marks, and attaching the chip to the wafer.
FIGS. 4A to 4C are schematic views of the above steps.
As shown in fig. 4A, referring to step S30, a first alignment pattern 401 is provided on the chip 40, the first alignment pattern 401 being a well-shaped recess. This shape can be seen as a mosaic combination of four cross shapes. In the present embodiment, the number of the chips 40 is 5 as an example. In other embodiments, the number of the chips 40 can be arbitrarily set. The present embodiment is described by taking a well-shaped recess as an example, and in other embodiments, a well-shaped protrusion may be used instead of a recess as the alignment. In this embodiment, as a preferable technical solution, an oxide layer 403 is formed on the surface of the chip 40, and the first alignment pattern 401 is disposed in the oxide layer 403 on the surface. In other embodiments, the oxide layer 403 may also be a nitride layer. The longitudinal distance from the surface to the depth of the depression of the first alignment pattern 401 is preferably 0.5 to 50 μm.
Referring to step S31, as shown in fig. 4B, a second alignment pattern 502 is disposed on the wafer 50, wherein the second alignment pattern 502 includes at least one protrusion corresponding to the cross-shaped recess on the wafer 40. Since the first alignment pattern 401 is a recess, the corresponding second alignment pattern 502 is a protrusion. In contrast, in the embodiment where the cross shape on the chip 40 is a protrusion, the corresponding recess on the wafer is replaced by a cross shape. In this embodiment, as a preferred technical solution, an oxide layer 503 is formed on the surface of the wafer 50, and the second alignment pattern 502 is disposed on the oxide layer 303 on the surface. In other embodiments, the oxide layer 503 may also be a nitride layer. The second alignment pattern 502 preferably has a protrusion height at a longitudinal distance of 0.5 to 50 μm from the surface.
Referring to step S32, referring to fig. 4C, the first alignment pattern 401 and the second alignment pattern 502 are used as alignment marks to attach the chip 40 to the wafer 50. Since the first alignment pattern 401 is previously formed on the chip 40 and the second alignment pattern 502 is previously formed on the wafer 50, the alignment accuracy between the two can be improved in this step.
The surface of the wafer 50 obtained after the above steps is completed has a plurality of bonded chips 40, the chips 40 have a first alignment pattern 401, and the first alignment pattern 401 is a well-shaped recess; the wafer 50 has a second alignment pattern 502, where the second alignment pattern 502 is a protrusion corresponding to the first alignment pattern 401; the first alignment pattern 401 and the second alignment pattern 502 are aligned to overlap each other.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for bonding a chip and a wafer is characterized by comprising the following steps:
providing a first alignment pattern on at least one chip, the first alignment pattern including at least one criss-cross-shaped protrusion/recess;
arranging a second alignment graph on a wafer, wherein the second alignment graph comprises at least one concave/convex corresponding to the first alignment graph;
and taking the first alignment pattern and the second alignment pattern as alignment marks to attach the chip to the wafer.
2. The method of claim 1, wherein the die is a logic die and the wafer is a memory wafer.
3. The method of claim 1, wherein the first and second alignment patterns are well-shaped.
4. The method of claim 1, wherein a plurality of second alignment patterns are disposed on the wafer for attaching a plurality of chips.
5. The method as claimed in claim 1, wherein the first alignment pattern is provided in a nitride or oxide layer on the surface of the chip with a recess depth/protrusion height of 0.5-50 μm, and the second alignment pattern is provided in a nitride or oxide layer on the surface of the wafer with a recess depth/protrusion height of 0.5-50 μm.
6. A wafer pasted with chips is characterized in that:
the chip is provided with a first alignment pattern, and the first alignment pattern comprises at least one criss-cross-shaped protrusion/recess;
a second alignment pattern is arranged on the wafer, and the second alignment pattern comprises at least one concave/convex corresponding to the first alignment pattern;
the first alignment pattern and the second alignment pattern are aligned to overlap each other.
7. The wafer of claim 6, wherein the chips are logic circuit chips and the wafer is a memory wafer.
8. The wafer of claim 6, wherein the first and second alignment patterns are well-shaped.
9. The wafer of claim 6, wherein the wafer has a plurality of second alignment patterns and is attached with a plurality of chips, each of the chips is disposed on the first alignment patterns aligned with the second alignment patterns in an overlapping manner.
10. The wafer of claim 6, wherein the first alignment pattern is disposed in the nitride or oxide layer on the surface of the chip and has a recess depth/protrusion height of 0.5-50 μm, and the second alignment pattern is disposed in the nitride or oxide layer on the surface of the wafer and has a recess depth/protrusion height of 0.5-50 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010679712.6A CN111799186A (en) | 2020-07-15 | 2020-07-15 | Method for bonding chip to wafer and wafer with chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010679712.6A CN111799186A (en) | 2020-07-15 | 2020-07-15 | Method for bonding chip to wafer and wafer with chip |
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| CN111799186A true CN111799186A (en) | 2020-10-20 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235245A (en) * | 2003-01-28 | 2004-08-19 | Denso Corp | Method of manufacturing semiconductor device |
| JP2005026467A (en) * | 2003-07-02 | 2005-01-27 | Sumitomo Heavy Ind Ltd | Stage device and electronic beam proximity exposure system |
| US20110233706A1 (en) * | 2010-03-23 | 2011-09-29 | Samsung Electronics Co., Ltd. | Method For Wafer Level Package and Semiconductor Device Fabricated Using The Same |
| CN107706120A (en) * | 2017-09-28 | 2018-02-16 | 深圳赛意法微电子有限公司 | The method for packing of ultra-thin wafers |
| CN110600414A (en) * | 2019-08-01 | 2019-12-20 | 中国科学院微电子研究所 | Wafer heterogeneous alignment method and device |
| CN110896025A (en) * | 2019-10-28 | 2020-03-20 | 芯盟科技有限公司 | Wafer bonding method and bonded wafer |
-
2020
- 2020-07-15 CN CN202010679712.6A patent/CN111799186A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235245A (en) * | 2003-01-28 | 2004-08-19 | Denso Corp | Method of manufacturing semiconductor device |
| JP2005026467A (en) * | 2003-07-02 | 2005-01-27 | Sumitomo Heavy Ind Ltd | Stage device and electronic beam proximity exposure system |
| US20110233706A1 (en) * | 2010-03-23 | 2011-09-29 | Samsung Electronics Co., Ltd. | Method For Wafer Level Package and Semiconductor Device Fabricated Using The Same |
| CN107706120A (en) * | 2017-09-28 | 2018-02-16 | 深圳赛意法微电子有限公司 | The method for packing of ultra-thin wafers |
| CN110600414A (en) * | 2019-08-01 | 2019-12-20 | 中国科学院微电子研究所 | Wafer heterogeneous alignment method and device |
| CN110896025A (en) * | 2019-10-28 | 2020-03-20 | 芯盟科技有限公司 | Wafer bonding method and bonded wafer |
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