CN111799166A - 边缘环移除方法 - Google Patents
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Abstract
本发明题为“边缘环移除方法”。移除边缘支撑环的方法的实施方式可包括:提供半导体晶圆。该半导体晶圆可包括第一侧面和第二侧面。半导体晶圆的第一侧面可包括背金属。半导体晶圆还可包括围绕半导体晶圆的周边的边缘环。该方法可包括将半导体晶圆的第一侧面安装到膜框架。该方法可包括移除边缘支撑环周围的背金属的一部分以及从半导体晶圆分割出边缘支撑环。
Description
相关专利申请的交叉引用
本申请要求授予Seddon的名称为“边缘环移除方法(EDGE RING REMOVALMETHODS)”的美国临时专利申请62/827,968的权益,该申请提交于2019年4月2日,该申请的公开内容据此全文以引用方式并入本文。
技术领域
本文件的方面总体上涉及移除边缘环的方法。更具体的实施方式涉及从半导体晶圆的边缘移除环。
背景技术
半导体器件包括存在于常用电气和电子设备(诸如电话、台式计算机、平板电脑、其他计算设备和其他电子设备)中的集成电路。半导体器件通常形成在半导体衬底上。
发明内容
移除边缘支撑环的方法的实施方式可包括:提供半导体晶圆。该半导体晶圆可包括第一侧面和第二侧面。半导体晶圆的第一侧面可包括背金属。半导体晶圆还可包括围绕半导体晶圆的周边的边缘环。该方法可包括将半导体晶圆的第一侧面安装到膜框架。该方法可包括移除边缘支撑环周围的背金属的一部分以及从半导体晶圆分割出边缘支撑环。
移除边缘支撑环的方法的实施方式可包括以下中的一个、全部或任何一个:
该方法可包括将边缘支撑环暴露于紫外光。
该方法可包括将边缘支撑环提升远离半导体晶圆。
边缘支撑环可包括斜面/倾坡。
晶圆可包括小于50微米的厚度。
该方法可包括将晶圆分割成多个管芯。
移除背金属的一部分可包括锯切和激光处理。
从半导体晶圆分割出边缘支撑环可包括等离子蚀刻和湿法蚀刻。
移除边缘支撑环的方法的实施方式可包括:提供具有第一侧面和第二侧面的半导体晶圆半导体晶圆的第一侧面可包括背金属。该半导体晶圆可包括围绕半导体晶圆的周边的边缘环。该方法可包括将半导体晶圆的第一侧面安装到膜框架。该方法可包括使用锯切移除边缘支撑环周围的背金属的一部分。该方法还可包括在背金属的移除部分处进行等离子蚀刻,以从半导体晶圆分割出边缘支撑环。半导体晶圆可具有小于50微米的厚度。
移除边缘支撑环的方法的实施方式可包括以下中的一个、全部或任何一个:
该方法可进一步包括将与边缘支撑环联接的带暴露于紫外光。
该方法可包括将边缘支撑环提升远离半导体晶圆。
边缘支撑环可包括斜面/倾坡。
该方法还可包括将晶圆分割成多个管芯。
移除边缘支撑环的方法的实施方式可包括:提供具有第一侧面和第二侧面的半导体晶圆半导体晶圆的第一侧面可包括背金属。半导体晶圆可包括围绕半导体晶圆的周边的边缘支撑环。该方法可包括将半导体晶圆的第一侧面安装到膜框架以及移除边缘支撑环周围的背金属的一部分。该方法还可包括在背金属的移除部分处进行锯切,以沿着边缘支撑环的内部部分从半导体晶圆分割出边缘支撑环。
移除边缘支撑环的方法的实施方式可包括以下中的一个、全部或任何一个:
该方法可包括对边缘支撑环和半导体晶圆之间的两个或更多个侧壁进行进一步等离子蚀刻。
半导体晶圆可包括小于50微米的厚度。
该方法可进一步包括将与边缘支撑环联接的带暴露于紫外光。
该方法可进一步包括将边缘支撑环提升远离半导体晶圆。
移除背金属的一部分可包括激光处理、锯切或湿法蚀刻。
边缘支撑环的内部部分可以是倾斜的或不倾斜的中的一个。
对于本领域的普通技术人员而言,通过说明书和附图并且通过权利要求书,上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述实施方式,在附图中类似标号表示类似元件,并且:
图1是具有边缘支撑环的半导体衬底的实施方式的截面视图;
图2是在衬底上的边缘支撑环的实施方式的一部分的截面视图,其示出了用于分割的三个可能位置;
图3是图2的边缘支撑环的实施方式的截面视图,在用于分割的三个可能的位置处移除金属层;
图4是在等离子蚀刻期间在衬底上的图3的边缘支撑环的实施方式的截面视图的示意图;
图5是在衬底上的边缘支撑环的实施方式的一部分的截面视图,其示出了用于分割的三个可能位置;
图6是在等离子蚀刻期间在衬底上的图6的边缘支撑环的实施方式的截面视图的示意图;
图7是在衬底上的边缘支撑环的实施方式的一部分的截面视图,其示出了用于通过激光切割进行分割的三个位置;并且
图8是图7的边缘支撑环的实施方式的截面视图,在用于分割的各个位置处移除金属层。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的与预期边缘环移除方法符合的许多另外的部件、组装工序和/或方法元素将显而易见地能与本公开的特定实施方式一起使用。因此,例如,尽管公开了特定实施方式,此类实施方式和实施部件可包括符合预期操作和方法的本领域已知用于此类边缘环移除方法以及实施部件和方法的任何形状、尺寸、样式、类型、模型、版本、量度、浓度、材料、数量、方法元素、步骤等。
由于封装件的小型化以及对MOSFET器件提高效率的需求,新器件的典型管芯厚度正在不断减小。不断开发出约25um-50um厚的管芯的新技术,以满足行业要求。对于约10um-100um厚的晶圆而言最佳的管芯分割工艺可满足大多数新技术的要求。
参考图1,示出了具有边缘环的衬底2的截面侧视图。术语“衬底”是指半导体衬底,因为半导体衬底是一种常见的衬底类型,然而,“衬底”并非是用于指代所有半导体衬底类型的专门术语。相似地,术语“衬底”可以指晶圆,因为晶圆是常见的衬底类型,然而,“衬底”并非是用于指代所有晶圆的专门术语。作为非限制性示例,本文档中公开的可用于各种实施方式的各种半导体衬底类型,可为圆形的、倒圆的、正方形的、矩形的或任何其他封闭形状。在各种实施方式中,衬底2可包含衬底材料,诸如(作为非限制性示例)单晶硅、二氧化硅、玻璃、砷化镓、蓝宝石、红宝石、绝缘体上硅、碳化硅、多晶或任何前述物质的非晶态,以及可用于构造半导体器件的任何其他衬底材料。在特定实施方式中,该衬底可为绝缘体上硅衬底。
在本文档公开的各种实施方式中,该半导体衬底包括多个半导体管芯,该多个半导体管芯已使用半导体制造工艺进行处理以在半导体衬底中或在半导体衬底上形成一个或多个半导体器件(未示出)。该多个管芯已在半导体衬底的第一侧面4或有源侧面上被处理。这可包括在衬底的第一侧面4上形成多个层。该多个层可被图案化,并且在各种实施方式中,可被图案化(或以其他方式被移除)成不位于衬底中的管芯通道/划线/管芯网格之上。作为非限制性示例,多个层可包括一个或多个金属层、一个或多个钝化层、任何其他层,以及它们的任何组合。在各种实施方式中,多个管芯可包括功率半导体器件,诸如(作为非限制性示例)MOSFET、IGBT或任何其他功率半导体器件。在其他实施方式中,多个管芯可包括非功率半导体器件。
在完成制造工艺之后(或在一些实施方式中,在该制造工艺的一些部分期间),该半导体衬底2在该半导体衬底的一侧面6上减薄至期望衬底厚度,该侧面与其上已形成一个或多个半导体器件的侧面4相反。在各种实施方式中,该减薄工艺可在衬底周围产生边缘环8(像在加利福尼亚州圣克拉拉的迪思科科技美国公司(Disco Hi-Tec America,Inc.,Santa Clara,California)销售的商标名为TAIKO的背面研磨工艺中存在的边缘环)。在各种实施方式中,边缘环8可以是倾斜的边缘环或包括如图所示的斜面10。在其他实施方式中,边缘环可以不倾斜而具有基本上垂直于衬底的变薄表面的边缘。边缘环8用于在减薄之后在结构上支撑衬底,使得在后续处理步骤期间不需要使用载体。在各种实施方式中,在半导体衬底已被安装到背面研磨带之后,可以进行减薄工艺,无论是否在背面研磨期间形成边缘环。在各种实施方式中,可采用各种背面研磨带,包括与后续等离子蚀刻操作兼容的那些背面研磨带。在其他实施方式中,半导体衬底可不联接到背面研磨带。
在各种实施方式中,可将衬底2减薄至小于50微米(μm)的平均厚度。如本文所用,“平均厚度”是指在衬底的最大平坦表面的至少大部分上的衬底平均厚度。在其他实施方式中,可将衬底减薄至小于30μm的平均厚度。在另外其他实施方式中,可将衬底减薄至小于100μm、大于100μm的平均厚度,并且在其他各种实施方式中,该衬底可不被减薄。在特定实施方式中,可将衬底减薄至约25μm的平均厚度,并且在其他特定实施方式中,可将衬底减薄至约75μm的平均厚度。该衬底可通过背面研磨、蚀刻或任何其它减薄技术变薄。
在各种实施方式中,在减薄工艺之后,将金属层施加到该半导体衬底的第二侧面。在一些实施方式中,该金属层可被称为背面金属层或背金属。在各种实施方式中,背金属层可以是铜或铜合金。在一些实施方式中,该金属可包括钨、锡、金、钛、铝、银、镍、铜、铬、它们的合金、或它们的任何组合。在其他实施方式中,该背面金属层可包括任何其他类型的金属、它们的合金、或它们的组合。在各种实施方式中,背侧金属层可为约10μm厚。在其他实施方式中,背侧金属层可厚于10μm或薄于10μm。
对于平均厚度小于40微米的半导体衬底,存在特定的处理挑战。管芯处理、管芯强度以及用管芯和衬底执行处理操作全都存在特定挑战,因为管芯和衬底破损可显著降低产率并且/或者影响器件可靠性。管芯强度受到传统分割选项的负面影响,比如锯切,这引起管芯破碎以及沿着管芯通道的破裂。在锯切工艺期间形成的这些碎片和裂缝最终可在操作和可靠性测试期间传播,从而导致管芯失效。本文描述的方法可用于移除超薄晶圆和较厚晶圆上的边缘支撑环。由于晶圆的内部部分较薄,可能难以将晶圆安装/保持/支撑在用于边缘环移除的磨轮或其他类似的转盘结构上。当晶圆包括背金属时,也难以对环进行等离子蚀刻,背金属包括种子金属或用于焊料附着的金属板。
用于从衬底移除边缘环的各种方法可包括提供具有第一侧面和第二侧面的衬底。参考图2,示出了边缘环18的一部分的截面视图。衬底包括在衬底12的第二侧面16上的背金属14。背金属14可包括铜或本文先前描述的任何金属。移除边缘环18的方法可包括将衬底的第一侧面20安装到带22,该带可以由膜框架(未示出)支撑。在各种实施方式中,膜框架可以由聚苯硫醚、苯乙烯丙烯腈、聚对苯二甲酸乙二醇酯(PETG)、黑色导电聚苯乙烯和其他硬塑料制成。在各种实施方式中,带可以是切割带、拾取胶带或背面研磨带。如图所示,可以通过边缘环18的斜面30背离膜框架而定位衬底。然后,在边缘支撑环周围移除背金属14的一部分。在各种实施方式中,可以使用锯、激光、划刻、蚀刻以及其任意组合或适合于移除衬底上的金属的小部分的其他方法来移除背金属。图2示出了三个可能的位置24、26和28,在这些位置可以从衬底移除背金属,但是对于本公开的目的,这些是非限制性示例,可选择如边缘环上、边缘环外或沿倾斜部分30的其他位置。在图2所示的实施方式中,锯片70用于移除背金属14的部分。尽管图2(并且类似地,图5和图7)示出了三个不同位置,在这些位置,通过锯(或通过激光划刻工具,如图7所示)移除背金属,但是将理解,本文公开的各种实施方式仅包括在所示的三个位置之一(或在与所示的三个位置不同的另一位置)处移除背金属。在各种实施方式中,边缘环18可包括所示的斜坡/斜面30。在各种实施方式中,可通过沿着边缘支撑环的斜坡部分30进行切割来执行晶圆的最佳分割。在其他实施方式中,可以沿着衬底的平坦表面34或在边缘环18的整个厚度部分32中进行移除。在其他变型中,边缘环的面对衬底的变薄部分的面可基本垂直于衬底并且不包括斜面。
参考图3,示出了图2的边缘环的实施方式的截面视图,在用于分割的三个可能位置处移除背金属。如图所示,背金属14包括完全延伸穿过背金属的开口56(或背金属的移除部分)。尽管图3(以及图4、图6和图8)示出了三个不同的开口,但是将理解,这些是开口的可能位置,并且本文公开的方法的各种实施方式仅包括形成所示的开口之一。在各种实施方式中,开口56可延伸到衬底12中。在其他实施方式中,开口56不延伸到衬底12中。
参考图4,示出了在等离子蚀刻36期间边缘环12的实施方式。通过移除背金属有助于等离子蚀刻的使用,这允许等离子化学物质接触衬底材料。如图所示,背金属14在等离子蚀刻工艺期间用作掩模。在各种实施方式中,可以进行等离子蚀刻以确保到蚀刻区域60的侧壁58的向外斜面所示对衬底进行过度蚀刻。然而,在其他实施方式中,可以进行等离子蚀刻以产生直的侧壁或向内倾斜的侧壁。在衬底是硅的各种实施方式中,可以使用由德国的格林根(Gerlingen)的罗伯特·博世公司(Robert Bosch Gmbh)以商标名为BOSCH工艺销售的深反应离子等离子蚀刻工艺来进行蚀刻。在其他实施方式中,可以通过湿法蚀刻对边缘支撑环进行分割。在蚀刻工艺之后,在一些实施方式中,可以将与边缘环联接的带暴露于紫外光以减小带与边缘环的材料之间的粘合力。在各种实施方式中,该方法可进一步包括将边缘环18提升远离衬底12的其余部分。在各种实施方式中,可使用镊子移除边缘环18。在其他实施方式中,可使用机械臂或其他自动化工具移除边缘环18。
在移除边缘环18之后,可执行进一步的处理步骤,诸如将衬底分割成多个管芯。在各种实施方式中,可通过等离子蚀刻、锯切、湿法蚀刻、激光切割、喷射烧蚀、隐形切分和用于分割管芯的其他方法分割管芯。在一些实施方式中,可使用特定于超薄衬底的分割方法。可以从衬底的第一侧面或第二侧面分割管芯。在各种实施方式中,可以在将边缘环从衬底分割的同时将晶圆分割。
参考图5,示出了具有背金属42的半导体晶圆40的一部分的实施方式。如图所示,边缘环44可联接到带46,带可由膜框架(未示出)支撑。晶圆可定位在带上,而边缘环44面向上或远离带。在各种实施方式中,可以通过使用锯48锯切穿过晶圆的背金属42一直到晶圆40的第一侧面50来移除边缘环。在一些实施方式中,可使用如图7所示的激光划片工具来分割边缘环44。
参考图6,示出了锯切后图5的晶圆的实施方式。从晶圆分割边缘环44的方法可进一步包括通过各向同性等离子蚀刻56对边缘支撑环44和半导体晶圆40之间的两个或更多个侧壁62进行远程等离子修复,以移除在蚀刻工艺期间引起的侧壁损坏。在一些实施方式中,在分割之后,晶圆可暴露于紫外光,从而可移除边缘环。在各种实施方式中,该方法可进一步包括将边缘支撑环提升远离晶圆周围。在移除边缘支撑环之后,可执行进一步的处理步骤,诸如管芯分割。在各种实施方式中,可在移除边缘支撑环的同时执行管芯分割。在其他实施方式中,可通过湿法蚀刻分割边缘支撑环和管芯。
参考图7,示出了在衬底上的边缘环的实施方式的一部分的截面视图,其示出了用于通过激光切割进行分割的三个位置。类似于本文公开的其他实施方式,特别是图2所示的实施方式,该方法可包括从衬底66的其余部分移除边缘环52。在各种实施方式中,背金属层64可联接到衬底66。移除边缘环52的方法可包括使用激光划片工具54移除边缘环52。虽然可在图7所示的任何位置处使用激光划片工具54,但是在其他实施方式中,可在其他位置使用激光划片工具移除边缘环52。
参考图8,示出了图7的边缘支撑环的实施方式的截面视图,在用于分割的各个位置处移除金属层。在各种实施方式中,该方法包括使用图7的激光划片工具54形成穿过背金属层64的开口68。如图所示,在各种实施方式中,开口68可部分地延伸到衬底中。在其他实施方式中,可以仅穿过背金属层64形成开口68。在形成穿过背金属层的开口时,可使用本文公开的任何方法移除边缘环52,包括通过图4所示的蚀刻分割边缘环。
尽管本文公开的方法集中于从衬底移除边缘环,但是将理解,衬底可包括和/或联接至未示出的其他元件(诸如在衬底中或上形成的多个半导体器件)。在这样的实施方式中,多个半导体器件可包括功率电子半导体器件或非功率电子半导体器件。在将多个功率器件联接到衬底的实施方式中,功率器件可包括(作为非限制性示例)金属氧化物场效应晶体管(MOSFET)、绝缘栅双极晶体管(IGBT)、二极管、晶闸管、可控硅整流器(SCR)或任何其他类型的功率半导体器件。诸如图像传感器和其他无源电子部件的其它设备可被包括在衬底的材料中或上。
移除边缘支撑环的方法的实施方式可包括将边缘支撑环暴露于紫外光。
移除边缘支撑环的方法的实施方式可包括将边缘支撑环提升远离晶圆。
在移除边缘支撑环的方法的各种实施方式中,边缘支撑环可包括斜面。
边缘支撑环的实施方式可包括将晶圆分割成多个管芯。
在移除边缘支撑环的方法的各种实施方式中,边缘支撑环可以是倾斜的或不倾斜的。
在上面的描述涉及移除边缘支撑环和实施部件、子部件、方法和子方法的方法的特定实施方式的地方,应该明显显而易见的是,在不脱离其实质的情况下可进行许多修改,并且这些实施方式、实施部件、子部件、方法和子方法可应用于移除边缘支撑环的其他方法。
Claims (10)
1.一种移除边缘支撑环的方法,所述方法包括:
提供包括第一侧面和第二侧面的半导体晶圆,所述半导体晶圆的所述第一侧面在其上包括背金属,所述半导体晶圆包括围绕所述半导体晶圆的周边的边缘环;
将所述半导体晶圆的第一侧面安装到膜框架;
移除所述边缘支撑环周围的所述背金属的一部分;以及
从所述半导体晶圆分割出所述边缘支撑环。
2.根据权利要求1所述的方法,其中所述晶圆的厚度小于50微米。
3.根据权利要求1所述的方法,其中移除背金属的所述部分包括锯切和激光处理。
4.根据权利要求1所述的方法,其中从所述半导体晶圆分割出所述边缘支撑环包括等离子蚀刻和湿法蚀刻。
5.一种移除边缘支撑环的方法,所述方法包括:
提供包括第一侧面和第二侧面的半导体晶圆,所述半导体晶圆的所述第一侧面在其上包括背金属,所述半导体晶圆包括围绕所述半导体晶圆的周边的边缘环;
将所述半导体晶圆的第一侧面安装到膜框架;
使用锯切移除所述边缘支撑环周围的所述背金属的一部分;以及
在所述背金属的移除部分处进行等离子蚀刻,以从所述半导体晶圆分割出所述边缘支撑环;
其中所述半导体晶圆包括小于50微米的厚度。
6.根据权利要求5所述的方法,进一步包括将与所述边缘支撑环联接的带暴露于紫外光。
7.一种移除边缘支撑环的方法,所述方法包括:
提供包括第一侧面和第二侧面的半导体晶圆,所述半导体晶圆的所述第一侧面在其上包括背金属,所述半导体晶圆包括围绕所述半导体晶圆的周边的边缘支撑环;
将所述半导体晶圆的第一侧面安装到膜框架;
移除所述边缘支撑环周围的所述背金属的一部分;以及
在所述背金属的移除部分处进行锯切,以沿着所述边缘支撑环的内部部分从所述半导体晶圆分割出所述边缘支撑环。
8.根据权利要求7所述的方法,对所述边缘支撑环和所述半导体晶圆之间的两个或更多个侧壁进一步进行等离子蚀刻。
9.根据权利要求7所述的方法,其中所述半导体晶圆包括小于50微米的厚度。
10.根据权利要求7所述的方法,其中移除所述背金属的一部分包括激光、锯切或湿法蚀刻中的一种。
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US6162702A (en) * | 1999-06-17 | 2000-12-19 | Intersil Corporation | Self-supported ultra thin silicon wafer process |
US7148125B2 (en) * | 2001-12-12 | 2006-12-12 | Denso Corporation | Method for manufacturing semiconductor power device |
US7244663B2 (en) * | 2004-08-31 | 2007-07-17 | Micron Technology, Inc. | Wafer reinforcement structure and methods of fabrication |
JP5111938B2 (ja) * | 2007-05-25 | 2013-01-09 | 日東電工株式会社 | 半導体ウエハの保持方法 |
US8048775B2 (en) * | 2007-07-20 | 2011-11-01 | Alpha And Omega Semiconductor Incorporated | Process of forming ultra thin wafers having an edge support ring |
US8012857B2 (en) * | 2007-08-07 | 2011-09-06 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US8859396B2 (en) * | 2007-08-07 | 2014-10-14 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US7989319B2 (en) * | 2007-08-07 | 2011-08-02 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
JP2009096698A (ja) * | 2007-10-19 | 2009-05-07 | Toshiba Corp | ウェーハ及びその製造方法 |
US8084335B2 (en) * | 2008-07-11 | 2011-12-27 | Semiconductor Components Industries, Llc | Method of thinning a semiconductor wafer using a film frame |
JP2010050416A (ja) * | 2008-08-25 | 2010-03-04 | Toshiba Corp | 半導体装置の製造方法 |
US8292690B2 (en) * | 2008-09-08 | 2012-10-23 | Semiconductor Components Industries, Llc | Thinned semiconductor wafer and method of thinning a semiconductor wafer |
US8062958B2 (en) * | 2009-04-01 | 2011-11-22 | Micron Technology, Inc. | Microelectronic device wafers and methods of manufacturing |
JP5431777B2 (ja) * | 2009-04-20 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20110193200A1 (en) * | 2010-02-09 | 2011-08-11 | Lyne Kevin P | Semiconductor wafer chip scale package test flow and dicing process |
US9099547B2 (en) * | 2011-10-04 | 2015-08-04 | Infineon Technologies Ag | Testing process for semiconductor devices |
US9196534B2 (en) * | 2013-02-24 | 2015-11-24 | Alpha And Omega Semiconductor Incorporated | Method for preparing semiconductor devices applied in flip chip technology |
US9129899B2 (en) * | 2013-07-17 | 2015-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and system for thinning wafer thereof |
JP6366351B2 (ja) * | 2014-05-13 | 2018-08-01 | 株式会社ディスコ | ウェーハの加工方法 |
JP6479532B2 (ja) * | 2015-03-30 | 2019-03-06 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9847258B2 (en) * | 2015-09-30 | 2017-12-19 | Nxp B.V. | Plasma dicing with blade saw patterned underside mask |
US10109475B2 (en) * | 2016-07-29 | 2018-10-23 | Semiconductor Components Industries, Llc | Semiconductor wafer and method of reducing wafer thickness with asymmetric edge support ring encompassing wafer scribe mark |
US10096460B2 (en) * | 2016-08-02 | 2018-10-09 | Semiconductor Components Industries, Llc | Semiconductor wafer and method of wafer thinning using grinding phase and separation phase |
US9793186B1 (en) * | 2016-08-08 | 2017-10-17 | Semiconductor Components Industries, Llc | Semiconductor wafer and method of backside probe testing through opening in film frame |
US9905525B1 (en) * | 2016-08-18 | 2018-02-27 | Semiconductor Components Industries, Llc | Semiconductor wafer and method of ball drop on thin wafer with edge support ring |
US10074611B1 (en) * | 2017-03-08 | 2018-09-11 | Semiconductor Components Industries, Llc | Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die |
DE102018117393A1 (de) * | 2018-07-18 | 2020-01-23 | Infineon Technologies Ag | Auflagetisch, auflagetischbaugruppe,verarbeitungsanordnung und verfahren dafür |
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