CN111796480A - Optical proximity correction method - Google Patents
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- CN111796480A CN111796480A CN201910274318.1A CN201910274318A CN111796480A CN 111796480 A CN111796480 A CN 111796480A CN 201910274318 A CN201910274318 A CN 201910274318A CN 111796480 A CN111796480 A CN 111796480A
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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Abstract
The invention relates to an optical proximity correction method, which is characterized in that an optical proximity correction simulation model is established, photoetching is carried out on front layer graphs with different sizes, data is collected, a correction rule is formulated according to the data, the graph size of a photoetching plate is adjusted according to the correction rule until the graph size formed after the graphs on the photoetching plate are transferred to a wafer is irrelevant to the size of the front layer graph, so that the influence of the front layer graphs with different sizes on the key size of a current layer is improved, the consistency of the key size is improved, and the product performance is stabilized.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an optical proximity correction method.
Background
The integrated circuit manufacturing technology involves very complicated processes, wherein the photolithography technology is an important part of the integrated circuit manufacturing technology, and the quality of the photolithography technology directly determines the performance of the chip.
The photolithography process typically uses exposure and development to pattern a geometric structure on a photoresist layer, and then transfers the pattern on the photomask to the substrate by an etching process. However, in actual operation, the pattern etched on the substrate is not consistent with the pattern size on the photomask, mainly due to OPE (Optical Proximity Effect). In order to eliminate the OPE, the design pattern of the integrated circuit is usually corrected in advance using an OPC (Optical Proximity Correction) method so that the corrected pattern can compensate for the missing part caused by the OPE. Therefore, the photoetching layout after OPC correction can obtain the originally expected circuit structure on the substrate after photoetching. However, the inventor finds that in the process of realizing the traditional technology: the traditional OPC method only corrects the graph of the current layer by positioning the graph of the current layer transferred by photoetching above the structure obtained by etching according to the graph of the previous layer, but the default structures of the layers of the previous layer are consistent, so that the influence of the step formed after the multilayer is overlapped on the current CD cannot be solved.
Disclosure of Invention
Therefore, it is necessary to provide an optical proximity correction method for solving the problem that the conventional OPC method cannot solve the problem that the steps formed after the multi-layer stacking affect the accuracy of the current CD online control.
An optical proximity correction method comprising:
placing the same current layer pattern on the front layer patterns with different sizes for simulation by utilizing an optical proximity correction simulation model to form a first version test pattern, and forming a first version photoetching plate according to the first version test pattern;
according to the first plate photoetching plate, photoetching is carried out on the wafer with the front layer patterns with different sizes to obtain a plurality of groups of different first plate photoetching patterns;
designing a first version correction rule according to the size of the first version photoetching pattern;
forming a second version of photoetching plate according to the first version of correction rules, and verifying whether the second version of photoetching plate meets the correction requirements;
and when the second plate of the photoetching plate meets the correction requirement, publishing photoetching according to the second plate of the photoetching plate.
In one embodiment, the forming a second version of the reticle according to the first version of the correction rule and verifying whether the second version of the reticle meets the correction requirement includes:
correcting the first photolithography mask through the simulation model according to the first version correction rule to form a second version test pattern, and forming a second version photolithography mask according to the second version test pattern;
according to the second plate photoetching plate, photoetching is carried out on the wafer with the front layer patterns with different sizes to obtain a plurality of groups of different second plate photoetching patterns;
and judging whether the size of the second version photoetching pattern meets the correction requirement.
In one embodiment, the simulation model using optical proximity correction further includes, before placing a current layer pattern of the same size on a previous layer pattern of a different size for simulation:
photoetching a wafer by adopting a special photoetching plate so as to transfer the pattern of the special photoetching plate to the wafer to obtain an etched pattern;
acquiring original data of the etched pattern;
and establishing a simulation model of the optical proximity correction according to the original data.
In one embodiment, the raw data includes a line width of the etched pattern.
In one embodiment, the performing lithography on the wafer using the special reticle includes:
acquiring photoetching process conditions, wherein the photoetching process conditions comprise optical parameters of an exposure light path and chemical parameters of an etching process;
and photoetching the wafer by adopting a special photoetching plate according to the photoetching process condition.
In one embodiment, the performing lithography on the wafer with the front layer patterns of different sizes according to the first plate reticle includes:
and photoetching the wafer with the front layer patterns with different sizes according to the photoetching process conditions and the first plate photoetching plate to obtain a plurality of groups of different first plate photoetching patterns.
In one embodiment, the designing a first version of modification rules according to the size of the first version of lithography pattern includes:
acquiring a preset size;
determining the difference value between the size of the first version photoetching pattern and the preset size according to the size of the first version photoetching pattern and the preset size;
and designing a first version of correction rule according to the difference.
In one embodiment, the correcting the first reticle by the simulation model according to the first revision rule includes:
and according to the first version correction rule, widening or indenting the line width on the first version photoetching plate.
In one embodiment, when the size of the second version of the photoetching pattern does not meet the correction requirement, a second version of correction rule is designed according to the size of the second version of the photoetching pattern;
and correcting the second version test pattern through the simulation model according to the second version correction rule until the size of the final version photoetching pattern formed by the photoetching plate corresponding to the corrected test pattern meets the correction requirement.
In one embodiment, the revision requirement includes: and the difference value between the size of the photoetching pattern and the preset size is less than or equal to a preset difference value.
According to the optical proximity correction method, the front layer patterns with different sizes are subjected to photoetching, data are collected, correction rules are formulated, the pattern sizes on the photoetching plate are adjusted according to the correction rules until the patterns on the photoetching plate are transferred to the patterns formed after the wafer, the line widths on the patterns are the same on the front layer patterns with different sizes, and further the influence of the sizes of the front layer patterns on the key sizes of the current layer patterns is eliminated, namely the key sizes of the current layer patterns are irrelevant to the sizes of the front layer patterns, so that the influence of the front layer patterns with different sizes on the key sizes of the current layer patterns is improved, the consistency of the key sizes is improved, and the product performance is stabilized.
Drawings
FIG. 1 is a flowchart of a method for optical proximity correction according to an embodiment of the present application;
FIG. 2A is a line graph of raw data collected by photolithography on previous layer patterns of different sizes for the same current layer pattern according to an embodiment of the present application;
FIG. 2B is a line graph of raw data collected by photolithography on previous layer patterns of different sizes for the same current layer pattern according to an embodiment of the present application;
FIG. 2C is a line graph of raw data collected by lithography on previous layer patterns of different sizes, with the same current layer pattern, according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As described in the background, with the rapid development of Ultra Large Scale Integration (ULSI), integrated circuit fabrication processes become more and more complex and sophisticated. In the key layers of the technology node of 0.13um and below, the CD (Critical Dimension) of the key layers such as TO (active area layer), GT (gate oxide layer) and An (metal connection layer) is getting smaller and smaller, and the CD of some key layers is already close TO or even smaller than the wavelength 248nm of the light wave used in the photolithography process. In the exposure process in the photoetching process, certain deformation and deviation exist between a photoetching pattern obtained on an actual product wafer and a mask pattern due to the interference and diffraction phenomena of light, and the circuit performance and the production yield are directly influenced by the error in the photoetching process. In order to eliminate the error, the design drawing is usually corrected to some extent by using an OPC (optical proximity Correction) method. At a 0.11um or 0.13um technology node, the fluctuation of the nanoscale critical dimension can cause the fluctuation of the critical parameters of the device, and further the performance of the whole product is influenced, wherein the step formed after the multilevel superposition can influence the current layer CD, and especially the influence of the front layer graphic dimension on the current layer critical dimension is large and can not be ignored.
In view of the above problem, referring to fig. 1, an embodiment of the present application provides an optical proximity correction method, including the following steps:
s100: and placing the same current layer pattern on the front layer patterns with different sizes for simulation by using the simulation model of optical proximity correction to form a first version test pattern, and forming a first version photoetching plate according to the first version test pattern.
Before the step, the photoetching process condition is obtained, and then photoetching is carried out on the wafer according to the preset photoetching process condition and the special photoetching plate for establishing the model through processes of gluing, exposing, developing and the like, so that the pattern on the special photoetching plate is transferred to the wafer to obtain a real etching pattern. The method comprises the steps of collecting original data of an etched graph on a wafer, wherein the original data comprises line width, line spacing and the like on the etched graph, and establishing an optical proximity correction simulation model according to the original data, photoetching process conditions and the like. When the simulation model is used for carrying out simulation photoetching, real photoetching process parameters and photoetching process flows can be simulated.
And then, placing the same current layer pattern on the front layer patterns with different sizes by using an optical proximity correction simulation model to simulate to obtain a first version test pattern, and forming a first version photoetching plate according to the first version test pattern. Wherein the first plate reticle and the dedicated reticle may have the same pattern.
S200: and photoetching the wafer with the front layer patterns with different sizes according to the first plate photoetching plate to obtain a plurality of groups of different first plate photoetching patterns.
Wherein, the front layer graph is the graph of the lower layer structure where the current layer graph is located. And photoetching and transferring the current layer of pattern on the structure corresponding to the previous layer of pattern. The semiconductor structure generally includes a multilayer structure, such as a substrate layer, a gate oxide layer, a metal layer, etc., which are sequentially arranged, and if the current layer pattern is the pattern of the gate oxide layer, the previous layer pattern is the pattern of the substrate layer.
And under the same process condition with the preset photoetching process condition, photoetching the wafer with the front layer patterns with different sizes according to the first edition of photoetching plate, thereby obtaining the first edition of photoetching patterns on the front layer patterns with different sizes and researching the influence of the front layer patterns with different sizes on the key size of the current layer.
S300: and designing a first version correction rule according to the size of the first version photoetching pattern.
Specifically, after the first version of the photoetching pattern is obtained, the key sizes of the first version of the photoetching pattern corresponding to the front layer patterns with different sizes are collected. Wherein the critical dimension comprises a line width. And the simulation model acquires a pre-stored preset size, and a first edition correction rule is formulated according to the difference value of the key size and the preset size so as to correct the first edition of the photoetching plate.
S400: and forming a second plate photolithography mask according to the first plate correction rule, and verifying whether the second plate photolithography mask meets the correction requirement.
Specifically, after the first version of the modification rule is determined, the first version of the modification rule needs to be verified. The verification mode is that the simulation model corrects the first version test pattern according to the first version correction rule. In this embodiment, the line width of the first version of test pattern may be widened or retracted according to the difference between the critical dimension and the preset dimension, so as to obtain the second version of test pattern. A second plate reticle is then formed according to the second plate test pattern.
And after the second plate photoetching plate is formed, photoetching is carried out on the wafer with the front layer patterns with different sizes again according to the second photoetching plate so as to obtain a plurality of groups of different second plate photoetching patterns, and the sizes of the second plate photoetching patterns are collected.
And judging whether the second version photoetching plate meets the correction requirement or not, collecting the sizes of the corresponding second version photoetching patterns on the front layer patterns with different sizes, and judging whether the second version photoetching plate meets the correction requirement or not according to the difference value between the size of the second version photoetching pattern and the preset size.
S500: and when the second plate of the photoetching plate meets the correction requirement, publishing photoetching according to the second plate of the photoetching plate.
When the difference value between the size of the second version photoetching pattern corresponding to the front layer patterns with different sizes and the preset size is smaller than the preset difference value, namely the line width on the second version photoetching pattern is irrelevant to the size of the front layer pattern, the second version photoetching plate meets the correction requirement, publication photoetching is carried out according to the second version photoetching plate, meanwhile, the first version correction rule can be determined to be the final version correction rule, and OPC can be assisted for correction.
In the optical proximity correction method provided in the above embodiment, the lithography is performed on the front layers with different sizes, the data is collected, the correction rule is formulated according to the data, and the pattern size on the lithography plate is adjusted according to the correction rule until the pattern size formed after the pattern on the lithography plate is transferred to the wafer is unrelated to the pattern size of the front layer, so that the influence of the pattern size of the front layer on the critical size of the current layer can be eliminated.
In one embodiment, the performing lithography on the front layer patterns with different sizes by using a special reticle specifically comprises: firstly, obtaining photoetching process conditions, and then photoetching front layer patterns with different sizes according to the photoetching process conditions and a special photoetching plate. The photoetching process conditions comprise optical parameters of an exposure light path and chemical parameters of an etching process. The optical parameters of the exposure light path comprise specific parameters such as wavelength and exposure light source, and the chemical parameters of the etching process comprise specific parameters such as chemical properties of the etchant. The photolithography process conditions may also include parameters such as the material of the photoresist.
In one embodiment, when the simulation size of the second version of simulation pattern does not meet the correction requirement, the second version of correction rule is designed according to the difference between the size of the second version of lithography pattern and the preset size. And correcting the second version test pattern through the simulation model of optical proximity correction according to a second version correction rule until the size of the pattern obtained by etching the photoetching plate corresponding to the corrected test pattern meets the correction requirement. And judging whether the simulated dimension on the simulated pattern meets the correction requirement, namely judging whether the difference value between the dimension on the photoetching pattern obtained by etching the front layer patterns with different dimensions and the preset dimension is smaller than the preset difference value. If the line width difference is smaller than the preset difference value, publishing photoetching can be carried out according to the photoetching plate. If the line width difference is larger than the preset value, the correction requirement is not met, the correction rule needs to be continuously adjusted according to the size of the photoetching pattern obtained by the last photoetching until the adjusted photoetching plate meets the correction requirement.
The optical proximity correction method provided by the above embodiment is to perform photolithography on substrates with different dimensions, collect data and make a correction rule, adjust the dimension of the pattern on the photolithography mask according to the correction rule until the dimension of the pattern formed after the pattern on the photolithography mask is transferred to the wafer is independent of the dimension of the pattern on the previous layer, so as to improve the influence of the patterns on the previous layer with different dimensions on the key dimension of the pattern on the current layer, improve the consistency of the key dimension, and stabilize the product performance.
Referring to fig. 2A, fig. 2A is a line graph of raw data collected by photolithography on previous layer patterns of different sizes for the same current layer pattern. In this embodiment, the current layer pattern is a gate metal layer, and the current layer pattern is designed as a photolithography mask, and the line width on the photolithography mask is 130 nm. The front layer pattern is an active region pattern on the substrate. The horizontal axis is the size of the active area along a certain direction, and the vertical axis is the line width of an etched pattern etched on the active area according to the photoetching plate. In the figure, a shot1, a shot2 and a shot3 are respectively line width change curves obtained by etching lines with the same line width at different positions on a photoetching plate, and ave is the average line width of three line widths, namely a shot1, a shot2 and a shot 3. It can be seen from the data in the figure that the difference between the maximum value of the average line width and the minimum value of the average line width is 8nm, and the preset size is 5nm, when the line width difference exceeds 5nm, the photolithography mask needs to be corrected.
In actual production, the line spacing has the same influence on the line width, so that the sampling range of original data can be expanded, and the change condition of the line width along with the size of an active area under the condition of different line spacings can be detected. As shown in fig. 2B and 2C. Fig. 2B shows line width data obtained by etching active regions of different sizes when the line width on the reticle is 130nm and the line spacing and the average line width are 450 nm. In the figure, shot1, shot2 and shot3 are line widths obtained by etching lines with the same line width at different positions of the photoetching plate respectively, and ave is the average line width of three line widths. As can be seen from the data in the figure, the difference between the maximum value of the average line width and the minimum value of the average line width is 7.8nm, the preset size is 3nm, the line width difference exceeds the standard control line, and the photolithography mask needs to be corrected.
Fig. 2C shows line width data obtained by etching active regions of different sizes when the photolithography mask has a line width of 130nm and a line spacing and a line width mean of 275 nm. In the figure, shot1, shot2 and shot3 are line widths obtained by etching lines with the same line width at different positions respectively, and ave is an average value of the three line widths. As can be seen from the data in the figure, the difference between the maximum value of the average line width and the minimum value of the average line width is 7.7nm, and the preset size is 3 nm. The line width difference exceeds the standard control line, and the photolithography mask needs to be corrected. The embodiment may also collect original data obtained by etching other line widths on active regions with different sizes, for example, the etching condition on active regions with different sizes when the line width is 140nm, so as to expand the sampling range and facilitate obtaining the data rule, which is not illustrated in the embodiment.
After the data are collected, a first version correction rule can be formulated according to the difference between the data and a preset value, and the photoetching version of the current layer of graph is adjusted for the first time through an optical proximity correction simulation model according to the first version correction rule. And photoetching the adjusted photoetching plate on active area patterns with different sizes to obtain photoetching patterns, and collecting the sizes of the photoetching patterns. And judging whether the difference between the line width on each photoetching pattern and the preset size is smaller than the corresponding preset difference, and if so, carrying out photoetching publication according to the photoetching plate. And if the difference value is larger than the corresponding preset difference value, correcting the photoetching plate again according to the collected data until the line widths obtained by etching the same line width on the active regions with different sizes under the condition of different line spacing meet the requirements, and then formulating a final plate correction rule to assist OPC correction.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An optical proximity correction method, comprising:
placing the same current layer pattern on the front layer patterns with different sizes for simulation by utilizing an optical proximity correction simulation model to form a first version test pattern, and forming a first version photoetching plate according to the first version test pattern;
according to the first plate photoetching plate, photoetching is carried out on the wafer with the front layer patterns with different sizes to obtain a plurality of groups of different first plate photoetching patterns;
designing a first version correction rule according to the size of the first version photoetching pattern;
forming a second version of photoetching plate according to the first version of correction rules, and verifying whether the second version of photoetching plate meets the correction requirements;
and when the second plate of the photoetching plate meets the correction requirement, publishing photoetching according to the second plate of the photoetching plate.
2. The method of claim 1, wherein the forming a second reticle according to the first reticle correction rule and verifying that the second reticle satisfies the correction requirement comprises:
correcting the first photolithography mask through the simulation model according to the first version correction rule to form a second version test pattern, and forming a second version photolithography mask according to the second version test pattern;
according to the second plate photoetching plate, photoetching is carried out on the wafer with the front layer patterns with different sizes to obtain a plurality of groups of different second plate photoetching patterns;
and judging whether the size of the second version photoetching pattern meets the correction requirement.
3. The method of claim 1, wherein the using the simulation model for optical proximity correction before the simulation of placing the current layer pattern with the same size on the previous layer patterns with different sizes further comprises:
photoetching a wafer by adopting a special photoetching plate so as to transfer the pattern of the special photoetching plate to the wafer to obtain an etched pattern;
acquiring original data of the etched pattern;
and establishing a simulation model of the optical proximity correction according to the original data.
4. The method of claim 3, wherein the raw data includes a line width of the etched pattern.
5. The method of claim 4, wherein the performing lithography on the wafer using the special reticle comprises:
acquiring photoetching process conditions, wherein the photoetching process conditions comprise optical parameters of an exposure light path and chemical parameters of an etching process;
and photoetching the wafer by adopting a special photoetching plate according to the photoetching process condition.
6. The method of claim 5, wherein the performing lithography on wafers having different sizes of front layer patterns according to the first reticle comprises:
and photoetching the wafer with the front layer patterns with different sizes according to the photoetching process conditions and the first plate photoetching plate to obtain a plurality of groups of different first plate photoetching patterns.
7. The method according to claim 1, wherein the designing a first version of the correction rules according to the size of the first version of the lithographic pattern comprises:
acquiring a preset size;
determining the difference value between the size of the first version photoetching pattern and the preset size according to the size of the first version photoetching pattern and the preset size;
and designing a first version of correction rule according to the difference.
8. The method of claim 2, wherein the modifying the first reticle with the simulation model according to the first reticle modification rule comprises:
and according to the first version correction rule, widening or indenting the line width on the first version photoetching plate.
9. The method according to claim 2, wherein when the size of the second version of the lithographic pattern does not meet the correction requirement, a second version of the correction rule is designed according to the size of the second version of the lithographic pattern;
and correcting the second version test pattern through the simulation model according to the second version correction rule until the size of the final version photoetching pattern formed by the photoetching plate corresponding to the corrected test pattern meets the correction requirement.
10. The optical proximity correction method according to claim 9, wherein the correction requirement comprises: and the difference value between the size of the photoetching pattern and the preset size is less than or equal to a preset difference value.
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| CN102103324A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity effect correction method |
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