CN111796213B - Detection circuit and method for electrical loop integrity and breakpoint positioning - Google Patents
Detection circuit and method for electrical loop integrity and breakpoint positioning Download PDFInfo
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- CN111796213B CN111796213B CN202010660969.7A CN202010660969A CN111796213B CN 111796213 B CN111796213 B CN 111796213B CN 202010660969 A CN202010660969 A CN 202010660969A CN 111796213 B CN111796213 B CN 111796213B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/56—Testing of electric apparatus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
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Abstract
The invention discloses aThe detection circuit comprises a reference voltage input end, a detection voltage output end, an amplifier, first to fourth resistors, and 1 st to fourth resistorsnLinkage module, the firstiThe linkage module comprises the firsti‑1 to 1i‑4 resistance, the firstiAnd a logic linkage switch. The detection method comprises the steps of obtaining a detection voltage mapping table of the breakpoint position and the detection voltage of the high-voltage component according to a detection circuit for the integrity and the breakpoint positioning of the electric loop, obtaining a detection voltage value of a detection voltage output end at the current moment, converting the detection voltage value into an ADC value, searching a range where the ADC value is located in the mapping table, and determining whether the range belongs to an ADC range corresponding to the disconnection of a high-voltage interlocking interface or an ADC range corresponding to the loosening of the high-voltage interlocking interface. The invention solves the problems of electric loop on-off state detection, multipoint breakpoint positioning detection and contact loosening detection, and has simple realization, economy and reliability.
Description
Technical Field
The invention relates to a circuit and a method for detecting the integrity of an electric loop and locating a breakpoint, and belongs to the technical field of connection of high-voltage components (connectors), linkage state confirmation and locating of the breakpoint.
Background
One of the risk points of high-voltage systems of electric automobiles is sudden power failure, and the automobiles lose power. There are several reasons for the possibility of losing power of the automobile, one of which is that the high-voltage loop is automatically released. The high-voltage interlocking can monitor the sign and provide alarm information for the controller before high-voltage power failure, and the time for the whole vehicle system to take countermeasures is reserved. Another risk point of electric vehicles is manual misoperation, and in the working process of the system, the high-voltage connection point is manually disconnected. If no high voltage interlock design is present, the whole loop voltage is applied across the break point at the moment of disconnection, which is very dangerous for devices such as high voltage connectors that do not have breaking capacity themselves. The voltage breakdown air draws an arc between the two devices, which time, although short, can be very high, can cause injury to personnel and equipment around the breakpoint. The high-voltage interlocking design has two factors to consider, one is how the low-voltage system comprehensively detects the connection state of each connection position of the whole high-voltage system; another problem is how to implement the information transfer action of the low-voltage detection circuit must precede the action of the disconnection of the high-voltage circuit. The high voltage interlock principle therefore requires consideration of both the overall circuit design principle and the connector design principle itself. High Voltage Interlock (HVIL) a safe design method for monitoring the integrity of a high voltage circuit with a low voltage signal. In theory, the low voltage monitoring circuit is turned on after the high voltage, and is turned off first, and the necessary advance must be maintained, for example, 150ms (displacement difference between the high voltage contact and the low voltage contact). The electrical components that require HVIL functionality are mainly high voltage connectors, manual service switches (MSDs).
The traditional level type high-voltage interlocking or PWM type high-voltage interlocking is changed, the on-off state can be detected only, or a detection interface is added to locate the break point. The break-make state cannot be detected and the break point cannot be located.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the circuit and the method for detecting the integrity and breakpoint positioning of the electric loop solve the problems of detection of the on-off state of the electric loop, multipoint breakpoint positioning detection and contact looseness detection.
The invention adopts the following technical scheme for solving the technical problems:
a detection circuit for electrical loop integrity and breakpoint positioning, wherein the electrical loop comprises 1 st to nth high-voltage components, the ith high-voltage components comprise an ith high-voltage interlocking interface, the detection circuit comprises a reference voltage input end, a detection voltage output end, an amplifier, first to fourth resistors and 1 st to nth linkage modules, the ith linkage modules comprise i-1 to i-4 th resistors and an ith logic linkage switch, and i=1, …, n;
one end of the ith logic linkage switch is connected with the reference voltage input end, and the other end of the ith logic linkage switch is respectively connected with one end of the third resistor, one end of the fourth resistor and the ground; the other end of the third resistor is connected with one end of the second resistor after being sequentially connected with the 1 st high-voltage interlocking interface to the n high-voltage interlocking interface in series; the other end of the second resistor is connected with the detection voltage output end through the first resistor, the other end of the second resistor is also connected with the negative phase input end of the amplifier, the output end of the amplifier is connected with the detection voltage output end, and the positive phase input end of the amplifier is grounded; the other end of the fourth resistor is sequentially connected with the 1 st resistor, the 2 nd resistor, the 3 rd resistor, the 2 nd resistor, the … …, the n-1 st resistor and the n-2 nd resistor in series and then connected with one end of the second resistor; one end of the ith-2 resistor connected with the (i+1) -1 th resistor and one end of the ith high-voltage interlocking interface connected with the (i+1) -1-th high-voltage interlocking interface are respectively connected with one end of the ith-3 resistor, and one end of the ith-2 resistor connected with the (i-1) -1-th resistor is connected with one end of the (i-4) -1, i=1, … and n-1; one end of the n-2 resistor connected with the second resistor and one end of the n high-voltage interlocking interface connected with the second resistor are respectively connected with one end of the n-3 resistor, and one end of the n-2 resistor connected with the n-1 resistor is connected with one end of the n-4 resistor; the other end of the ith resistor-3 and the other end of the ith resistor-4 are respectively connected with the linkage end of the ith logic linkage switch, i=1, … and n;
when the ith high-voltage interlocking interface is closed, one end and the other end of the corresponding ith logic linkage switch are both closed, and when the ith high-voltage interlocking interface is opened, one end and the other end of the corresponding ith logic linkage switch are both opened.
The detection method of the detection circuit based on the electrical loop integrity and breakpoint positioning comprises the following steps:
the 1 st to nth high voltage interlocking interfaces are all closed, namely, one end and the other end of an ith logic linkage switch corresponding to the ith high voltage interlocking interface are all 1, a detection voltage value of a detection voltage output end at the moment is obtained, the detection voltage value is converted into an ADC value through analog-to-digital conversion, the values of one end and the other end of each logic linkage switch and the ADC value are recorded in a mapping table, i=1, …, n are all 1 group of data;
one of the 1 st to the n th high-voltage interlocking interfaces is selected to be disconnected, namely one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interface are both valued to be 0, and the other high-voltage interlocking interfaces are all closedCombining, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating an ADC range corresponding to the disconnection of one high-voltage interlocking interface and an ADC range corresponding to the loosening of the high-voltage interlocking interface according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value, the ADC range corresponding to the disconnection of one high-voltage interlocking interface and the ADC range corresponding to the loosening in a mapping table, and sharing
Group data;
selecting two of the 1 st to nth high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interface is 0, the other high-voltage interlocking interfaces are closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating the corresponding ADC range when the two high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC range when the two high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values and the ADC ranges in a mapping table together
Group data;
selecting three high-voltage interlocking interfaces from 1 st to n-th high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interfaces are all 0, other high-voltage interlocking interfaces are all closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating the corresponding ADC range when the three high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC range when the three high-voltage interlocking interfaces are disconnected in a mapping table, and sharing
Group data;
……
selecting 1 st to nth high voltage interlocking interfaces, wherein n-1 th high voltage interlocking interfaces are disconnected, namely, one end and the other end of a logic linkage switch corresponding to the disconnected high voltage interlocking interfaces are all 0, other high voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating an ADC range corresponding to the disconnection of the n-1 th high voltage interlocking interfaces according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the ADC range corresponding to the disconnection of the n-1 high voltage interlocking interfaces in a mapping table, and sharing
Group data; />
The 1 st to nth high voltage interlocking interfaces are all disconnected, namely, one end and the other end of an ith logic interlocking switch corresponding to the ith high voltage interlocking interface are both taken as 0, the detection voltage value of the detection voltage output end at the moment is obtained, the detection voltage value is converted into an ADC value through analog-to-digital conversion, the ADC ranges corresponding to the disconnection of the n high voltage interlocking interfaces are calculated according to the ADC value, the value taken by one end and the other end of each logic interlocking switch, the ADC value and the ADC range corresponding to the disconnection of the n high voltage interlocking interfaces are recorded in a mapping table, and the two are together
Group data;
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
the invention connects the HVIL interfaces of the high-voltage components in series through the single shielding wire, detects the change of the voltage of the distribution point to realize the positioning of faults, and has the advantages of economy, reliability and simple realization. The method can simultaneously realize loop integrity detection of the high-voltage plug-in and the low-voltage plug-in, provide scene identification support for vehicle interlocking faults and provide a quick channel for after-sales problem investigation.
Drawings
FIG. 1 is a schematic diagram of an electrical circuit integrity and breakpoint positioning detection circuit according to the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
As shown in fig. 1, the electrical circuit comprises 1 st to nth high voltage components, the ith high voltage component comprises an ith high voltage interlocking interface, the detection circuit comprises a reference voltage input end, a detection voltage output end, an amplifier, first to fourth resistors, and 1 st to nth linkage modules, the ith linkage modules comprise i-1 to i-4 th resistors, an ith logic linkage switch, and i=1, …, n;
one end of the ith logic linkage switch is connected with the reference voltage input end, and the other end of the ith logic linkage switch is respectively connected with one end of the third resistor, one end of the fourth resistor and the ground; the other end of the third resistor is connected with one end of the second resistor after being sequentially connected with the 1 st high-voltage interlocking interface to the n high-voltage interlocking interface in series; the other end of the second resistor is connected with the detection voltage output end through the first resistor, the other end of the second resistor is also connected with the negative phase input end of the amplifier, the output end of the amplifier is connected with the detection voltage output end, and the positive phase input end of the amplifier is grounded; the other end of the fourth resistor is sequentially connected with the 1 st resistor, the 2 nd resistor, the 3 rd resistor, the 2 nd resistor, the … …, the n-1 st resistor and the n-2 nd resistor in series and then connected with one end of the second resistor; one end of the ith-2 resistor connected with the (i+1) -1 th resistor and one end of the ith high-voltage interlocking interface connected with the (i+1) -1-th high-voltage interlocking interface are respectively connected with one end of the ith-3 resistor, and one end of the ith-2 resistor connected with the (i-1) -1-th resistor is connected with one end of the (i-4) -1, i=1, … and n-1; one end of the n-2 resistor connected with the second resistor and one end of the n high-voltage interlocking interface connected with the second resistor are respectively connected with one end of the n-3 resistor, and one end of the n-2 resistor connected with the n-1 resistor is connected with one end of the n-4 resistor; the other end of the ith resistor-3 and the other end of the ith resistor-4 are respectively connected with the linkage end of the ith logic linkage switch, i=1, … and n;
when the i high-voltage interlocking interface is closed, one end and the other end of the corresponding i logic linkage switch are closed, and when the i high-voltage interlocking interface is opened, one end and the other end of the corresponding i logic linkage switch are opened.
The resistance of the i-1 resistor is the same as that of the i-2 resistor, the resistance of the i-3 resistor is the same as that of the i-4 resistor, and the resistance of the i-3 resistor is twice that of the i-1 resistor. The resistance of the first resistor is the same as that of the i-1 resistor, and the resistances of the second to fourth resistors are the same as that of the i-3 resistor.
A detection method of a detection circuit based on electrical loop integrity and breakpoint positioning comprises the following steps:
the 1 st to nth high voltage interlocking interfaces are all closed, namely, one end and the other end of an ith logic linkage switch corresponding to the ith high voltage interlocking interface are all 1, a detection voltage value of a detection voltage output end at the moment is obtained, the detection voltage value is converted into an ADC value through analog-to-digital conversion, the values of one end and the other end of each logic linkage switch and the ADC value are recorded in a mapping table, i=1, …, n are all 1 group of data;
selecting one of the 1 st to nth high voltage interlock interfacesOne high-voltage interlocking interface is disconnected, namely, one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interface are all valued to be 0, other high-voltage interlocking interfaces are all closed, the detection voltage value of the detection voltage output end at the moment is obtained, the detection voltage value is converted into an ADC value through analog-to-digital conversion, the ADC range corresponding to the disconnection of one high-voltage interlocking interface and the ADC range corresponding to the loosening of one high-voltage interlocking interface are calculated according to the ADC value, the value of one end and the other end of each logic linkage switch, the ADC value, the ADC range corresponding to the disconnection of one high-voltage interlocking interface and the ADC range corresponding to the loosening are recorded in a mapping table, and the values, the ADC ranges and the ADC ranges are recorded together
Group data;
selecting two of the 1 st to nth high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interface is 0, the other high-voltage interlocking interfaces are closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating the corresponding ADC range when the two high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC range when the two high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values and the ADC ranges in a mapping table together
Group data;
selecting three high-voltage interlocking interfaces from 1 st to n-th high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interfaces are all 0, other high-voltage interlocking interfaces are all closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating the corresponding ADC range when the three high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC range when the three high-voltage interlocking interfaces are disconnected in a mapping table, and sharing
Group data;
……
selecting 1 st to nth high voltage interlocking interfaces, wherein n-1 th high voltage interlocking interfaces are disconnected, namely, one end and the other end of a logic linkage switch corresponding to the disconnected high voltage interlocking interfaces are all 0, other high voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating an ADC range corresponding to the disconnection of the n-1 th high voltage interlocking interfaces according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the ADC range corresponding to the disconnection of the n-1 high voltage interlocking interfaces in a mapping table, and sharing
Group data;
the 1 st to nth high voltage interlocking interfaces are all disconnected, namely, one end and the other end of an ith logic interlocking switch corresponding to the ith high voltage interlocking interface are both taken as 0, the detection voltage value of the detection voltage output end at the moment is obtained, the detection voltage value is converted into an ADC value through analog-to-digital conversion, the ADC ranges corresponding to the disconnection of the n high voltage interlocking interfaces are calculated according to the ADC value, the value taken by one end and the other end of each logic interlocking switch, the ADC value and the ADC range corresponding to the disconnection of the n high voltage interlocking interfaces are recorded in a mapping table, and the two are together
Group data;
The corresponding ADC range when one high voltage interlock interface is disconnected is expressed as:
the range represents the corresponding ADC range when the i-th high voltage interlock interface is disconnected, i=1, …, n, n being the number of all high voltage interlock interfaces, BIN being the corresponding ADC value when the i-th high voltage interlock interface is disconnected,
indicating that the i-th high-voltage interlocking interface disconnects one end of the corresponding logic linkage switch to be inverted, namely +.>
Taking 1.
The corresponding ADC range when the two high voltage interlock interfaces are disconnected is expressed as:
BIN is the corresponding ADC value when the two high-voltage interlocking interfaces are disconnected, i is the larger serial number in the serial numbers corresponding to the two disconnected high-voltage interlocking interfaces,
the other end of the logic linkage switch which indicates that the ith high-voltage interlocking interface is disconnected is reversed, namely +.>
Taking 1.
The corresponding ADC range when one high voltage interlock interface is loose is expressed as:
the range represents the corresponding ADC range when the ith high-voltage interlocking interface is loose, i=1, …, n, n is the number of all high-voltage interlocking interfaces, BIN is the corresponding ADC value when the ith high-voltage interlocking interface is loose,
indicating that the i-th high-voltage interlocking interface disconnects one end of the corresponding logic linkage switch to be inverted, namely +.>
1->
The other end of the logic linkage switch which indicates that the ith high-voltage interlocking interface is disconnected is reversed, namely +.>
Taking 1.
An embodiment will be described in detail below.
Assume that there are four high voltage components in an electrical circuit: JB1, JB2, JB3, JB4, then n in fig. 1 takes 4. The high voltage component breakpoint position and detection voltage mapping table obtained according to fig. 1 is shown in table 1.
TABLE 1 connector breakpoint position and test voltage mapping table
Wherein V represents the detection voltage of the detection voltage output end, vref represents the reference voltage inputReference voltage at terminal D i1 、D i2 The values of one end (right side of table 1) and the other end (left side of table 1) of the interlock switch corresponding to the i-th high voltage component are respectively shown, and BIN represents the ADC value corresponding to V.
1. Loop on-off detection
When the OUT signal voltage is greater than 4980mv, no connector is disconnected. Otherwise the line is broken or the connector is disconnected.
2. 1 breakpoint positioning detection
When the signal voltage of the OUT port is at
And when the number of the connectors is equal to the number of the connectors in the mapping table, the connectors in the corresponding positions in the mapping table are disconnected.
3. Multiple breakpoint number and breakpoint positioning detection
When the signal voltage of the OUT port is at
And when the number of the connectors is equal to the number of the connectors in the mapping table, the connectors in the corresponding positions in the mapping table are disconnected. For example, JB1 and JB3 are off, i takes the larger value 3 of 1 and 3 when calculating the range. When JB1, JB3 and JB4 are disconnected, i takes the maximum value 4 in 1, 3 and 4 when the range is calculated.
4. Single point looseness detection
During the running of the vehicle (vehicle vibration), the signal voltage ADC value at the OUT port is
And when the number is equal to the number, loosening the connectors at the corresponding positions in the mapping table.
5. Circuit self-test
When the vehicle is stationary (the vehicle does not vibrate), the signal voltage ADC value at the OUT port is
And the resistor network is damaged.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.
Claims (6)
1. The detection method is realized based on a detection circuit for the integrity and breakpoint positioning of an electric loop, the electric loop comprises 1 st to nth high-voltage components, the ith high-voltage components comprise an ith high-voltage interlocking interface, the detection circuit comprises a reference voltage input end, a detection voltage output end, an amplifier, first to fourth resistors and 1 st to nth linkage modules, and the ith linkage modules comprise i-1 to i-4 th resistors and an ith logic linkage switch, and i=1, … and n;
one end of the ith logic linkage switch is connected with the reference voltage input end, and the other end of the ith logic linkage switch is respectively connected with one end of the third resistor, one end of the fourth resistor and the ground; the other end of the third resistor is connected with one end of the second resistor after being sequentially connected with the 1 st high-voltage interlocking interface to the n high-voltage interlocking interface in series; the other end of the second resistor is connected with the detection voltage output end through the first resistor, the other end of the second resistor is also connected with the negative phase input end of the amplifier, the output end of the amplifier is connected with the detection voltage output end, and the positive phase input end of the amplifier is grounded; the other end of the fourth resistor is sequentially connected with the 1 st resistor, the 2 nd resistor, the 3 rd resistor, the 2 nd resistor, the … …, the n-1 st resistor and the n-2 nd resistor in series and then connected with one end of the second resistor; one end of the ith-2 resistor connected with the (i+1) -1 th resistor and one end of the ith high-voltage interlocking interface connected with the (i+1) -1-th high-voltage interlocking interface are respectively connected with one end of the ith-3 resistor, and one end of the ith-2 resistor connected with the (i-1) -1-th resistor is connected with one end of the (i-4) -1, i=1, … and n-1; one end of the n-2 resistor connected with the second resistor and one end of the n high-voltage interlocking interface connected with the second resistor are respectively connected with one end of the n-3 resistor, and one end of the n-2 resistor connected with the n-1 resistor is connected with one end of the n-4 resistor; the other end of the ith resistor-3 and the other end of the ith resistor-4 are respectively connected with the linkage end of the ith logic linkage switch, i=1, … and n;
when the ith high-voltage interlocking interface is closed, one end and the other end of the corresponding ith logic linkage switch are both closed, and when the ith high-voltage interlocking interface is opened, one end and the other end of the corresponding ith logic linkage switch are both opened; the detection method is characterized by comprising the following steps of:
step 1, acquiring a breakpoint position and a detection voltage mapping table of a high-voltage component according to an electric loop integrity and a breakpoint positioning detection circuit; the method comprises the following steps:
the 1 st to nth high voltage interlocking interfaces are all closed, namely, one end and the other end of an ith logic linkage switch corresponding to the ith high voltage interlocking interface are all 1, a detection voltage value of a detection voltage output end at the moment is obtained, the detection voltage value is converted into an ADC value through analog-to-digital conversion, the values of one end and the other end of each logic linkage switch and the ADC value are recorded in a mapping table, i=1, …, n are all 1 group of data;
selecting one of the 1 st to nth high-voltage interlocking interfaces to be disconnected, namely, disconnecting one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interface to be 0, disconnecting the other high-voltage interlocking interfaces to be closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating an ADC range corresponding to one high-voltage interlocking interface when the disconnected high-voltage interlocking interface and an ADC range corresponding to one high-voltage interlocking interface when the high-voltage interlocking interface is loosened according to the ADC value, and recording the values of one end and the other end of each logic linkage switch, the ADC value, the ADC range corresponding to one high-voltage interlocking interface when the disconnected high-voltage interlocking interface and the ADC range corresponding to the loosening in a mapping table, wherein the values are recorded together in the mapping table
Group data;
selecting two high-voltage interlocking interfaces from the 1 st to the n-th high-voltage interlocking interfaces to be disconnected, namely, the one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interfaces are both 0, and the other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an analog-to-digital (ADC) value, and calculating that the two high-voltage interlocking interfaces are disconnected according to the ADC valueCorresponding ADC ranges when the two high-voltage interlocking interfaces are disconnected are recorded in the mapping table, and the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC ranges when the two high-voltage interlocking interfaces are disconnected are shared
Group data;
selecting three high-voltage interlocking interfaces from 1 st to n-th high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linkage switch corresponding to the disconnected high-voltage interlocking interfaces are all 0, other high-voltage interlocking interfaces are all closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating the corresponding ADC range when the three high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC range when the three high-voltage interlocking interfaces are disconnected in a mapping table, and sharing
Group data;
……
selecting 1 st to nth high voltage interlocking interfaces, wherein n-1 th high voltage interlocking interfaces are disconnected, namely, one end and the other end of a logic linkage switch corresponding to the disconnected high voltage interlocking interfaces are all 0, other high voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC value through analog-to-digital conversion, calculating an ADC range corresponding to the disconnection of the n-1 th high voltage interlocking interfaces according to the ADC value, recording the value of one end and the other end of each logic linkage switch, the ADC value and the ADC range corresponding to the disconnection of the n-1 high voltage interlocking interfaces in a mapping table, and sharing
Group data;
the 1 st to the nth high voltage interlocking interfaces are all disconnected, namely one end and the other end of the ith logic linkage switch corresponding to the ith high voltage interlocking interface are all 0, the detection voltage value of the detection voltage output end at the moment is obtained, and the detection voltage value is obtainedThe detection voltage value is converted into an ADC value through analog-to-digital conversion, the corresponding ADC ranges when the n high-voltage interlocking interfaces are disconnected are calculated according to the ADC value, the value of one end and the other end of each logic linkage switch, the ADC value and the corresponding ADC ranges when the n high-voltage interlocking interfaces are disconnected are recorded in a mapping table, and the mapping table is shared
Group data;
step 2, obtaining a detection voltage value of a detection voltage output end at the current moment, converting the detection voltage value into an ADC value, searching a range where the ADC value is located in a mapping table, and determining whether the range belongs to an ADC range corresponding to the disconnection of a high-voltage interlocking interface or an ADC range corresponding to the loosening of the high-voltage interlocking interface; if the range belongs to the corresponding ADC range when the high-voltage interlocking interface is disconnected, determining which high-voltage components are disconnected according to a mapping table; if the range belongs to the corresponding ADC range when the high-voltage interlocking interface loosens, judging whether the vehicle in which the electric loop is positioned vibrates, if so, determining which high-voltage component loosens according to the mapping table, and if not, indicating that the detection circuit is damaged.
2. The method according to claim 1, wherein the i-1 th resistor and the i-2 th resistor have the same resistance, the i-3 rd resistor and the i-4 th resistor have the same resistance, and the i-3 th resistor has a resistance twice as high as the i-1 th resistor.
3. The method according to claim 2, wherein the first resistor has the same resistance as the i-1 resistor, and the second to fourth resistors have the same resistance as the i-3 resistor.
4. The method of claim 1, wherein the corresponding ADC range when the one high voltage interlock interface is disconnected is expressed as:
the range represents the corresponding ADC range when the i-th high voltage interlock interface is disconnected, i=1, …, n, n being the number of all high voltage interlock interfaces, BIN being the corresponding ADC value when the i-th high voltage interlock interface is disconnected,
indicating that the i-th high-voltage interlocking interface disconnects one end of the corresponding logic linkage switch to be inverted, namely +.>
Taking 1.
5. The method of claim 1, wherein the corresponding ADC ranges when the two high voltage interlock interfaces are disconnected are expressed as:
BIN is the corresponding ADC value when the two high-voltage interlocking interfaces are disconnected, i is the larger serial number in the serial numbers corresponding to the two disconnected high-voltage interlocking interfaces,
the other end of the logic linkage switch which indicates that the ith high-voltage interlocking interface is disconnected is reversed, namely +.>
Taking 1./>
6. The method of claim 1, wherein the corresponding ADC range when the one high voltage interlock interface is loose is expressed as:
the range represents the corresponding ADC range when the ith high-voltage interlocking interface is loose, i=1, …, n, n is the number of all high-voltage interlocking interfaces, BIN is the corresponding ADC value when the ith high-voltage interlocking interface is loose, D i1 Indicating that the i-th high-voltage interlocking interface disconnects one end of the corresponding logic linkage switch, namely D i1 Taking 1, D i2 Indicating that the other end of the logic linkage switch corresponding to the i-th high-voltage interlocking interface is disconnected is reversed, namely D i2 Taking 1.
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