CN111796213A - Detection circuit and method for electrical loop integrity and breakpoint positioning - Google Patents
Detection circuit and method for electrical loop integrity and breakpoint positioning Download PDFInfo
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- CN111796213A CN111796213A CN202010660969.7A CN202010660969A CN111796213A CN 111796213 A CN111796213 A CN 111796213A CN 202010660969 A CN202010660969 A CN 202010660969A CN 111796213 A CN111796213 A CN 111796213A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/56—Testing of electric apparatus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
Abstract
The invention discloses a detection circuit and a method for electrical loop integrity and breakpoint positioning, wherein the detection circuit comprises a reference voltage input end, a detection voltage output end, an amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a sixth resistor, anLinkage module ofiThe linkage module comprises a firsti‑1 to the firsti‑4 resistance, the secondiA logic linkage switch. The detection method comprises the steps of obtaining a breakpoint position of the high-voltage component and a detection voltage mapping table according to the integrity of the electric circuit and a breakpoint positioning detection circuit, obtaining a detection voltage value of a detection voltage output end at the current moment, converting the detection voltage value into an ADC (analog to digital converter) value, searching a range where the ADC value is located in the mapping table, and determining whether the range belongs to an ADC range corresponding to the disconnection of the high-voltage interlocking interface or the ADC range corresponding to the loosening of the high-voltage interlocking interface. The invention solves the problems of on-off state detection of an electric loop, multi-point breakpoint positioning detection and contact looseness detection, and has simple realization, economy and reliability.
Description
Technical Field
The invention relates to a detection circuit and a detection method for the integrity and the breakpoint positioning of an electric circuit, belonging to the technical field of connection of high-voltage components (connectors), linkage state confirmation and breakpoint positioning.
Background
One of the risk points of the high-voltage system of the electric automobile is that the automobile loses power due to sudden power failure. There are several possible reasons for the loss of power to the vehicle, one of which is the automatic release of the high-pressure circuit. The high-voltage interlocking can monitor the sign, provide alarm information for the controller before high-voltage power failure and reserve the time for taking countermeasures for the whole vehicle system. Another risk point of the electric automobile is manual misoperation, and in the working process of the system, the high-voltage connection point is manually disconnected. If no high-voltage interlocking design exists, the whole loop voltage is applied to two ends of the breaking point at the moment of disconnection, and the device such as a high-voltage connector which does not have breaking capacity per se is very dangerous. The voltage breakdown air arcs between the two devices, which, while short in time, can be high, potentially causing injury to people and equipment around the break. Two factors of the high-voltage interlocking design need to be considered, one is how the low-voltage system comprehensively detects the connection state of each connection position of the whole high-voltage system; another problem is how to implement the information transmission action of the low-voltage detection circuit before the action of the high-voltage circuit disconnection. The high voltage interlock principle therefore needs to be considered from both these aspects, both in terms of the overall circuit design principle and in terms of the connector design principle itself. A High Voltage Interlock (HVIL) is a safety design method for monitoring the integrity of a high voltage loop by using a low voltage signal. Theoretically, the low voltage monitoring circuit is switched on and off before the high voltage, and the necessary advance, for example, 150ms (difference in displacement between the high voltage contact and the low voltage contact), must be maintained. The electrical components required to be HVIL enabled are mainly the high voltage connector, the manual service switch (MSD).
The mode that the traditional level type high-voltage interlocking or PWM type high-voltage interlocking can only detect the on-off state or can only position the breakpoint by adding a detection interface is changed. The on-off state cannot be detected, and the breakpoint can not be positioned.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the circuit and the method for detecting the integrity and the breakpoint positioning of the electrical circuit solve the problems of on-off state detection, multipoint breakpoint positioning detection and contact looseness detection of the electrical circuit.
The invention adopts the following technical scheme for solving the technical problems:
a detection circuit for integrity and breakpoint positioning of an electrical loop comprises 1 st to nth high-voltage components, wherein the ith high-voltage component comprises an ith high-voltage interlocking interface, the detection circuit comprises a reference voltage input end, a detection voltage output end, an amplifier, first to fourth resistors and 1 st to nth linkage modules, the ith linkage module comprises i-1 th to i-4 th resistors and an ith logic linkage switch, and i is 1, …, n;
one end of the ith logic linked switch is connected with the reference voltage input end, and the other end of the ith logic linked switch is respectively connected with one end of the third resistor, one end of the fourth resistor and the ground; the other end of the third resistor is connected with one end of the second resistor after being sequentially connected in series with the 1 st high-voltage interlocking interface to the nth high-voltage interlocking interface; the other end of the second resistor is connected with the detection voltage output end through the first resistor, the other end of the second resistor is also connected with the negative phase input end of the amplifier, the output end of the amplifier is connected with the detection voltage output end, and the positive phase input end of the amplifier is grounded; the other end of the fourth resistor is connected with one end of the second resistor after being sequentially connected with a 1 st-1 st resistor, a 1 st-2 nd resistor, a 2 nd-1 st resistor, a 2 nd-2 nd resistor, a 3 rd-1 st resistor, a 3 rd-2 nd resistor, … …, an n-1 st resistor and an n-2 nd resistor in series; one end of the i-2 resistor connected with the i +1-1 resistor and one end of the i-1 high-voltage interlocking interface connected with the i +1 high-voltage interlocking interface are respectively connected with one end of an i-3 resistor, one end of the i-2 resistor connected with the i-1 resistor is connected with one end of an i-4 resistor, and i is 1, … and n-1; one end of the n-2 th resistor connected with the second resistor and one end of the n-2 th high-voltage interlocking interface connected with the second resistor are respectively connected with one end of the n-3 th resistor, and one end of the n-2 th resistor connected with the n-1 th resistor is connected with one end of the n-4 th resistor; the other ends of the i-3 th resistor and the i-4 th resistor are respectively connected with the linkage end of the i-th logic linkage switch, and i is 1, … and n;
when the ith high-voltage interlocking interface is closed, one end and the other end of the corresponding ith logic linkage switch are both closed, and when the ith high-voltage interlocking interface is disconnected, one end and the other end of the corresponding ith logic linkage switch are both disconnected.
A detection method of a detection circuit based on the integrity and breakpoint positioning of an electrical loop comprises the following steps:
closing the 1 st to nth high-voltage interlocking interfaces, namely, taking the value of one end and the other end of the ith logic linked switch corresponding to the ith high-voltage interlocking interface as 1, acquiring a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog to digital converter) value through an analog-to-digital converter, and recording the value of one end and the other end of each logic linked switch and the ADC value in a mapping table, wherein i is 1, …, n, and 1 group of data in total;
selecting one of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, the other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating an ADC range corresponding to the disconnection of one high-voltage interlocking interface and an ADC range corresponding to the loosening of one high-voltage interlocking interface according to the ADC value, recording the values of one end and the other end of each logic linked switch, the ADC value, the ADC range corresponding to the disconnection of one high-voltage interlocking interface and the ADC range corresponding to the loosening in a mapping table
Group data;
selecting two of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface is 0, the other high-voltage interlocking interfaces are closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating the ADC range corresponding to the disconnection of the two high-voltage interlocking interfaces according to the ADC value, and comparing the value of one end and the other end of each logic linked switch, the ADC value and the disconnection of the two high-voltage interlocking interfacesThe corresponding ADC range is recorded in a mapping table
Group data;
selecting three high-voltage interlocking interfaces from 1 st to nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating corresponding ADC ranges when the three high-voltage interlocking interfaces are disconnected according to the ADC value, recording the values of one end and the other end of each logic linked switch, the ADC value and the corresponding ADC ranges when the three high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values
Group data;
……
selecting n-1 of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating an ADC range corresponding to the n-1 high-voltage interlocking interfaces when the n-1 high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linked switch, the ADC value and the ADC range corresponding to the n-1 high-voltage interlocking interfaces when the n-1 high
Group data;
the method comprises the steps of enabling 1 st to nth high-voltage interlocking interfaces to be disconnected, namely enabling one end and the other end of an ith logic linkage switch corresponding to the ith high-voltage interlocking interface to be 0, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating corresponding ADC ranges when the n high-voltage interlocking interfaces are disconnected according to the ADC value, and taking one end and the other end of each logic linkage switchThe values, ADC values and corresponding ADC ranges when n high-voltage interlocking interfaces are disconnected are recorded in a mapping table
Group data;
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
the HVIL interfaces of the high-voltage components are connected in series through the single shielding wire, and the fault location is realized by detecting the change of the voltage of the distribution point, so that the method is economical, reliable and simple to realize. The loop integrity detection of the high-voltage plug-in and the low-voltage plug-in can be realized simultaneously, scene recognition support is provided for vehicle interlocking faults, and a quick channel is provided for after-sale problem troubleshooting.
Drawings
Fig. 1 is a schematic diagram of a detection circuit for electrical loop integrity and breakpoint positioning according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
As shown in fig. 1, the detection circuit for integrity and breakpoint positioning of an electrical circuit according to the present invention includes a 1 st to an nth high voltage component, where the ith high voltage component includes an ith high voltage interlock interface, the detection circuit includes a reference voltage input terminal, a detection voltage output terminal, an amplifier, first to fourth resistors, and a 1 st to nth linkage module, where the ith linkage module includes an i-1 th to an i-4 th resistor and an ith logic linkage switch, where i is 1, …, n;
one end of the ith logic linked switch is connected with the reference voltage input end, and the other end of the ith logic linked switch is respectively connected with one end of the third resistor, one end of the fourth resistor and the ground; the other end of the third resistor is connected with one end of the second resistor after being sequentially connected in series with the 1 st high-voltage interlocking interface to the nth high-voltage interlocking interface; the other end of the second resistor is connected with the detection voltage output end through the first resistor, the other end of the second resistor is also connected with the negative phase input end of the amplifier, the output end of the amplifier is connected with the detection voltage output end, and the positive phase input end of the amplifier is grounded; the other end of the fourth resistor is connected with one end of the second resistor after being sequentially connected with a 1 st-1 st resistor, a 1 st-2 nd resistor, a 2 nd-1 st resistor, a 2 nd-2 nd resistor, a 3 rd-1 st resistor, a 3 rd-2 nd resistor, … …, an n-1 st resistor and an n-2 nd resistor in series; one end of the i-2 resistor connected with the i +1-1 resistor and one end of the i-1 high-voltage interlocking interface connected with the i +1 high-voltage interlocking interface are respectively connected with one end of an i-3 resistor, one end of the i-2 resistor connected with the i-1 resistor is connected with one end of an i-4 resistor, and i is 1, … and n-1; one end of the n-2 th resistor connected with the second resistor and one end of the n-2 th high-voltage interlocking interface connected with the second resistor are respectively connected with one end of the n-3 th resistor, and one end of the n-2 th resistor connected with the n-1 th resistor is connected with one end of the n-4 th resistor; the other ends of the i-3 th resistor and the i-4 th resistor are respectively connected with the linkage end of the i-th logic linkage switch, and i is 1, … and n;
when the ith high-voltage interlocking interface is closed, one end and the other end of the corresponding ith logic linkage switch are both closed, and when the ith high-voltage interlocking interface is disconnected, one end and the other end of the corresponding ith logic linkage switch are both disconnected.
The resistance of the (i-1) th resistor is the same as that of the (i-2) th resistor, the resistance of the (i-3) th resistor is the same as that of the (i-4) th resistor, and the resistance of the (i-3) th resistor is twice that of the (i-1) th resistor. The resistance of the first resistor is the same as that of the (i-1) th resistor, and the resistance of the second to fourth resistors is the same as that of the (i-3) th resistor.
A detection method of a detection circuit based on electrical loop integrity and breakpoint positioning comprises the following steps:
closing the 1 st to nth high-voltage interlocking interfaces, namely, taking the value of one end and the other end of the ith logic linked switch corresponding to the ith high-voltage interlocking interface as 1, acquiring a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog to digital converter) value through an analog-to-digital converter, and recording the value of one end and the other end of each logic linked switch and the ADC value in a mapping table, wherein i is 1, …, n, and 1 group of data in total;
selecting one of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, the other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating an ADC range corresponding to the disconnection of one high-voltage interlocking interface and an ADC range corresponding to the loosening of one high-voltage interlocking interface according to the ADC value, recording the values of one end and the other end of each logic linked switch, the ADC value, the ADC range corresponding to the disconnection of one high-voltage interlocking interface and the ADC range corresponding to the loosening in a mapping table
Group data;
selecting two of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interfaces are both 0, the other high-voltage interlocking interfaces are all closed, acquiring the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value, and calculating two ADC values according to the ADC valueRecording values of one end and the other end of each logic linked switch, ADC values and corresponding ADC ranges when the two high-voltage interlocking interfaces are disconnected in a mapping table, wherein the values and the ADC ranges correspond to the high-voltage interlocking interfaces when the two high-voltage interlocking interfaces are disconnected
Group data;
selecting three high-voltage interlocking interfaces from 1 st to nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating corresponding ADC ranges when the three high-voltage interlocking interfaces are disconnected according to the ADC value, recording the values of one end and the other end of each logic linked switch, the ADC value and the corresponding ADC ranges when the three high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values
Group data;
……
selecting n-1 of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating an ADC range corresponding to the n-1 high-voltage interlocking interfaces when the n-1 high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linked switch, the ADC value and the ADC range corresponding to the n-1 high-voltage interlocking interfaces when the n-1 high
Group data;
the 1 st to nth high-voltage interlocking interfaces are all disconnected, namely, one end and the other end of the ith logic linked switch corresponding to the ith high-voltage interlocking interface are both taken as 0, the detection voltage value of the detection voltage output end at the moment is obtained, and the detection is carried outConverting the voltage value into an ADC value through analog-to-digital conversion, calculating corresponding ADC ranges when the n high-voltage interlocking interfaces are disconnected according to the ADC value, recording values of one end and the other end of each logic gang switch, the ADC value and the corresponding ADC ranges when the n high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values, the ADC values and the corresponding ADC ranges in the mapping table when the n high-voltage interlocking interfaces are disconnected
Group data;
The corresponding ADC range when one high voltage interlock interface is open is expressed as:
the range represents the corresponding ADC range when the ith high-voltage interlocking interface is disconnected, i is 1, …, n is the number of all the high-voltage interlocking interfaces, BIN is the corresponding ADC value when the ith high-voltage interlocking interface is disconnected,
one end of the logic linkage switch which represents that the ith high-voltage interlocking interface is disconnected with the corresponding logic linkage switch is inverted, namely
1 is taken.
The corresponding ADC range when the two high voltage interlock interfaces are disconnected is represented as:
BIN is the corresponding ADC value when the two high-voltage interlocking interfaces are disconnected, i takes the value of the larger serial number in the serial numbers corresponding to the two disconnected high-voltage interlocking interfaces,
the other end of the logic linkage switch corresponding to the ith high-voltage interlocking interface is disconnected is inverted, namely
1 is taken.
The corresponding ADC range when a high voltage interlock interface is loose is expressed as:
the range represents the corresponding ADC range when the ith high-voltage interlocking interface is loosened, i is 1, …, n is the number of all the high-voltage interlocking interfaces, BIN is the corresponding ADC value when the ith high-voltage interlocking interface is loosened,
one end of the logic linkage switch which represents that the ith high-voltage interlocking interface is disconnected with the corresponding logic linkage switch is inverted, namely
Taking out the number 1 of the samples,
the other end of the logic linkage switch corresponding to the ith high-voltage interlocking interface is disconnected is inverted, namely
1 is taken.
The following description will specifically explain an embodiment.
Assume that there are four high voltage components in an electrical circuit: JB1, JB2, JB3, and JB4, wherein n is 4 in FIG. 1. The high-voltage component breakpoint position and detection voltage mapping table obtained according to fig. 1 is shown in table 1.
TABLE 1 connector breakpoint position and detection voltage mapping table
Where V denotes a detection voltage at the detection voltage output terminal, Vref denotes a reference voltage at the reference voltage input terminal, Di1、Di2Respectively represent values of one end (corresponding to the right side of the table 1) and the other end (corresponding to the left side of the table 1) of the ganged switch corresponding to the ith high-voltage component, and BIN represents an ADC value corresponding to V.
1. Loop on-off detection
When the signal voltage of the OUT port is greater than 4980mv, no connector is disconnected. Otherwise, the line is interrupted or the connector is disconnected.
2. 1 breakpoint positioning detection
When the signal voltage of the OUT port is at
And when the mapping table is in the middle, the connectors at the corresponding positions and the corresponding number in the mapping table are disconnected.
3. Number of multiple breakpoints and breakpoint positioning detection
When the signal voltage of the OUT port is at
And when the mapping table is in the middle, the connectors at the corresponding positions and the corresponding number in the mapping table are disconnected. For example, when JB1 and JB3 are disconnected, i takes the larger value of 3 out of 1 and 3 when calculating the range. When JB1, JB3, and JB4 were disconnected, i took the maximum value of 4 out of 1, 3, and 4 when calculating this range.
4. Single point loosening detection
When the signal voltage ADC value of the OUT port is in the process of vehicle running (vehicle vibration)
And when the mapping table is in the middle, the connector at the corresponding position in the mapping table is loosened.
5. Circuit self-checking
When the vehicle is at rest (the vehicle does not vibrate), the signal voltage ADC value at the OUT port is
In between, the resistor network is damaged.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (7)
1. The detection circuit for the integrity and the breakpoint positioning of the electrical loop comprises 1 st to nth high-voltage components, wherein the ith high-voltage component comprises an ith high-voltage interlocking interface, and is characterized by comprising a reference voltage input end, a detection voltage output end, an amplifier, first to fourth resistors and 1 st to nth linkage modules, wherein the ith linkage module comprises i-1 st to i-4 th resistors and an ith logic linkage switch, and i is 1, …, n;
one end of the ith logic linked switch is connected with the reference voltage input end, and the other end of the ith logic linked switch is respectively connected with one end of the third resistor, one end of the fourth resistor and the ground; the other end of the third resistor is connected with one end of the second resistor after being sequentially connected in series with the 1 st high-voltage interlocking interface to the nth high-voltage interlocking interface; the other end of the second resistor is connected with the detection voltage output end through the first resistor, the other end of the second resistor is also connected with the negative phase input end of the amplifier, the output end of the amplifier is connected with the detection voltage output end, and the positive phase input end of the amplifier is grounded; the other end of the fourth resistor is connected with one end of the second resistor after being sequentially connected with a 1 st-1 st resistor, a 1 st-2 nd resistor, a 2 nd-1 st resistor, a 2 nd-2 nd resistor, a 3 rd-1 st resistor, a 3 rd-2 nd resistor, … …, an n-1 st resistor and an n-2 nd resistor in series; one end of the i-2 resistor connected with the i +1-1 resistor and one end of the i-1 high-voltage interlocking interface connected with the i +1 high-voltage interlocking interface are respectively connected with one end of an i-3 resistor, one end of the i-2 resistor connected with the i-1 resistor is connected with one end of an i-4 resistor, and i is 1, … and n-1; one end of the n-2 th resistor connected with the second resistor and one end of the n-2 th high-voltage interlocking interface connected with the second resistor are respectively connected with one end of the n-3 th resistor, and one end of the n-2 th resistor connected with the n-1 th resistor is connected with one end of the n-4 th resistor; the other ends of the i-3 th resistor and the i-4 th resistor are respectively connected with the linkage end of the i-th logic linkage switch, and i is 1, … and n;
when the ith high-voltage interlocking interface is closed, one end and the other end of the corresponding ith logic linkage switch are both closed, and when the ith high-voltage interlocking interface is disconnected, one end and the other end of the corresponding ith logic linkage switch are both disconnected.
2. The circuit for detecting the integrity and the location of a breakpoint of an electrical loop according to claim 1, wherein the resistance values of the i-1 th resistor and the i-2 th resistor are the same, the resistance values of the i-3 rd resistor and the i-4 th resistor are the same, and the resistance value of the i-3 th resistor is twice the resistance value of the i-1 th resistor.
3. The circuit as claimed in claim 2, wherein the first resistor has the same resistance as that of the i-1 th resistor, and the second to fourth resistors have the same resistance as that of the i-3 th resistor.
4. A method for detecting an electrical loop integrity and breakpoint positioning detection circuit according to claim 1, comprising the steps of:
step 1, acquiring a breakpoint position and a detection voltage mapping table of a high-voltage component according to the integrity of an electrical circuit and a detection circuit for positioning breakpoints; the method specifically comprises the following steps:
closing the 1 st to nth high-voltage interlocking interfaces, namely, taking the value of one end and the other end of the ith logic linked switch corresponding to the ith high-voltage interlocking interface as 1, acquiring a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog to digital converter) value through an analog-to-digital converter, and recording the value of one end and the other end of each logic linked switch and the ADC value in a mapping table, wherein i is 1, …, n, and 1 group of data in total;
selecting one of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, the other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating an ADC range corresponding to the disconnection of one high-voltage interlocking interface and an ADC range corresponding to the loosening of one high-voltage interlocking interface according to the ADC value, recording the values of one end and the other end of each logic linked switch, the ADC value, the ADC range corresponding to the disconnection of one high-voltage interlocking interface and the ADC range corresponding to the loosening in a mapping table
Group data;
selecting two of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface is 0, the other high-voltage interlocking interfaces are closed, obtaining the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating the corresponding ADC range when the two high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linked switch, the ADC value and the corresponding ADC range when the two high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values in the
Group data;
selecting three of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, the value of one end and the other end of the logic linked switch corresponding to the disconnected high-voltage interlocking interface is 0, and the other high-voltage interlocking interfaces are closed to obtainTaking the detection voltage value of the detection voltage output end at the moment, converting the detection voltage value into an ADC value through an analog-to-digital converter, calculating the corresponding ADC ranges when the three high-voltage interlocking interfaces are disconnected according to the ADC value, recording the values of one end and the other end of each logic linked switch, the ADC value and the corresponding ADC ranges when the three high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values, the ADC values and the corresponding ADC ranges in the mapping table
Group data;
……
selecting n-1 of the 1 st to the nth high-voltage interlocking interfaces to be disconnected, namely, one end and the other end of a logic linked switch corresponding to the disconnected high-voltage interlocking interface are both taken as 0, other high-voltage interlocking interfaces are all closed, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter, calculating an ADC range corresponding to the n-1 high-voltage interlocking interfaces when the n-1 high-voltage interlocking interfaces are disconnected according to the ADC value, recording the value of one end and the other end of each logic linked switch, the ADC value and the ADC range corresponding to the n-1 high-voltage interlocking interfaces when the n-1 high
Group data;
the method comprises the steps of enabling 1 st to nth high-voltage interlocking interfaces to be disconnected, namely enabling one end and the other end of an ith logic linkage switch corresponding to the ith high-voltage interlocking interface to be respectively taken as 0, obtaining a detection voltage value of a detection voltage output end at the moment, converting the detection voltage value into an ADC (analog-to-digital converter) value through an analog-to-digital converter), calculating corresponding ADC ranges when n high-voltage interlocking interfaces are disconnected according to the ADC values, recording the values of one end and the other end of each logic linkage switch, the ADC values and the corresponding ADC ranges when the n high-voltage interlocking interfaces are disconnected in a mapping table, and recording the values
Group data;
step 2, obtaining a detection voltage value of a detection voltage output end at the current moment, converting the detection voltage value into an ADC value, searching a range where the ADC value is located in a mapping table, and determining whether the range belongs to the corresponding ADC range when the high-voltage interlocking interface is disconnected or the corresponding ADC range when the high-voltage interlocking interface is loosened; if the range belongs to the corresponding ADC range when the high-voltage interlocking interface is disconnected, determining which high-voltage components are disconnected according to a mapping table; if the range belongs to the ADC range corresponding to the looseness of the high-voltage interlocking interface, judging whether a vehicle where the electric loop is located vibrates, if so, determining which high-voltage component loosens according to the mapping table, and if not, indicating that the detection circuit is damaged.
5. The method of claim 4, wherein the ADC range corresponding to the disconnection of the one high-voltage interlock interface is expressed as:
the range represents the corresponding ADC range when the ith high-voltage interlocking interface is disconnected, i is 1, …, n is the number of all the high-voltage interlocking interfaces, BIN is the corresponding ADC value when the ith high-voltage interlocking interface is disconnected,
one end of the logic linkage switch which represents that the ith high-voltage interlocking interface is disconnected with the corresponding logic linkage switch is inverted, namely
1 is taken.
6. The detection method according to claim 4, wherein the ADC ranges corresponding to the disconnection of the two high-voltage interlock interfaces are expressed as:
BIN is the corresponding ADC value when the two high-voltage interlocking interfaces are disconnected, i takes the value of the larger serial number in the serial numbers corresponding to the two disconnected high-voltage interlocking interfaces,
the other end of the logic linkage switch corresponding to the ith high-voltage interlocking interface is disconnected is inverted, namely
1 is taken.
7. The method of claim 4, wherein the ADC range corresponding to the loose one of the high voltage interlock interfaces is expressed as:
the range represents the corresponding ADC range when the ith high-voltage interlocking interface is loosened, i is 1, …, n is the number of all the high-voltage interlocking interfaces, BIN is the corresponding ADC value when the ith high-voltage interlocking interface is loosened,
one end of the logic linkage switch which represents that the ith high-voltage interlocking interface is disconnected with the corresponding logic linkage switch is inverted, namely
Taking out the number 1 of the samples,
the other end of the logic linkage switch corresponding to the ith high-voltage interlocking interface is disconnected is inverted, namely
1 is taken.
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Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120238124A1 (en) * | 2011-03-15 | 2012-09-20 | Tyco Electronics Corporation | High Voltage Connector Assembly |
| CN204077389U (en) * | 2014-08-04 | 2015-01-07 | 浙江吉利控股集团有限公司 | Power brick high-voltage interlocking circuit system |
| CN104377684A (en) * | 2013-08-13 | 2015-02-25 | 上海汽车集团股份有限公司 | Interlocking detecting circuit, system and method of high-voltage parts |
| CN105203910A (en) * | 2015-10-20 | 2015-12-30 | 北京新能源汽车股份有限公司 | Electromobile, as well as high-low voltage interlocking detection circuit and interlocking signal detection method thereof |
| CN105270184A (en) * | 2015-10-26 | 2016-01-27 | 北京新能源汽车股份有限公司 | Electric automobile and high and low voltage interlocking detecting circuit |
| CN107219437A (en) * | 2017-05-27 | 2017-09-29 | 北京新能源汽车股份有限公司 | High-voltage interlocking detection circuit, method, device and automobile |
| CN107310395A (en) * | 2016-04-27 | 2017-11-03 | 东营俊通汽车有限公司 | The diagnostic circuit and method of a kind of loop interlocking |
| CN206644654U (en) * | 2017-04-13 | 2017-11-17 | 深圳市瀚路新能源汽车有限公司 | High-voltage interlocking loop and high-voltage interlocking loop detector |
| US20180113157A1 (en) * | 2016-10-24 | 2018-04-26 | Oliver Gross | High voltage test and service module |
| CN108469566A (en) * | 2018-03-31 | 2018-08-31 | 山东交通职业学院 | A kind of electric automobile high-voltage interlocking loop and broken circuit detecting method |
| CN108466553A (en) * | 2018-03-31 | 2018-08-31 | 山东交通职业学院 | A kind of electric automobile high-voltage interlocking loop of multibreak monitoring |
| CN108482127A (en) * | 2018-03-31 | 2018-09-04 | 山东交通职业学院 | A kind of electric automobile high-voltage interlocking loop and breaking localization method |
| CN108896861A (en) * | 2018-08-24 | 2018-11-27 | 北京新能源汽车股份有限公司 | A kind of detection circuit and electric car in high-voltage interlocking circuit |
| CN208207183U (en) * | 2018-05-29 | 2018-12-07 | 吉利汽车研究院（宁波）有限公司 | High-voltage interlocking detection circuit and electric car |
| CN109100597A (en) * | 2018-10-18 | 2018-12-28 | 奇瑞新能源汽车技术有限公司 | A kind of high-pressure-loop interlock fault positioning circuit and localization method |
| CN109655708A (en) * | 2019-01-04 | 2019-04-19 | 北京新能源汽车股份有限公司 | The fault detection means and method of electric car and its high-voltage interlocking system |
| CN109664841A (en) * | 2018-12-06 | 2019-04-23 | 东软睿驰汽车技术（沈阳）有限公司 | A kind of high voltage interlock circuit, fault detection method and device |
| CN110014839A (en) * | 2019-04-09 | 2019-07-16 | 山东交通职业学院 | A kind of electric automobile high-voltage interlock detection circuit |
| CN209821326U (en) * | 2019-03-21 | 2019-12-20 | 鲁建华 | New energy automobile high pressure interlocking detection circuitry structure |
| CN210258025U (en) * | 2019-06-17 | 2020-04-07 | 北京长城华冠汽车科技股份有限公司 | High-voltage interlocking detection device and electric vehicle |
| CN111016656A (en) * | 2018-10-09 | 2020-04-17 | 上海汽车集团股份有限公司 | High-voltage interlocking detection circuit and detection method |
-
2020
- 2020-07-10 CN CN202010660969.7A patent/CN111796213B/en active Active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120238124A1 (en) * | 2011-03-15 | 2012-09-20 | Tyco Electronics Corporation | High Voltage Connector Assembly |
| CN104377684A (en) * | 2013-08-13 | 2015-02-25 | 上海汽车集团股份有限公司 | Interlocking detecting circuit, system and method of high-voltage parts |
| CN204077389U (en) * | 2014-08-04 | 2015-01-07 | 浙江吉利控股集团有限公司 | Power brick high-voltage interlocking circuit system |
| CN105203910A (en) * | 2015-10-20 | 2015-12-30 | 北京新能源汽车股份有限公司 | Electromobile, as well as high-low voltage interlocking detection circuit and interlocking signal detection method thereof |
| CN105270184A (en) * | 2015-10-26 | 2016-01-27 | 北京新能源汽车股份有限公司 | Electric automobile and high and low voltage interlocking detecting circuit |
| CN107310395A (en) * | 2016-04-27 | 2017-11-03 | 东营俊通汽车有限公司 | The diagnostic circuit and method of a kind of loop interlocking |
| US20180113157A1 (en) * | 2016-10-24 | 2018-04-26 | Oliver Gross | High voltage test and service module |
| CN206644654U (en) * | 2017-04-13 | 2017-11-17 | 深圳市瀚路新能源汽车有限公司 | High-voltage interlocking loop and high-voltage interlocking loop detector |
| CN107219437A (en) * | 2017-05-27 | 2017-09-29 | 北京新能源汽车股份有限公司 | High-voltage interlocking detection circuit, method, device and automobile |
| CN108466553A (en) * | 2018-03-31 | 2018-08-31 | 山东交通职业学院 | A kind of electric automobile high-voltage interlocking loop of multibreak monitoring |
| CN108469566A (en) * | 2018-03-31 | 2018-08-31 | 山东交通职业学院 | A kind of electric automobile high-voltage interlocking loop and broken circuit detecting method |
| CN108482127A (en) * | 2018-03-31 | 2018-09-04 | 山东交通职业学院 | A kind of electric automobile high-voltage interlocking loop and breaking localization method |
| CN208207183U (en) * | 2018-05-29 | 2018-12-07 | 吉利汽车研究院（宁波）有限公司 | High-voltage interlocking detection circuit and electric car |
| CN108896861A (en) * | 2018-08-24 | 2018-11-27 | 北京新能源汽车股份有限公司 | A kind of detection circuit and electric car in high-voltage interlocking circuit |
| CN111016656A (en) * | 2018-10-09 | 2020-04-17 | 上海汽车集团股份有限公司 | High-voltage interlocking detection circuit and detection method |
| CN109100597A (en) * | 2018-10-18 | 2018-12-28 | 奇瑞新能源汽车技术有限公司 | A kind of high-pressure-loop interlock fault positioning circuit and localization method |
| CN109664841A (en) * | 2018-12-06 | 2019-04-23 | 东软睿驰汽车技术（沈阳）有限公司 | A kind of high voltage interlock circuit, fault detection method and device |
| CN109655708A (en) * | 2019-01-04 | 2019-04-19 | 北京新能源汽车股份有限公司 | The fault detection means and method of electric car and its high-voltage interlocking system |
| CN209821326U (en) * | 2019-03-21 | 2019-12-20 | 鲁建华 | New energy automobile high pressure interlocking detection circuitry structure |
| CN110014839A (en) * | 2019-04-09 | 2019-07-16 | 山东交通职业学院 | A kind of electric automobile high-voltage interlock detection circuit |
| CN210258025U (en) * | 2019-06-17 | 2020-04-07 | 北京长城华冠汽车科技股份有限公司 | High-voltage interlocking detection device and electric vehicle |
Non-Patent Citations (1)
| Title |
|---|
| 周启晟: "电动汽车高压电连接与绝缘状态参数在线监测", 《电源技术》 * |
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