CN111792621B

CN111792621B - Wafer level thin film packaging method and packaging device

Info

Publication number: CN111792621B
Application number: CN202010640709.3A
Authority: CN
Inventors: 钟朋; 裴彬彬; 孙珂; 杨恒; 李昕欣
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2024-04-16
Anticipated expiration: 2040-07-06
Also published as: CN111792621A

Abstract

The invention relates to the technical field of microelectronic mechanical packaging, in particular to a wafer level thin film packaging method and a packaging device, wherein the method comprises the following steps: obtaining a chip wafer; etching part of the sacrificial layer to form a transverse etching hole between the substrate and the shell; depositing a first metal layer at the position of the transverse etching hole by adopting an evaporation or sputtering process, wherein the first metal layer is provided with a nano-scale through hole; depositing a second metal layer on the first metal layer; releasing the sacrificial layer through the sacrificial layer release hole to obtain a device to be packaged; and heating the device to be packaged, wherein the heating temperature is between the melting point of the second metal layer and the melting point of the first metal layer, so that the second metal layer is melted and spread, and the sacrificial layer release hole is sealed. By providing a lateral drill hole in the package structure, the lateral drill hole is used to form a self-aligned via hole in the metal layer, and sealing can be achieved by depositing a small amount of low-melting-point sealing metal at the via hole.

Description

Wafer level thin film packaging method and packaging device

Technical Field

The invention relates to the technical field of microelectronic mechanical packaging, in particular to a wafer level thin film packaging method and a packaging device.

Background

Micromechanical system (Micro-Electro-Mechanical System, MEMS) sensors achieve a high degree of integration of functionality by shrinking the size of sensitive structures. The air resistance is related to the structural feature size, the air resistance suffered by a macro-scale object at a low speed is generally negligible, but in a MEMS sensor with a small structural feature size, the air resistance is a main damping mechanism of the MEMS device, and the Q value of the sensor is determined, so that the amplitude-frequency characteristic, the phase-frequency characteristic and the bandwidth of the sensor are obviously influenced. Meanwhile, brownian motion noise caused by gas molecule thermal fluctuation is also main noise of MEMS devices such as an acceleration sensor, a gyroscope and the like. The vacuum packaging technique can significantly reduce air damping losses. Therefore, vacuum packaging is of great importance for a variety of MEMS devices.

The only surface micromachined vacuum packaging technology currently in commercial use is the epitaxial vacuum packaging (epieal) technology. The technology utilizes an epitaxially grown polysilicon layer to block the through hole to form an airtight vacuum cavity, utilizes the characteristic that residual gas generated by an epitaxial process is hydrogen which can diffuse through a solid structure, and diffuses the hydrogen out of the airtight cavity through a post-packaging thermal annealing process to form a high-reliability high-vacuum package. This process has been used in the manufacture of specialty sensors, such as high precision pressure sensors, MEMS oscillators, etc., that do not in part require metal wiring prior to vacuum packaging.

The problem with the epieal process is that a high temperature epitaxy process is required to plug the holes, the temperature is up to 980 ℃, and the high temperature process is used for tightly prohibiting all metal materials from entering, so that the process is only suitable for sensors which are respectively made of homogeneous silicon materials and do not need to manufacture metal wiring before packaging. The common MEMS sensor needs to be manufactured with metal wiring before packaging, and cannot be vacuum packaged by adopting the process. In addition, the MEMS structure is released when the epitaxial polysilicon hole is plugged, and the wafer cannot be cleaned before the epitaxial process, so that the sacrificial layer corrosion equipment and the epitaxial equipment are special, the equipment investment is large, and the process cost is high.

Disclosure of Invention

The invention aims to solve the technical problems that the existing micromechanical vacuum packaging technology has high process temperature and complex process.

In order to solve the above technical problems, in a first aspect, an embodiment of the present application discloses a wafer level thin film packaging method, including:

obtaining a chip wafer, wherein the chip wafer comprises a substrate, a sacrificial layer and a shell, a micromechanical structure is arranged on the substrate, and the sacrificial layer is arranged between the micromechanical structure and the shell;

etching part of the sacrificial layer to form a transverse etching hole between the substrate and the shell;

Depositing a first metal layer at the position of the transverse drilling hole by adopting an evaporation or sputtering process, wherein the first metal layer is provided with a nano-scale through hole, the through hole is communicated with the transverse drilling hole to form a sacrificial layer release hole, and the thickness of the first metal layer is larger than the dimension of the transverse drilling hole in the vertical direction;

depositing a second metal layer on the first metal layer, the second metal layer having a melting point lower than that of the first metal layer;

releasing the sacrificial layer through the sacrificial layer release hole to obtain a device to be packaged;

and heating the device to be packaged, wherein the heating temperature is between the melting point of the second metal layer and the melting point of the first metal layer, so that the second metal layer is melted and spread, and the sacrificial layer release hole is sealed.

Further, the dimension of the transverse drilling holes in the horizontal direction is larger than the dimension of the transverse drilling holes in the vertical direction.

Further, the dimension of the transverse drilling holes in the vertical direction is 0.1-3 μm.

Further, the depositing a first metal layer at the lateral etching holes by adopting an evaporation or sputtering process comprises the following steps:

the substrate is heated, and the temperature during the heating process is lower than 400 ℃.

Further, the melting point of the first metal layer is higher than 600 ℃, and the melting point of the second metal layer ranges from 150 ℃ to 400 ℃.

Further, the surfaces of the second metal layer opposite to the first metal layer are mutually infiltrated.

Further, the thickness of the second metal layer satisfies the following relationship:

wherein H is the thickness of the second metal layer;

a is the characteristic dimension of the opening of the through hole on the upper surface of the first metal layer;

θ is the contact angle of the molten metal on the first metal layer.

Further, the thickness of the second metal layer is less than 10 μm.

Further, the heating the device to be packaged includes:

and heating the device to be packaged in a vacuum environment.

In a second aspect, embodiments of the present application disclose a packaged device that is fabricated using the packaging method as described above.

By adopting the technical scheme, the wafer level thin film packaging method and the packaging device have the following beneficial effects:

according to the wafer level thin film vacuum packaging method, the transverse drilling holes are formed in the packaging structure and used for forming self-aligned through holes in the metal layer, and sealing can be achieved by depositing a small amount of sealing metal with low melting point at the through holes. The wafer level thin film vacuum packaging method adopts the common processes of the integrated circuit and the micro-electromechanical system, adopts low-melting-point metal as sealing metal, realizes vacuum packaging by spreading and flowing the molten metal under the action of surface tension, has the melting point lower than the safe temperature which can be tolerated by the integrated circuit and the MEMS device and higher than the temperature of the subsequent packaging process, and is compatible with the metal thin film process; the melting temperature of the sealing metal layer is close to the activation temperature of the low-temperature getter, and gas is hardly discharged in the process, so that the residual gas can be absorbed by the low-temperature getter, and the compatibility with the conventional low-temperature getter process is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a wafer level thin film packaging method according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a chip wafer according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a wafer structure of a chip including a micro-mechanical structure according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart of manufacturing a chip wafer according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a substrate structure filled with dual sacrificial layers according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a wafer structure of a chip with a micro-mechanical structure according to an embodiment of the present disclosure;

FIG. 7 is a schematic view of a housing made by a micro-electroforming process according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a chip wafer with a lateral etching hole according to an embodiment of the present disclosure;

FIG. 9 is an enlarged schematic view of a sacrificial layer release hole after the first metal layer is fabricated according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a package structure after the second metal layer is manufactured according to an embodiment of the present application;

fig. 11 is a schematic enlarged partial view of a package structure after the second metal layer is manufactured according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a second metal layer according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a first metal layer after patterning according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a structure of a sacrificial layer after release according to an embodiment of the present disclosure;

FIG. 15 is a schematic view of a structure of a sacrificial layer release hole sealed after a second metal layer is melted according to an embodiment of the present disclosure;

FIG. 16 is a schematic view of a wafer structure of chips containing micromechanical structures according to one embodiment of the present application;

FIG. 17 is a schematic diagram of a large area deposited first metal layer according to one embodiment of the present application;

FIG. 18 is an enlarged schematic view of a sacrificial layer release hole according to one embodiment of the present application;

FIG. 19 is a schematic diagram of a structure of a second metal layer according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a photoresist removal structure according to one embodiment of the present application;

FIG. 21 is a schematic diagram of a structure of a patterned first metal layer according to one embodiment of the present disclosure;

FIG. 22 is a schematic diagram of a structure after photoresist removal according to one embodiment of the present application;

FIG. 23 is an enlarged schematic view of a sacrificial layer release hole according to one embodiment of the present application;

FIG. 24 is a schematic diagram of a dual-layer sacrificial layer according to one embodiment of the present application after release;

FIG. 25 is a schematic view of a structure of a sacrificial layer release hole sealed after melting a second metal layer according to one embodiment of the present application;

FIG. 26 is an enlarged schematic view of a structure of a sealed sacrificial layer release hole according to one embodiment of the present application;

FIG. 27 is a schematic structural view of a chip wafer containing micromechanical structures according to one embodiment of the present application;

FIG. 28 is a schematic diagram of a large area deposited first metal layer after gumming in accordance with one embodiment of the present application;

FIG. 29 is a schematic diagram of a first metal layer patterned structure according to one embodiment of the present disclosure;

FIG. 30 is an enlarged schematic view of the structure of a sacrificial layer release hole according to one embodiment of the present application;

FIG. 31 is a schematic diagram of a large area deposition of a second metal layer after gumming in accordance with one embodiment of the present application;

FIG. 32 is a schematic diagram of a patterned second metal layer according to one embodiment of the present disclosure;

FIG. 33 is a schematic diagram of a dual-layer sacrificial layer according to one embodiment of the present disclosure after release;

FIG. 34 is a schematic view of a structure of a sacrificial layer release hole sealed after melting a second metal layer according to one embodiment of the present application;

FIG. 35 is an enlarged schematic view of a structure of a sealed sacrificial layer release hole according to one embodiment of the present application;

FIG. 36 is a schematic structural view of a chip wafer containing micromechanical structures according to one embodiment of the present application;

FIG. 37 is a schematic view of a structure of a first metal layer according to an embodiment of the present application;

FIG. 38 is an enlarged schematic view of the structure of a sacrificial layer release hole according to one embodiment of the present application;

FIG. 39 is a schematic diagram of a structure of a second metal layer according to an embodiment of the present application;

FIG. 40 is an enlarged schematic view of the structure of a sacrificial layer release hole according to one embodiment of the present application;

FIG. 41 is a schematic diagram of a bilayer structure sacrificial layer according to one embodiment of the present application after release;

FIG. 42 is a schematic view of a sacrificial layer release hole sealed after melting a second metal layer according to one embodiment of the present application;

FIG. 43 is an enlarged schematic view of a structure of a sealed sacrificial layer release hole according to one embodiment of the present application;

FIG. 44 is a schematic structural view of a chip wafer containing micromechanical structures according to one embodiment of the present application;

FIG. 45 is a schematic diagram of a cross-drilled hole with a sacrificial layer fabricated according to one embodiment of the present application;

FIG. 46 is a schematic diagram of a structure of a first metal layer according to an embodiment of the present application;

FIG. 47 is an enlarged schematic view of the structure of a sacrificial layer release hole according to one embodiment of the present application;

FIG. 48 is a schematic diagram of a structure for lithographically depositing a second metal layer according to one embodiment of the present application;

FIG. 49 is a schematic diagram of a structure after photoresist removal according to one embodiment of the present application;

FIG. 50 is a schematic diagram of a dual-layer sacrificial layer according to one embodiment of the present application after release;

FIG. 51 is a schematic view of a structure of a sacrificial layer release hole sealed after melting a second metal layer according to one embodiment of the present application;

FIG. 52 is an enlarged schematic view of a sealed sacrificial layer release hole according to one embodiment of the present application;

the following supplementary explanation is given to the accompanying drawings:

30-packaging the holes; 301-a substrate; 302-micromechanical structure; 303-a housing; 304-transversely drilling etching holes; 305-a metal seed layer; 306-a first metal layer; 307-vias; 308-a second metal layer; 309 photoresist; 310-a sacrificial layer; 311-a first sacrificial layer; 312-a second sacrificial layer; 320-getter layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the terms "upper," "lower," "top," "bottom," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and simplicity of description, and do not indicate or imply that the apparatus or elements in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein.

Surface micromachining processes can be used for vacuum packaging. Firstly, manufacturing a sacrificial layer covering a sensitive structure and a vacuum cavity shell structure, and opening a release pore canal on the shell; then etching to remove the sacrificial layer release sensitive structure; then, blocking the release pore canal by using a surface micromachining process to form an airtight micro vacuum cavity; and finally, removing residual gas in the micro vacuum cavity by adopting methods of gas diffusion, getter absorption and the like. Because the technology of manufacturing the sacrificial layer, the vacuum cavity shell and releasing the sacrificial layer is a conventional technology of surface micromachining, the main difficulty of the surface micromachining vacuum packaging technology is two steps of plugging holes and removing residual gas. Common plugging processes based on surface micromachining include low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), metal deposition, and the like.

The LPCVD hole plugging process is similar to the Episeal process except that the LPCVD process is used instead of the epitaxial process. Because the LPCVD process temperature is usually 400-900 ℃, the process temperature is high, and the problem is similar to that of an Episeal process, namely the LPCVD process must be finished before the metal lead process of an integrated circuit, and only the silicon-based resonant structure without the metal lead can be sealed by using the process; moreover, since the micromechanical sensing structure is generally released before hole plugging, and the released micromechanical sensing structure cannot be cleaned, the LPCVD furnace tube is contaminated, so that LPCVD equipment for hole plugging cannot be used for other processes, and the expensive equipment cost makes the process difficult to popularize. Another problem with the LPCVD hole plugging process is that it is not compatible with the getter process. The non-volatile getters commonly used today are metal-containing materials and cannot enter LPCVD equipment. Therefore, only the silane-based LPCVD polysilicon plugging process can expel residual gases through subsequent hydrogen diffusion, and other LPCVD processes cannot solve the problem of residual gas removal.

The PECVD hole plugging process temperature is usually lower than 400 ℃, but the deposited material has pinholes, loose materials and air tightness. Conventional PECVD silicon dioxide and the like are non-hermetic materials. The reliability and the service life of the PECVD hole plugging process are both problematic.

The metal deposition hole plugging process comprises metal sputtering, metal evaporation and the like. Because the metal sputtering and evaporating process is low in temperature, the process temperature is compatible with a metal wiring process, a getter process and the like, and the process based on metal deposition hole plugging is expected to realize thin film vacuum packaging after integrated circuit process. However, the problem of the metal deposition plugging process is that nanoscale pores originating from the release pores occur in the metal deposition layer, the characteristic dimensions of the pores are tens to hundreds of nanometers, the lengths of the pores can reach several micrometers to nearly ten micrometers, the pores generally extend from the release pores to the upper surface of the metal layer, and nano-scale openings are formed on the upper surface of the metal layer, so that the cavity is communicated with the atmosphere, and the air tightness is difficult to realize.

As shown in fig. 1, an embodiment of the present application provides a wafer level thin film packaging method, including:

s101: and obtaining the chip wafer.

In this embodiment, the chip wafer may be any chip wafer commonly provided with a micromechanical structure 302 in the market at present; the wafer can also be a chip wafer manufactured by the prior micro-mechanical process. As shown in fig. 2, the chip wafer has a plurality of package holes 30, and the embodiment of the present application selects a cross-sectional structure of any one of the package holes 30 for illustration. The structure shown in fig. 3 is a cross-sectional view of a partial structure of the package hole 30 in fig. 2. As shown in fig. 3, the chip wafer includes a substrate 301, a sacrificial layer 310, and a housing 303, the substrate 301 is provided with a micromechanical structure 302, and the housing 303 is provided on the substrate 301 and the sacrificial layer 310. The housing 303 is used to protect the micromechanical structure 302, and when the sacrificial layer 310 is released, a vacuum cavity is formed between the housing 303 and the substrate 301, within which the micromechanical structure 302 is located.

Fig. 4 is a schematic flow chart of manufacturing a chip wafer according to an embodiment of the present application, and as shown in fig. 4, manufacturing a chip wafer includes:

s401: the micromechanical structure 302 is fabricated.

In the present embodiment, a conventional micromechanical process is used to fabricate the micromechanical structure 302, resulting in the substrate 301 including the micromechanical structure 302. The substrate 301 may be selected from a common Silicon wafer, SOI (Silicon-On-Insulator), a thin film deposited On the surface of a Silicon wafer, etc. Alternatively, the micromechanical structure 302 is fabricated on a common silicon wafer, SOI top-layer silicon, or the like using bulk micromachining processes. Alternatively, surface micromachining process is used to fabricate surface micromachining structure 302 on thin films deposited on surfaces such as silicon wafers. Alternatively, the micromechanical structure 302 is a micromechanical sensing structure, a micromechanical actuating structure or a micromechanical control structure.

S403: a sacrificial layer 310 is fabricated on a substrate 301.

In the embodiment of the present application, the sacrificial layer 310 may have a single-layer structure or a multi-layer structure. Preferably, the sacrificial layer 310 includes a first sacrificial layer 311 and a second sacrificial layer 312. As shown in fig. 5, the first sacrificial layer 311 fills the micromechanical structure 302; the second sacrificial layer 312 is disposed on the surface of the substrate 301 and the first sacrificial layer 311, and the first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure. Fabricating the sacrificial layer 310 on the substrate 301 includes: the first sacrificial layer 311 is fabricated, and the first sacrificial layer 311 serves to protect the MEMS device structure from damage during the process, and to provide a movable space for the MEMS device after the sacrificial layer 310 is released. Optionally, the method for fabricating the first sacrificial layer 311 includes: thermal oxide silicon dioxide, LPCVD silicon dioxide, PECVD silicon dioxide, spin-on organic films, and the like. After the first sacrificial layer 311 is deposited, patterning of the first sacrificial layer 311 is achieved by using photolithography, etching, and other processes. Optionally, the method of patterning the first sacrificial layer 311 includes: dry etching, wet etching, steam etching, and the like. Finally, the photoresist 309 is removed by a conventional photoresist removing process, so as to complete the fabrication of the first sacrificial layer 311. After the first sacrificial layer 311 is completed, a second sacrificial layer 312 is formed on the first sacrificial layer 311 and the substrate 301. The purpose of fabricating the second sacrificial layer 312 is to fabricate the sacrificial layer 310 with a small size to laterally drill the holes 304 to reduce the thickness of the metal layer that needs to be deposited to self-align the formation of the nano-vias 307. Optionally, the method of fabricating the second sacrificial layer 312 includes: thermal oxide silicon dioxide, LPCVD silicon dioxide, PECVD silicon dioxide, spin-on organic films, and the like. Patterning of second sacrificial layer 312 is accomplished by photolithography and etching processes after deposition of second sacrificial layer 312 is completed. Optionally, the method of patterning the second sacrificial layer 312 includes: dry etching, wet etching, steam etching, and the like. Finally, the photoresist 309 is removed using a conventional photoresist removal process, such as a plasma photoresist removal process, to complete the fabrication of the second sacrificial layer 312.

In this embodiment, the material used for fabricating the sacrificial layer 310 can be completely removed by a high-selectivity etching technique, no solid or liquid residue is left, and the etching degree of the high-selectivity etching technique for removing the sacrificial layer 310 on the housing 303 and the package structure fabricated later is less than one tenth of the thickness before etching.

S405: the housing 303 is fabricated over the sacrificial layer 310 and the substrate 301.

In this embodiment, as shown in fig. 6, after the sacrificial layer 310 is fabricated, the housing 303 is fabricated on the sacrificial layer 310 and the substrate 301, the end of the housing 303 is anchored on the substrate 301, and the remaining portion of the housing 303 is disposed on the sacrificial layer 310. The housing 303 is used to protect the micromechanical structure 302, and after release of the sacrificial layer 310, a cavity structure is formed between the housing 303 and the substrate 301, within which cavity structure the micromechanical structure 302 is located. The housing 303 deposition may be performed using LPCVD deposition, PECVD deposition, sputtering, and the like, and optionally, the deposited materials include: polysilicon, low stress silicon nitride, silicon carbide, aluminum, and the like. After the deposition of the housing 303 is completed, the patterning of the housing 303 is achieved by using processes such as photolithography and etching, and finally, a conventional photoresist removing process is used to remove the photoresist 309, thereby completing the fabrication of the housing 303. Alternatively, polysilicon is deposited by LPCVD, then the etching window of the housing 303 is exposed by photolithography, then the housing 303 is formed by reactive ion etching, and finally the photoresist 309 is removed by Piranha solution wet photoresist removal to complete the fabrication of the junction housing 303.

In some embodiments, the housing 303 may be made by the following method: first, a negative pattern of the housing 303 is formed by photolithography, then the metal housing 303 is sputtered, and finally the photoresist 309 and the metal on the photoresist 309 are removed by a conventional photoresist removing process, thereby completing the fabrication of the housing 303. Optionally, the metallic material includes: aluminum, copper, etc. In other embodiments, as shown in fig. 7, the housing 303 may also be made by: first, a metal seed layer 305 is sputtered on the sacrificial layer 310, and optionally, the material of the metal seed layer 305 is: tiW/Au, tiW/Cu, cr/Au, cr/Cu, etc. The negative pattern of the housing 303 is then lithographically formed, and then the metal housing 303 is fabricated using a micro-electroforming process, optionally with the metal housing 303 material comprising: low stress nickel, copper, etc. Photoresist 309 is removed using a conventional photoresist removal process and finally metal seed layer 305 is patterned using an etching process to complete fabrication of housing 303.

In the embodiment of the present application, the housing 303 should not be wetted with the second metal layer 308. The thickness and span design of the housing 303 should ensure that the housing 303 flexes downward to less than 50% of the thickness of the sacrificial layer 310 at a pressure of one atmosphere. The highly selective etching technique for removing the sacrificial layer 310 should etch the housing 303 less than one tenth of its pre-etch thickness.

S103: a portion of the sacrificial layer 310 is etched to form a lateral drill hole 304 between the substrate 301 and the housing 303.

In the embodiment of the present application, after the enclosure 303 is manufactured, the sacrificial layer 310 between the enclosure 303 and the substrate 301 is etched, and the lateral etching hole 304 is formed between the enclosure 303 and the substrate 301 by etching for a short time. As shown in fig. 3 and 8, the function of the lateral drilled holes 304 is to form a discontinuous interface for self-aligned fabrication of the nano-vias 307, i.e. the housing 303 is discontinuous with the substrate 301 due to the presence of the lateral drilled holes 304. To ensure that nano-scale vias 307 can be naturally formed in the subsequently fabricated first metal layer 306, the depth of the lateral drill holes 304 is greater than the height of the lateral drill holes 304. The height of the lateral drill holes 304 is the distance between the substrate 301 and the housing 303, alternatively the height of the lateral drill holes 304 is 0.1 μm-3 μm. The method used to make the lateral drilled holes 304 is essentially one time a short release of the sacrificial layer 310 using an etching process. Alternatively, the lateral drill holes 304 may be formed by wet etching, dry etching, vapor etching, and the like.

In the embodiment of the present application, the depth of the lateral etching hole 304 is slightly greater than the thickness of the sacrificial layer 310 between the housing 303 and the substrate 301 on the sacrificial layer 310, so as to ensure that the sacrificial layer 310 at the opening is completely corroded, but most of the sacrificial layer 310 should remain, so as to support the housing 303 and protect the MEMS structure, so that the whole structure can withstand the subsequent conventional cleaning process, photolithography process, metal layer manufacturing process, and the like. After the lateral drill holes 304 are formed, the entire structure should be able to withstand subsequent conventional cleaning processes, photolithography processes, metal layer forming processes, and the like. The method used to make the transverse drilled holes 304 should be such that the structural layer 303 of the vacuum housing 303 and subsequently the package structure are etched to less than one tenth of their thickness prior to etching. The method used to make the lateral drill holes 304 should not leave a solid or liquid residue that cannot be removed by cleaning and dry processes and should not affect the integrated circuit or MEMS device structure.

S105: a first metal layer 306 is deposited at the lateral drilled holes 304 using an evaporation or sputtering process, the first metal layer 306 having nano-scale vias 307, the thickness of the first metal layer 306 being greater than the dimension of the lateral drilled holes 304 in the vertical direction.

In this embodiment, after the fabrication of the lateral etching hole 304 is completed, the device is cleaned by a cleaning process, so as to remove solid or liquid residues left by the fabrication of the sacrificial layer 310 and avoid the influence of the solid or liquid residues on the structure of the integrated circuit or the MEMS device. Alternatively, the cleaning process may be integrated circuit RCA standard cleaning, organic solvent cleaning, deionized water rinsing, ultrasonic cleaning, dry plasma, etc.

In this embodiment, after the device is cleaned, the first metal layer 306 is fabricated on the housing 303 and the substrate 301 by using an evaporation or sputtering process. As shown in fig. 9, due to the presence of the lateral drill holes 304, a discontinuous interface exists between the substrate 301 and the housing 303, and when the first metal layer 306 is deposited by evaporation or sputtering, the nano-scale through holes 307 are naturally formed at the positions on the first metal layer 306 corresponding to the lateral drill holes 304. The via 307 extends from the lateral drill hole 304 up to the upper surface of the first metal layer 306, has a width equal to that of the lateral drill hole 304 at the lateral drill hole 304, and then rapidly shrinks to several tens to one hundred nanometers, after which the width is hardly changed anymore, and remains at several tens to one hundred nanometers. Its length can reach approximately ten micrometers. Since the thickness of the metal layer formed by the integrated circuit metal deposition process is generally less than 10 microns, the nano-scale via 307 does not disappear as the metal deposition conditions change. The through hole 307 communicates with the laterally drilled hole 304 to form a sacrificial layer 310 release hole, and the sacrificial layer 310 is released through the sacrificial layer 310 release hole in a subsequent sacrificial layer 310 release process.

As shown in fig. 9, in the embodiment of the present application, the first metal layer 306 is fabricated by a sputtering or evaporation process, and the nano-via 307 is formed on the first metal layer 306 by self-aligning at the lateral etching hole 304. The first metal layer 306 is formed by a sputtering or evaporation process, and the temperature of the substrate 301 heated by the evaporation or sputtering process is lower than the tolerance temperature of the device structure, and optionally, the heating temperature is lower than 400 ℃. The first metal layer 306 may be a single metal layer structure, or may be a composite structure including multiple metal layers, and contact surfaces between the multiple metal layers may or may not be mutually wetted. Optionally, the material of which the first metal layer 306 is deposited includes TiW/Cu, ni/Au, and the like. Patterning of the metal layer is achieved using photolithography and etching processes, and finally the photoresist 309 is removed, completing the fabrication of the first metal layer 306. The method of removing the photoresist 309 includes: acetone photoresist stripping, organic photoresist stripping, plasma photoresist stripping and the like. In some embodiments, the first metal layer 306 may also be fabricated by the following method: first, a negative pattern of the first metal layer 306 is formed by photolithography, then the first metal layer 306 is sputtered, and simultaneously the nano-scale sacrificial layer 310 through hole 307 is formed by self-alignment, optionally, the first metal layer 306 material comprises TiW/Cu, ni/Au, etc. Finally, the photoresist 309 and the metal on the photoresist 309 are removed by a conventional photoresist removing process, so as to complete the manufacture of the first metal layer 306.

In the embodiment of the present application, in order to enable the self-aligned formation of the nano-via 307 while depositing the first metal layer 306, a sputtering or evaporation process is used for the deposition. The melting point of the first metal layer 306 is higher than that of the second metal layer 308 which is manufactured later, and optionally, the melting point of the first metal layer 306 is higher than 600 ℃. The first metal layer 306 may be a single metal layer such as titanium, tungsten, copper, gold, nickel, chromium, etc. A composite metal layer, such as TiW/Cu, ni/Au, etc., may be used to adhere the bottom TiW, ni, etc. metal to the housing 303, and Cu, au, etc. metal on the surface provides a wetting layer with the second metal layer 308.

S107: a second metal layer 308 is deposited over the first metal layer 306, the second metal layer 308 having a melting point lower than the melting point of the first metal layer 306.

In this embodiment, as shown in fig. 10, after the first metal layer 306 is manufactured, a second metal layer 308 is deposited at the through hole 307 as the sealing metal, and the second metal layer 308 is infiltrated with the upper surface of the first metal layer 306. As shown in fig. 10, one end of the second metal layer 308 is close to the via 307, and the distance between the lower surface of the second metal layer 308 and the via 307 is determined by the photolithography process, and may be generally designed to be the minimum photolithographic line width. There are various methods for forming the second metal layer 308, as shown In fig. 11, to form the second metal layer 308, first sputtering or evaporating a metal In a large area, optionally, the material of the second metal layer 308 includes Sn, in, sn ₂ Sb ₂ S ₅ Etc. ThenPatterning of the second metal layer 308 is achieved by using photolithography and etching processes, and finally the photoresist 309 is removed, so that the second metal layer 308 is manufactured, and the manufactured second metal layer 308 cannot completely block the nano-scale through hole 307. In some embodiments, the second metal layer 308 may also be fabricated by the following method: first lithographically forming a negative pattern of the second metal layer 308, and then sputtering or evaporating the second metal layer 308, optionally the material of the second metal layer 308 comprises Sn, in, sn ₂ Sb ₂ S ₅ Etc. Finally, the photoresist 309 and the metal on the photoresist 309 are removed by a conventional photoresist removing process, and the fabrication of the second metal layer 308 is completed. In other embodiments, the second metal layer 308 may also be formed by the following method: as shown in fig. 12, first a first metal layer 306 having a continuous surface is sputtered or evaporated over a large area while self-aligned to form nano-scale metal vias 307 when the first metal layer 306 is fabricated; then, a negative pattern of the second metal layer 308 is formed by photoetching, and the photoresist 309 should completely cover the nano-scale through hole 307 so as to avoid the subsequent electroplating process from sealing the through hole 307; the second metal layer 308 is then electroplated, optionally with the material of the second metal layer 308 comprising Sn, sn-Ag-Cu alloys, or the like. The photoresist 309 is then removed using a conventional photoresist removal process to complete the fabrication of the second metal layer 308. After the second metal layer 308 is fabricated, the patterning of the first metal layer 306 is then performed by photolithography or etching, and the photoresist 309 should completely cover the through hole 307 in order to ensure that the nano-scale through hole 307 is not etched away, and the patterning of the first metal layer 306 is performed in order to ensure that the melted second metal layer 308 spreads and flows only in a specified area around the through hole 307. Finally, the photoresist 309 is removed by a conventional photoresist removing process, and patterning of the first metal layer 306 is completed. Optionally, the method used to remove the photoresist 309 includes: acetone photoresist stripping, organic photoresist stripping, plasma photoresist stripping and the like.

In this embodiment, the melting point of the second metal layer 308 is lower than that of the first metal layer 306, and the melting point of the second metal layer 308 is lower than that of all materials in the previous process and higher than the temperature of the subsequent packaging process, and optionally, the melting point of the second metal layer 308 ranges from 150 ℃ to 400 ℃. The second metal layer 308 and the upper surface of the first metal layer 306 can be mutually infiltrated, but the material of the second metal layer 308 is not infiltrated with the housing 303. The molten second metal layer 308 reacts with the first metal layer 306 to consume less than 70% of the thickness of the first metal layer 306. When the packaging structure is packaged, the second metal layer 308 is heated under vacuum, so that the second metal layer 308 is heated and melted to form molten metal, and because the second metal layer 308 is infiltrated with the surface of the first metal layer 306, the molten metal spreads on the surface of the first metal layer 306 under the action of the surface tension based on the surface energy minimum principle to automatically seal the nano through holes 307, thereby realizing wafer level thin film vacuum packaging. Since the feature size of the surface opening of the through hole 307 is in the nanometer level, based on the energy minimum principle, the surface of the melted second metal layer 308 tends to shrink, i.e. tends to be subjected to the minimum surface force, and tends to form the minimum surface, so, in order to achieve the sealing, the thickness H of the second metal layer 308 after spreading needs to satisfy:

Where H is the thickness of the second metal layer 308; a is a characteristic dimension of the opening of the through hole 307 on the upper surface of the first metal layer 306, and a is a circular diameter when the opening of the through hole 307 on the upper surface of the first metal layer 306 is approximately circular; when the opening of the via 307 on the upper surface of the first metal layer 306 is approximately rectangular, a is the length of the short side of the rectangle; when the opening of the through hole 307 on the upper surface of the first metal layer 306 is approximately elliptical, a is the length of the minor axis of the ellipse; θ is the contact angle of the molten metal on the first metal layer 306.

Because the feature size of the surface opening of the self-aligned via 307 in the first metal layer 306 is on the nanometer scale, only a very thin second metal layer 308 is required to effect the seal during the subsequent melt-sealing process. When the size of the through hole 307 is as small as several tens to one hundred nanometers, the thickness of the second metal layer 308 after spreading is only above several tens nanometers to seal the through hole 307, and optionally, the thickness of the second metal layer 308 is less than 10 μm. Since the second metal layer 308 will alloy with the first metal layer 306 during the spreading process in the molten state, the thin second metal layer 308 means that only the thin first metal layer 306 is required to ensure that the alloying process does not completely consume the first metal layer 306, thereby ensuring process reliability.

S109: and releasing the sacrificial layer 310 through the release hole of the sacrificial layer 310 to obtain the device to be packaged.

In this embodiment, as shown in fig. 14, after the second metal layer 308 is manufactured, the sacrificial layer 310 is released through the release hole of the sacrificial layer 310. Release of sacrificial layer 310 using SiO ₂ The (post-metal) wet etching process, the etching solution of which reacts with the structure of the sacrificial layer 310 through the nano through holes 307, realizes the release of the sacrificial layer 310. In some embodiments, an O-rich may also be employed ₂ The plasma etching technology process realizes the release of the sacrificial layer 310, O ₂ The plasma reacts with the structure of the sacrificial layer 310 through the nano-via 307, completing the release of the sacrificial layer 310. Fig. 14 is a schematic view of a structure of a device to be packaged, as shown in fig. 14, after the sacrificial layer 310 is released, a cavity structure is formed between the housing 303 and the micromechanical structure 302, and the micromechanical structure 302 is located in the cavity structure after the sacrificial layer 310 is released.

In the present embodiment, when the sacrificial layer 310 is completely removed, the corrosion of the housing 303, the first metal layer 306, and the second metal layer 308 by the sacrificial layer 310 release process should be less than one tenth of the thickness before the corrosion. In addition, the sacrificial layer 310 release process should be capable of completely removing the sacrificial layer 310 material, leaving no solid or liquid residues that cannot be removed by dry processes, and without affecting the integrated circuit or MEMS device structure. Alternatively, sacrificial layer 310 may be removed using a wet etch, a dry etch, a vapor etch, or the like.

S111: the device to be packaged is heated to a temperature between the melting point of the second metal layer 308 and the melting point of the first metal layer 306, so that the second metal layer 308 is melt-spread, thereby sealing the release hole of the sacrificial layer 310.

In this embodiment, as shown in fig. 15, after the sacrificial layer 310 is removed, the second metal layer 308 is heated to melt the second metal layer 308, and because the second metal layer 308 infiltrates with the surface of the first metal layer 306, the melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension thereof, so as to seal the nano through holes 307, thereby sealing the release holes of the sacrificial layer 310 and completing the packaging. The heating process may be performed in a vacuum or non-vacuum environment, and may be specifically selected according to the type of micromechanical structure 302 and the operating requirements. The melt reflow of the second metal layer 308 in the embodiments of the present application is performed in a vacuum environment, and the heating temperature in the whole process should be higher than the melting point of the second metal layer 308 and lower than the safe temperature that can be tolerated by the integrated circuit and MEMS device.

The embodiment of the application also discloses a packaging device which is prepared by adopting the packaging method.

The vacuum packaging method described in the embodiments of the present application is compatible with thin film processes and surface micromachining techniques. Since the feature size of the surface opening of the through hole 307 formed by self-aligning the first metal layer 306 is in the nanometer level, only a very thin second metal layer 308 is needed in the subsequent melt sealing process to realize the sealing. Since the second metal layer 308 will alloy with the first metal layer 306 during the melt spreading process, the thin second metal layer 308 means that only the thin first metal layer 306 is needed to ensure that the alloying process does not completely consume the first metal layer 306, thereby ensuring process reliability. The conventional surface micromachining processes are thin film processes, and the self-aligned formation of the nano-vias 307 makes this patent compatible with thin film processes and surface micromachining techniques.

The vacuum packaging method is compatible with a metal wiring process. The integrated circuits such as LPCVD, metal deposition, electroplating and the like and the common processes of a micro-electromechanical system are adopted, the second metal layer 308 with the melting point lower than the tolerable temperature of the MEMS device is adopted as sealing metal, and the melted second metal layer 308 spreads and flows under the action of surface tension to realize vacuum packaging, so that the vacuum packaging is compatible with a metal film process. Thus, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) metal wiring and other metal structures can be completed prior to fabrication of the first metal layer 306. The vacuum sealing process from making the first metal layer 306 to the second metal layer 308 melt seal is a Post-CMOS process.

The vacuum packaging method described in the embodiments of the present application is compatible with conventional low temperature getter processes. The second metal layer 308 melts at a temperature close to the low temperature getter activation temperature and little gas is evolved during the process, so a low temperature getter can be used to effect the gettering of residual gases.

Based on the above alternative embodiments, four alternative examples are presented below.

Example 1:

in this embodiment, the sacrificial layer 310 is thermally oxidized SiO ₂ The outer shell 303 is made of LPCVD polysilicon, the sacrificial layer 310 is transversely drilled with a SiO2 (pre-metal) wet etching process, the first metal layer 306 is made of metal sputtered TiWu/Cu, the self-alignment is formed into a nano through hole 307, and the second metal layer 308 is made of electroplated lead-free tin. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 16, the micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Fabricating a dual-layer sacrificial layer 310 structure: as shown in FIG. 16, the dual sacrificial layer 310 structure employs thermally oxidized SiO ₂ The preparation method comprises the steps of firstly adopting thermal oxidation of SiO ₂ The first sacrificial layer 311 is fabricated by photolithography, siO ₂ Patterning of the first sacrificial layer 311 is achieved by a (pre-metal) wet etching process, and the photoresist 309 is removed by a plasma photoresist removal process, so that the fabrication of the first sacrificial layer 311 is completed. Then thermally oxidizing SiO ₂ And manufacturing the second sacrificial layer 312, patterning the second sacrificial layer 312 by using photoetching and dry etching processes, and finally removing the photoresist 309 by using a plasma photoresist removing process to finish manufacturing the second sacrificial layer 312. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a shell 303: as shown in fig. 16, the shell 303 is first deposited with polysilicon by an LPCVD process, then the etching window of the shell 303 is exposed by a photolithography technique, then the shell 303 is fabricated and formed by a reactive ion etching technique, and finally the photoresist 309 is removed by a Piranha solution wet photoresist removing process, thereby completing the fabrication of the shell 303.

Making a transverse drilling hole 304: as shown in FIG. 16, the lateral etch holes 304 are formed of SiO ₂ The (pre-metal) wet etching process is performed, and the transverse undercut depth of the sacrificial layer 310 is slightly larger than the depth of the sacrificial layer 310 at the opening through short-time etching, so that the sacrificial layer 310 at the opening is completely etched completely, most of the sacrificial layer 310 is reserved, a support is provided for a structural layer, the MEMS structure is protected, and the whole structure can withstand the subsequent conventional cleaning process, photoetching process, metal layer manufacturing process and the like.

Cleaning: the cleaning process uses deionized water to rinse and remove solid or liquid residues left after the sacrificial layer 310 is laterally drilled and etched in the hole 304 is completed, so as to avoid the influence of the solid or liquid residues on the structure of the integrated circuit or the MEMS device.

A first metal layer 306 is deposited: as shown in fig. 17 and 18, the first metal layer 306 is formed by first large area sputtering of TiWu/Cu with continuous surface and self-alignment to form the nano-vias 307, and the first metal layer 306 is overlaid on the housing 303 and the substrate 301.

A second metal layer 308 for sealing is made: as shown in fig. 19 and 20, the second metal layer 308 uses the first metal layer 306 deposited in a large area in the above step as a seed layer, and the material is TiWu/Cu; then, a negative pattern of the second metal layer 308 is formed by photolithography, and lead-free tin is electroplated by an electroplating process, the photoresist 309 is required to completely cover the nano through holes 307 in order to avoid the nano through holes 307 being closed by the electroplating process, and finally, the photoresist 309 is removed by an acetone photoresist removing process, so as to form the second metal layer 308.

Patterning the first metal layer 306: in this embodiment, since the second metal layer 308 is formed by electroplating and the first metal layer 306 is used as a seed layer, the first metal layer 306 is continuous. The first metal layer 306 and the second metal layer 308 are mutually infiltrated, if the first metal layer 306 is not patterned, the second metal layer 308 will flow on the surface of the first metal layer 306 after being melted, so that the first metal layer 306 needs to be patterned, so that the second metal layer 308 can only spread to seal the nano through holes 307 in a limited area. As shown in fig. 21, the patterning of the first metal layer 306 is performed by first etching the first metal layer 306 by photolithography or plasma, the photoresist 309 needs to completely cover the nano-via 307 in this step to avoid the removal of the nano-via 307 by the plasma etching process, and finally removing the photoresist 309 by the acetone photoresist removing process, thereby completing the patterning of the first metal layer 306. As shown in fig. 22 and 23, a certain space is formed between the second metal layer 308 and the via 307 by photolithography.

Sacrificial layer 310 releases: as shown in fig. 24, the release of the sacrificial layer 310 adopts a SiO2 (post-metal) wet etching process, and the etching solution thereof reacts with the double-layer sacrificial layer 310 structure through the nano through holes 307 to realize the release of the sacrificial layer 310.

And melting, reflowing and sealing the second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 25 and 26, the melting conditions of the sealing second metal layer 308 are: (1) a vacuum environment; (2) temperatures above 235 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension, and automatically seals the nano through holes 307.

Example 2:

in this embodiment, the sacrificial layer 310 is made of LPCVD silicon dioxide, the housing 303 is made of micro-electroformed low-stress Ni, and the transverse etching holes 304 on the sacrificial layer 310 are made of SiO ₂ The (post-metal) wet etching process is performed, the first metal layer 306 is made of metal evaporated Ni/Au, the nano-via 307 is formed by self-alignment, and the second metal layer 308 is made of metal sputtered Sn. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 27, the micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Fabricating a dual-layer sacrificial layer 310 structure: as shown in FIG. 27, the dual-layer sacrificial layer 310 is fabricated using LPCVD silicon dioxide, first LPCVD SiO ₂ First sacrificial layer 311 is fabricated using photolithography/SiO ₂ Patterning of the first sacrificial layer 311 is achieved by a (pre-metal) wet etching process, and the photoresist 309 is removed by a plasma photoresist removal process, so that the fabrication of the first sacrificial layer 311 is completed. Then use LPCVD SiO ₂ Second sacrificial layer 312 is fabricated, patterning of second sacrificial layer 312 is achieved using photolithography/dry etching processes, and finally plasma is employedThe sub-photoresist removal process removes the photoresist 309, completing the fabrication of the second sacrificial layer 312. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a shell 303: as shown in fig. 27, the shell 303 is formed by first sputtering a metal seed layer 305, then photo-etching to form a negative pattern of the shell 303, then micro-electroforming a low stress nickel process to form the metal shell 303, and finally removing the photoresist 309 by an acetone photoresist removing technique to complete the manufacture of the shell 303. The nickel surface tends to form a dense oxide film in the moist air that is non-wetting with the subsequent seal second metal layer 308.

The lateral drilled holes 304 of the sacrificial layer 310 are made: as shown in FIG. 27, the lateral etch holes 304 in the sacrificial layer 310 are formed using SiO ₂ And (after metal) wet etching process.

Manufacturing a first metal layer 306: as shown in fig. 28, the first metal layer 306 is first formed into a negative pattern of the first metal layer 306 by using a photolithography technique, then the first metal layer 306 is deposited by using a metal evaporation Ni/Au process, and the nano-via 307 is formed by self-alignment, and finally the photoresist 309 and the metal layer on the photoresist 309 are removed by using an acetone photoresist removing process, thereby completing the fabrication of the first metal layer 306. As shown in fig. 29 and 30, a nano-scale via 307 is naturally formed on the first metal layer 306.

A second metal layer 308 for sealing is made: as shown in fig. 31 and 32, the second metal layer 308 is first formed into a negative pattern of the second metal layer 308 by using a photolithography technique, then the second metal layer 308 is deposited by using metal sputtering Sn, and finally the photoresist 309 and the metal layer on the photoresist 309 are removed by using an acetone photoresist removing process, thereby completing the fabrication of the second metal layer 308.

Sacrificial layer 310 releases: as shown in FIG. 33, the release of sacrificial layer 310 uses SiO ₂ (post-metal) wet etching process, wherein etching solution passes through nano through hole 307 and double-layer sacrificial layer 310 structureThe reaction, effecting release of the sacrificial layer 310.

And melting, reflowing and sealing the second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 34 and 35, the melting conditions of the sealing second metal layer 308 are: (1) a vacuum environment; (2) temperatures above 235 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension, and the nano through holes 307 are automatically sealed.

Example 3:

in this embodiment, the sacrificial layer 310 is made of PECVD silicon dioxide, the housing 303 is made of PECVD polysilicon, the transverse drilled hole 304 of the sacrificial layer 310 is made of SiO2 (pre-metal) wet etching, the first metal layer 306 is made of metal sputtered Ni/Au, and the self-aligned nano-via 307 is formed, and the second metal layer 308 is made of metal sputtered In. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 36, the micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Fabricating a dual-layer sacrificial layer 310 structure: as shown in fig. 36, the dual-layer sacrificial layer 310 is formed of PECVD silicon dioxide, first PECVD SiO ₂ The first sacrificial layer 311 is manufactured, patterning of the first sacrificial layer 311 is achieved by using a photoetching/SiO 2 (pre-metal) wet etching process, and finally photoresist 309 is removed by using a plasma photoresist removing process, so that the manufacturing of the first sacrificial layer 311 is completed. Then PECVD SiO is adopted ₂ The second sacrificial layer 312 is fabricated, patterning of the second sacrificial layer 312 is then achieved by using a photolithography/dry etching process, and finally, photoresist 309 is removed by using a plasma photoresist removing process, thereby completing fabrication of the second sacrificial layer 312. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a shell 303: as shown in fig. 36, the housing 303 is first deposited with polysilicon by PECVD, and then patterning of the housing 303 is achieved using a photolithography/reactive ion etching process; finally, photoresist 309 is removed by an acetone photoresist removal process, thereby completing the fabrication of housing 303.

The lateral drilled holes 304 of the sacrificial layer 310 are made: as shown in fig. 36, the lateral drill holes 304 are made using a SiO2 (pre-metal) wet etching process.

Manufacturing a first metal layer 306: as shown in fig. 37 and 38, the first metal layer 306 is formed by first sputtering Ni/Au and self-aligning to form the nano-via 307; then, exposing the etching window of the first metal layer 306 by using a photolithography technique, wherein the photoresist 309 needs to completely cover the nano through hole 307 so as to avoid removing the nano through hole 307 by a plasma etching process; finally, removing Ni/Au at the corrosion window by using a plasma etching technology, and removing the photoresist 309 by using an acetone photoresist removing technology to finish the manufacture of the first metal layer 306.

Making the second metal layer 308 for sealing: as shown In fig. 39 and 40, the second metal layer 308 is formed by first sputtering In and self-aligning to form the nano-via 307; then, exposing the etching window of the second metal layer 308 by using a photolithography technique, wherein the photoresist 309 needs to completely cover the nano through hole 307 so as to avoid removing the nano through hole 307 by a plasma etching process; finally, removing In at the corrosion window by using a plasma etching technology, and removing the photoresist 309 by using an acetone photoresist removing technology to finish the manufacture of the second metal layer 308.

Sacrificial layer 310 releases: as shown in FIG. 41, the release of the sacrificial layer 310 employs SiO ₂ The (post-metal) wet etching process, the etching solution reacts with the sacrificial layer 310 through the nano-via 307, and the release of the double-layer sacrificial layer 310 is realized.

And melting, reflowing and sealing the second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 42 and 43, the melting conditions of the sealing second metal layer 308 are: (1) a vacuum environment; (2) temperatures above 157 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension, and the nano through holes 307 are automatically sealed.

Example 4:

in this embodiment, the sacrificial layer 310 is made of polyimide PI2610, the getter layer 320 is made of metal sputtered Ti, and the housing 303 is made of LPCVD nitrogen Silicon carbide is manufactured, and the sacrificial layer 310 is transversely drilled with an etching hole 304 by O ₂ The first metal layer 306 is made by metal evaporation Ni/Au and is self-aligned to form the nano through holes 307, and the second metal layer 308 is made by sputtering Sn. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 44, the micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Fabricating a dual-layer sacrificial layer 310 structure: as shown in fig. 44, the double-layer sacrificial layer 310 is made of polyimide PI2610, and the polyimide PI2610 is spin-coated first, and part of the solvent is removed by two times of baking, so that the double-layer sacrificial layer is more stable, and the baking conditions are respectively baking at 90 ℃ for 3 minutes and 180 ℃ for 90 seconds; then placing the mixture into a nitrogen environment at 400 ℃ for curing; then depositing a SiC layer as a hard mask for etching the sacrificial layer 310; then etching the SiC layer and the polyimide PI2610 layer by using a photoetching technology and an Alcatel GIR300 fluorine etching machine, wherein the etching of the SiC layer adopts CF4, SF6 and O ₂ The polyimide PI2610 adopts O ₂ Etching by using plasma; then removing the photoresist 309 with acetone; and removing the residual SiC layer by using an Alcatel GIR300 fluorine etching machine to finish the manufacture of the first sacrificial layer 311. Finally, a second sacrificial layer 312 is formed, and the second sacrificial layer 312 is formed by the same method as the first sacrificial layer 311. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Making a getter layer 320: as shown in fig. 44, the getter layer 320 is formed by first sputtering Ti and then exposing the etch window of the getter layer 320 using photolithography; finally, ti at the corrosion window is removed by using a plasma etching technology, and photoresist 309 is removed by using an acetone photoresist removing technology, so that the manufacture of the getter layer 320 is completed.

Manufacturing a shell 303: as shown in fig. 44, the shell 303 is first deposited with low stress silicon nitride by a PECVD process, then the etching window of the shell 303 is exposed by a photolithography technique and the shell 303 is fabricated and formed by a reactive ion etching technique, and finally the photoresist 309 is removed by an acetone photoresist removing process, thereby completing the fabrication of the shell 303.

Fabrication of sacrificialLateral drilling of the layer 310 etches 304: as shown in FIG. 45, the lateral etch holes 304 of the sacrificial layer 310 are drilled with O ₂ The plasma etching technology is used for manufacturing, and the transverse undercut depth of the sacrificial layer 310 is slightly larger than the depth of the sacrificial layer 310 at the opening by short-time etching, so that the sacrificial layer 310 at the opening is completely corroded completely, most of the sacrificial layer 310 is reserved, the structural layer is supported and protected, and the whole structure can withstand the subsequent conventional cleaning process, photoetching process, metal layer manufacturing process and the like.

Manufacturing a first metal layer 306: as shown in fig. 46 and 47, first metal layer 306 first evaporates Ni/Au with metal and self-aligns to form nano-scale metal sacrificial layer 310 via 307; then, exposing the etching window of the first metal layer 306 by using a photolithography technique, wherein the photoresist 309 needs to completely cover the nano through hole 307 so as to avoid removing the nano through hole 307 by a plasma etching process; finally, removing Ni/Au at the corrosion window by adopting a plasma etching technology, and removing photoresist 309 by adopting an acetone photoresist removing technology to finish the manufacture of the first metal layer 306.

Making the second metal layer 308 for sealing: as shown in fig. 48 and 49, the second metal layer 308 is formed by first forming a negative pattern of the second metal layer 308 by photolithography, then forming the second metal layer 308 by sputtering Sn, and finally removing the photoresist 309 and the metal layer on the photoresist 309 by acetone photoresist removing process, thereby completing the manufacture of the second metal layer 308.

Sacrificial layer 310 releases: as shown in fig. 50, release of sacrificial layer 310 employs O-rich ₂ Plasma etching technology process implementation, O ₂ The plasma reacts with the bilayer sacrificial layer 310 structure through the nano-vias 307, completing the release of the sacrificial layer 310.

And melting, reflowing and sealing the second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 51 and 52, the melting conditions of the sealing second metal layer 308 are: (1) a vacuum environment; (2) temperatures above 235 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension, and the nano through holes 307 are automatically sealed.

The foregoing description of the preferred embodiments of the present application is not intended to limit the invention to the particular embodiments of the present application, but to limit the scope of the invention to the particular embodiments of the present application.

Claims

1. A wafer level thin film packaging method, comprising:

fabricating a micromechanical structure (302) in a substrate (301);

-fabricating a sacrificial layer (310) on the substrate (301); the sacrificial layer (310) is manufactured on the surface of the substrate (301) and fills the micromechanical structure (302);

-fabricating a housing (303) over the sacrificial layer (310) and the substrate (301); the sacrificial layer (310) comprises a first sacrificial layer (311) and a second sacrificial layer (312), the first sacrificial layer (311) fills the micromechanical structure (302), and the second sacrificial layer (312) is arranged on the surfaces of the substrate (301) and the first sacrificial layer (311);

Etching a sacrificial layer (310) between the housing (303) and the substrate (301), forming a lateral drill (304) between the substrate (301) and the housing (303); the depth of the lateral drill holes (304) is greater than the height of the lateral drill holes (304);

depositing a first metal layer (306) at the position of the transverse drilling hole (304) by adopting an evaporation or sputtering process, heating the substrate (301), wherein the temperature in the heating process is lower than 400 ℃, a nano-scale through hole (307) is formed in the first metal layer (306) in a self-alignment manner, the through hole (307) is communicated with the transverse drilling hole (304) to form a sacrificial layer (310) release hole, and the thickness of the first metal layer (306) is larger than the dimension of the transverse drilling hole (304) in the vertical direction;

depositing a second metal layer (308) at the through hole (307), wherein the second metal layer is deposited on the first metal layer (306), the melting point of the second metal layer (308) is lower than that of the first metal layer (306), the melting point of the first metal layer (306) is higher than 600 ℃, and the melting point of the second metal layer (308) ranges from 150 ℃ to 400 ℃; -the second metal layer (308) is mutually infiltrated with the surface opposite to the first metal layer (306);

The thickness of the second metal layer (308) satisfies the following relationship:

wherein H is the thickness of the second metal layer (308);

a is the characteristic dimension of the opening of the through hole (307) on the upper surface of the first metal layer (306);

θ is the contact angle of the molten metal on the first metal layer (306);

releasing the sacrificial layer (310) through the sacrificial layer (310) release hole to obtain a device to be packaged;

and heating the device to be packaged under vacuum, wherein the heating temperature is between the melting point of the second metal layer (308) and the melting point of the first metal layer (306), so that the melted second metal layer (308) spreads and flows on the surface of the first metal layer (306) under the action of surface tension, and the through holes (307) are automatically sealed.

2. The packaging method according to claim 1, characterized in that the dimension of the lateral drill holes (304) in the horizontal direction is larger than the dimension of the lateral drill holes (304) in the vertical direction.

3. The packaging method according to claim 2, characterized in that the dimension of the lateral drill holes (304) in the vertical direction is 0.1-3 μm.

4. The packaging method according to claim 1, characterized in that the thickness of the second metal layer (308) is less than 10 μm.

5. The packaging method of claim 1, wherein the heating the device to be packaged comprises:

and heating the device to be packaged in a vacuum environment.

6. A packaged device prepared by the packaging method of any one of claims 1-5.