CN111792621A

CN111792621A - Wafer-level film packaging method and packaging device

Info

Publication number: CN111792621A
Application number: CN202010640709.3A
Authority: CN
Inventors: 钟朋; 裴彬彬; 孙珂; 杨恒; 李昕欣
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2020-10-20
Anticipated expiration: 2040-07-06
Also published as: CN111792621B

Abstract

The invention relates to the technical field of micro-electromechanical packaging, in particular to a wafer-level film packaging method and a packaging device, which comprise the following steps: obtaining a chip wafer; etching part of the sacrificial layer to form a transverse drilled etching hole between the substrate and the shell; depositing a first metal layer at the transverse undercut hole by adopting an evaporation or sputtering process, wherein the first metal layer is provided with a through hole with a nanoscale; depositing a second metal layer on the first metal layer; releasing the sacrificial layer through the sacrificial layer release hole to obtain a device to be packaged; and heating the device to be packaged at a temperature between the melting point of the second metal layer and the melting point of the first metal layer, so that the second metal layer is melted and spread, and the sacrificial layer release hole is sealed. By providing a lateral underetched hole in the package structure for forming a self-aligned via in the metal layer, sealing can be achieved by depositing a small amount of low melting point sealing metal in the via.

Description

Wafer-level film packaging method and packaging device

Technical Field

The invention relates to the technical field of micro-electromechanical packaging, in particular to a wafer-level film packaging method and a packaging device.

Background

Micro-Electro-Mechanical systems (MEMS) sensors achieve a high degree of functional integration by reducing the size of sensitive structures. The air resistance is related to the size of the structural feature, the air resistance of a macro-scale object is generally negligible at low speed, but in the MEMS sensor with small structural feature size, the air resistance is a main damping mechanism of an MEMS device, and the Q value of the sensor is determined, so that the amplitude-frequency characteristic, the phase-frequency characteristic and the bandwidth of the sensor are significantly influenced. Meanwhile, brownian motion noise caused by thermal fluctuation of gas molecules is also the main noise of MEMS devices such as acceleration sensors and gyros. The vacuum packaging technology can obviously reduce air damping loss. Therefore, vacuum packaging is of great significance for a variety of MEMS devices.

The only surface micro-mechanical vacuum packaging technology that has been commercially implemented at present is the epitaxial vacuum packaging (Episeal) technology. The technology utilizes the characteristic that the epitaxial growth polycrystalline silicon layer blocks the through hole to form an airtight vacuum cavity, utilizes the characteristic that residual gas generated by the epitaxial process is hydrogen which can diffuse through a solid structure, and utilizes the thermal annealing process after packaging to diffuse the hydrogen out of the airtight cavity to form high-reliability high-vacuum packaging. The process has been used in the manufacture of some special sensors, such as high precision pressure sensors, MEMS oscillators, etc., that do not require metal wiring to be fabricated prior to vacuum packaging.

The problem of the Episeal process is that a high-temperature epitaxial process is required to block the holes in the process, the temperature is up to 980 ℃, and the high-temperature process strictly prohibits all metal materials from entering, so that the process is only suitable for being manufactured by adopting homogeneous silicon materials individually, and a sensor with metal wiring is not required to be manufactured before packaging. The general MEMS sensor needs to be manufactured with metal wiring before packaging, and the process cannot be adopted for vacuum packaging. In addition, the MEMS structure is released when epitaxial polysilicon hole plugging is carried out, and a wafer cannot be cleaned before an epitaxial process, so that sacrificial layer corrosion equipment and epitaxial equipment are required to be special, and the equipment investment is large and the process cost is high.

Disclosure of Invention

The invention aims to solve the technical problems that the existing micromechanical vacuum packaging technology has high process temperature and complex process.

In order to solve the above technical problem, in a first aspect, an embodiment of the present application discloses a wafer level thin film packaging method, including:

obtaining a chip wafer, wherein the chip wafer comprises a substrate, a sacrificial layer and a shell, a micro-mechanical structure is arranged on the substrate, and the sacrificial layer is arranged between the micro-mechanical structure and the shell;

etching part of the sacrificial layer to form a transverse drilled etching hole between the substrate and the shell;

depositing a first metal layer at the transverse drilled and etched hole by adopting an evaporation or sputtering process, wherein the first metal layer is provided with a through hole with a nanoscale, the through hole is communicated with the transverse drilled and etched hole to form a sacrificial layer release hole, and the thickness of the first metal layer is larger than the size of the transverse drilled and etched hole in the vertical direction;

depositing a second metal layer on the first metal layer, the second metal layer having a melting point lower than the melting point of the first metal layer;

releasing the sacrificial layer through the sacrificial layer release hole to obtain a device to be packaged;

and heating the device to be packaged at a temperature between the melting point of the second metal layer and the melting point of the first metal layer, so that the second metal layer is melted and spread, and the sacrificial layer release hole is sealed.

Further, the size of the transverse drilled and etched hole in the horizontal direction is larger than the size of the transverse drilled and etched hole in the vertical direction.

Further, the size of the transverse drilled and etched hole in the vertical direction is 0.1-3 μm.

Further, the depositing a first metal layer at the lateral undercut hole by using an evaporation or sputtering process includes:

heating the substrate, wherein the temperature in the heating process is lower than 400 ℃.

Further, the melting point of the first metal layer is higher than 600 ℃, and the melting point of the second metal layer ranges from 150 ℃ to 400 ℃.

Furthermore, the surfaces of the second metal layer opposite to the first metal layer are mutually wetted.

Further, the thickness of the second metal layer satisfies the following relationship:

wherein H is the thickness of the second metal layer;

a is the characteristic dimension of the opening of the through hole on the upper surface of the first metal layer;

θ is a contact angle of the molten metal liquid on the first metal layer.

Further, the thickness of the second metal layer is less than 10 μm.

Further, the heating the device to be packaged includes:

and heating the device to be packaged in a vacuum environment.

In a second aspect, an embodiment of the present application discloses a packaged device, which is prepared by using the packaging method described above.

By adopting the technical scheme, the wafer-level film packaging method and the packaging device have the following beneficial effects:

according to the wafer-level film vacuum packaging method, the transverse drilled and etched hole is formed in the packaging structure and used for forming the self-aligned through hole in the metal layer, and sealing can be achieved through a small amount of sealing metal with a low melting point deposited in the through hole. The wafer-level film vacuum packaging method adopts the common processes of an integrated circuit and a micro electro mechanical system, adopts low-melting-point metal as sealing metal, realizes vacuum packaging by spreading and flowing the molten metal under the action of surface tension, has the melting point lower than the safe temperature which can be endured by the integrated circuit and the MEMS device and higher than the temperature of the subsequent packaging process, and is compatible with a metal film process; the melting temperature of the sealing metal layer is close to the activation temperature of the low-temperature getter, and gas is hardly discharged in the process, so that the residual gas can be absorbed by the low-temperature getter, and the compatibility with the conventional low-temperature getter process is realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic flowchart of a wafer-level thin film encapsulation method according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a chip wafer according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a chip wafer structure including a micro-mechanical structure according to an embodiment of the present disclosure;

fig. 4 is a schematic view of a process for manufacturing a chip wafer according to an embodiment of the present disclosure;

FIG. 5 is a schematic view of a substrate filled with dual sacrificial layers according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a chip wafer structure including a micro-mechanical structure according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a housing fabricated by a micro electroforming process according to an embodiment of the present disclosure;

fig. 8 is a diagram illustrating a chip wafer structure for etching a lateral via hole according to an embodiment of the present disclosure;

fig. 9 is an enlarged structural view of a sacrificial layer release hole after a first metal layer is manufactured according to an embodiment of the present disclosure;

fig. 10 is a schematic view of a package structure after a second metal layer is completely formed according to an embodiment of the present disclosure;

fig. 11 is a partially enlarged schematic view of a package structure after a second metal layer is manufactured according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram illustrating a second metal layer according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a patterned first metal layer according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a released sacrificial layer according to an embodiment of the present disclosure;

FIG. 15 is a schematic structural diagram of a sacrificial layer release hole sealed after a second metal layer is melted according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of a chip wafer structure including a micromechanical structure according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a large area deposition of a first metal layer according to one embodiment of the present application;

FIG. 18 is an enlarged structural view of a sacrificial layer release hole according to an embodiment of the present application;

FIG. 19 is a schematic diagram of a second metal layer according to one embodiment of the present application;

FIG. 20 is a schematic view of the structure after photoresist removal according to one embodiment of the present application;

FIG. 21 is a schematic diagram of a patterned first metal layer according to one embodiment of the present application;

FIG. 22 is a schematic view of the structure after photoresist removal according to one embodiment of the present application;

FIG. 23 is an enlarged structural view of a sacrificial layer release hole according to an embodiment of the present application;

FIG. 24 is a schematic structural diagram of a bilayer structure after release of a sacrificial layer according to one embodiment of the present application;

FIG. 25 is a schematic view of a sacrificial layer release hole being sealed after melting of a second metal layer according to an embodiment of the present application;

FIG. 26 is an enlarged schematic view of a sacrificial layer release hole being encapsulated in accordance with an embodiment of the present application;

FIG. 27 is a schematic structural view of a chip wafer containing micromechanical structures according to one embodiment of the present application;

FIG. 28 is a schematic diagram of a large area deposition of a first metal layer after glue application according to one embodiment of the present application;

FIG. 29 is a schematic view of a first metal layer patterning structure according to one embodiment of the present application;

FIG. 30 is an enlarged schematic view of a sacrificial layer release hole according to an embodiment of the present application;

FIG. 31 is a schematic view of a large area deposited second metal layer after glue application according to an embodiment of the present application;

FIG. 32 is a schematic diagram illustrating a patterned second metal layer according to one embodiment of the present application;

FIG. 33 is a schematic diagram illustrating a released sacrificial layer of a dual-layer structure in accordance with one embodiment of the present application;

FIG. 34 is a schematic view of a sacrificial layer release hole being sealed after melting of a second metal layer according to an embodiment of the present application;

FIG. 35 is an enlarged schematic view of a sacrificial layer release hole being encapsulated in accordance with an embodiment of the present application;

FIG. 36 is a schematic structural view of a chip wafer containing micromechanical structures according to one embodiment of the present application;

FIG. 37 is a schematic diagram of a structure in which a first metal layer is formed, according to one embodiment of the present application;

FIG. 38 is an enlarged structural view of a sacrificial layer release hole according to an embodiment of the present application;

FIG. 39 is a schematic diagram of a second metal layer according to one embodiment of the present application;

FIG. 40 is an enlarged schematic view of a sacrificial layer release hole according to an embodiment of the present application;

FIG. 41 is a schematic diagram illustrating a released sacrificial layer of a dual-layer structure according to an embodiment of the present application;

FIG. 42 is a schematic view of a sacrificial layer release hole being sealed after melting of a second metal layer according to an embodiment of the present application;

FIG. 43 is an enlarged schematic view of a sacrificial layer release hole being encapsulated in accordance with an embodiment of the present application;

FIG. 44 is a schematic structural diagram of a chip wafer containing micromechanical structures according to one embodiment of the present application;

FIG. 45 is a schematic diagram of a lateral via hole structure with a sacrificial layer formed in accordance with one embodiment of the present application;

FIG. 46 is a schematic diagram of a structure in which a first metal layer is formed, according to one embodiment of the present application;

FIG. 47 is an enlarged schematic view of a sacrificial layer release hole according to an embodiment of the present application;

FIG. 48 is a schematic diagram of a structure for lithographically depositing a second metal layer in accordance with one embodiment of the present application;

FIG. 49 is a schematic view of the structure after removal of the photoresist according to one embodiment of the present application;

FIG. 50 is a schematic diagram illustrating a released structure of a sacrificial layer of a dual-layer structure according to an embodiment of the present application;

FIG. 51 is a schematic view of a sacrificial layer release hole being sealed after melting of a second metal layer according to an embodiment of the present application;

FIG. 52 is an enlarged schematic view of a sacrificial layer release hole being encapsulated in accordance with an embodiment of the present application;

the following is a supplementary description of the drawings:

30-packaging holes; 301-a substrate; 302-a micromechanical structure; 303-a housing; 304-transversely drilling and etching holes; 305-a metal seed layer; 306-a first metal layer; 307-via holes; 308-a second metal layer; 309-photoresist; 310-a sacrificial layer; 311-a first sacrificial layer; 312 — a second sacrificial layer; 320-getter layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

Surface micromachining processes may be used for vacuum packaging. Firstly, manufacturing a sacrificial layer covering a sensitive structure and a vacuum cavity shell structure, and forming a release pore channel on the shell; then corroding and removing the sacrificial layer release sensitive structure; then, blocking the release pore passage by using a surface micro-mechanical process to form an airtight micro-vacuum cavity; and finally, removing residual gas in the micro vacuum cavity by methods such as gas diffusion, getter absorption and the like. As the sacrificial layer, the vacuum cavity shell and the sacrificial layer release technology are conventional processes of surface micro-machinery, the main difficulty of the surface micro-machinery vacuum packaging technology is two steps of hole plugging and residual gas removal. Common hole plugging processes based on surface micromachining include Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), metal Deposition, and the like.

The LPCVD via plugging process is similar to the Episeal process except that an LPCVD process is used instead of an epitaxial process. Because the temperature of the LPCVD process is usually between 400 ℃ and 900 ℃, the process temperature is high, the problem is similar to that of the Episeal process, namely the LPCVD process is completed before the metal lead process of the integrated circuit, and only the silicon-based resonant structure without the metal lead can be sealed by using the LPCVD process; in addition, because the micromechanical sensing structure is generally released before hole plugging, and the released micromechanical sensing structure cannot be cleaned, the LPCVD furnace tube is contaminated, the LPCVD equipment for the hole plugging process cannot be used for other processes, and the process is difficult to popularize due to expensive equipment cost. Another problem with LPCVD via plugging processes is incompatibility with getter processes. The non-volatile getters commonly used at present all contain metal materials, and cannot enter LPCVD equipment. Therefore, only the silane-based LPCVD polysilicon hole plugging process can drive off the residual gas through the subsequent hydrogen diffusion, and other LPCVD processes cannot solve the problem of removing the residual gas.

Although the temperature of the PECVD hole blocking process is usually lower than 400 ℃, the deposited material has pinholes, the material is loose, and the material has the problem of air tightness. Commonly used PECVD silicon dioxide and the like are non-hermetic materials. The reliability and the service life of the PECVD hole plugging process are both problematic.

The metal deposition hole plugging process comprises metal sputtering, metal evaporation and the like. Because the technological temperature of metal sputtering and evaporation is low, the technological temperature is compatible with a metal wiring technology, a getter technology and the like, and the thin film vacuum packaging after the integrated circuit technology is hopefully realized by the technology based on metal deposition hole plugging. However, the problem of the metal deposition pore-blocking process is that a nano-scale pore channel originated from a release pore channel appears in the metal deposition layer, the characteristic dimension of the pore channel is dozens to one hundred nanometers, the length of the pore channel can reach several micrometers to nearly ten micrometers, the pore channel generally extends from the release pore channel to the upper surface of the metal layer, and a nano-scale opening is formed on the upper surface of the metal layer, so that the cavity is communicated with the atmosphere, and the air tightness is difficult to realize.

As shown in fig. 1, an embodiment of the present application provides a wafer level thin film encapsulation method, including:

s101: and obtaining a chip wafer.

In the embodiment of the present application, the chip wafer may be any common chip wafer on the market at present, which is provided with the micro mechanical structure 302; the wafer can also be a chip wafer manufactured by the existing micro-mechanical process. As shown in fig. 2, a plurality of package holes 30 are formed on the chip wafer, and the cross-sectional structure of any one package hole 30 is selected for illustration in the embodiment of the present application. The structure shown in fig. 3 is a cross-sectional view of a portion of the package aperture 30 of fig. 2. As shown in fig. 3, the chip wafer includes a substrate 301, a sacrificial layer 310, and a housing 303, where the substrate 301 is provided with a micro-mechanical structure 302, and the housing 303 is disposed on the substrate 301 and the sacrificial layer 310. The housing 303 is used to protect the micromechanical structure 302, and when the sacrificial layer 310 is released, a vacuum cavity is formed between the housing 303 and the substrate 301, and the micromechanical structure 302 is located in the vacuum cavity.

Fig. 4 is a schematic flow chart of manufacturing a chip wafer according to an embodiment of the present application, and as shown in fig. 4, the manufacturing of the chip wafer includes:

s401: a micromechanical structure 302 is fabricated.

In the embodiment of the present application, the micro-mechanical structure 302 is fabricated by a conventional micro-mechanical process, and the substrate 301 including the micro-mechanical structure 302 is obtained. The substrate 301 may be a common Silicon wafer, an SOI (Silicon-On-Insulator), a thin film deposited On the surface of a Silicon wafer, or the like. Optionally, a bulk micro-mechanical process is used to fabricate the micro-mechanical structure 302 on a common silicon wafer, SOI top layer silicon, or the like. Optionally, a surface micro-mechanical process is used to fabricate the surface micro-mechanical structure 302 on a thin film deposited on the surface of a silicon wafer or the like. Optionally, the micromechanical structure 302 is a micromechanical sensing structure, a micromechanical actuation structure, or a micromechanical control structure.

S403: a sacrificial layer 310 is fabricated on a substrate 301.

In the embodiment of the present application, the sacrificial layer 310 may have a single-layer structure or a multi-layer structure. Preferably, the sacrificial layer 310 includes a first sacrificial layer 311 and a second sacrificial layer 312. As shown in fig. 5, first sacrificial layer 311 fills micromechanical structure 302; the second sacrificial layer 312 is disposed on the surfaces of the substrate 301 and the first sacrificial layer 311, and the first sacrificial layer 311 and the second sacrificial layer 312 together constitute a double-layer sacrificial layer 310 structure. Fabricating the sacrificial layer 310 on the substrate 301 includes: the first sacrificial layer 311 is formed, and the first sacrificial layer 311 serves to protect the structure of the MEMS device from being damaged during the process and to provide a space for the MEMS device to move after the sacrificial layer 310 is released. Optionally, the method for manufacturing the first sacrificial layer 311 includes: thermal oxide silicon dioxide, LPCVD silicon dioxide, PECVD silicon dioxide, spin-on organic films, and the like. After the first sacrificial layer 311 is deposited, patterning of the first sacrificial layer 311 is achieved by using processes such as photolithography and etching. Optionally, the method for patterning the first sacrificial layer 311 includes: dry etching, wet etching, steam etching, and the like. Finally, the photoresist 309 is removed by a conventional photoresist removal process, and the first sacrificial layer 311 is completed. After the first sacrificial layer 311 is formed, a second sacrificial layer 312 is formed on the first sacrificial layer 311 and the substrate 301. The purpose of the second sacrificial layer 312 is to make the small-sized sacrificial layer 310 drill the etch hole 304 laterally to reduce the thickness of the metal layer that needs to be deposited for self-aligned formation of the nano-via 307. Optionally, the method for manufacturing the second sacrificial layer 312 includes: thermal oxide silicon dioxide, LPCVD silicon dioxide, PECVD silicon dioxide, spin-on organic films, and the like. After the second sacrificial layer 312 is deposited, the second sacrificial layer 312 is patterned by photolithography and etching. Optionally, the method for patterning the second sacrificial layer 312 includes: dry etching, wet etching, steam etching, and the like. Finally, the photoresist 309 is removed by a conventional photoresist removing process, such as a plasma photoresist removing process, thereby completing the fabrication of the second sacrificial layer 312.

In the embodiment of the present application, the material used for manufacturing the sacrificial layer 310 can be completely removed by a high-selectivity etching technique, no solid or liquid residue is left, and the degree of corrosion of the high-selectivity etching technique for removing the sacrificial layer 310 to the housing 303 and the package structure manufactured subsequently is less than one tenth of the thickness of the housing 303 before etching.

S405: a housing 303 is fabricated over the sacrificial layer 310 and the substrate 301.

In the embodiment of the present application, as shown in fig. 6, after the sacrificial layer 310 is formed, the housing 303 is formed on the sacrificial layer 310 and the substrate 301, the end portion of the housing 303 is anchored on the substrate 301, and the rest of the housing 303 is disposed on the sacrificial layer 310. The housing 303 is used to protect the micromechanical structure 302, and when the sacrificial layer 310 is released, a cavity structure is formed between the housing 303 and the substrate 301, and the micromechanical structure 302 is located in the cavity structure. The shell 303 may be deposited by LPCVD deposition, PECVD deposition, sputtering, or the like, and optionally, the deposited material includes: polysilicon, low stress silicon nitride, silicon carbide, aluminum, and the like. After the deposition of the housing 303 is completed, the patterning of the housing 303 is realized by using the processes of photolithography, corrosion and the like, and finally the photoresist 309 is removed by using the conventional photoresist removing process, so that the manufacturing of the housing 303 is completed. Optionally, depositing polysilicon by LPCVD, exposing a corrosion window of the case 303 by using photolithography, forming the case 303 by using reactive ion etching, and removing the photoresist 309 by using Piranha solution wet photoresist removal process to complete the formation of the case 303.

In some embodiments, the housing 303 may be fabricated as follows: firstly, a negative image of the shell 303 is formed by photoetching, then the metal shell 303 is sputtered, and finally the photoresist 309 and the metal on the photoresist 309 are removed by adopting a conventional photoresist removing process, so that the shell 303 is manufactured. Optionally, the metal material includes: aluminum, copper, and the like. In other embodiments, as shown in fig. 7, the housing 303 can be made by the following method: firstly, sputtering a metal seed layer 305 on a sacrificial layer 310, and optionally, the material of the metal seed layer 305 is: TiW/Au, TiW/Cu, Cr/Au, Cr/Cu, etc. Then, a negative pattern of the housing 303 is formed by photolithography, and then the metal housing 303 is manufactured by using a micro electroforming process, and optionally, the material for manufacturing the metal housing 303 includes: low stress nickel, copper, etc. The photoresist 309 is removed by a conventional photoresist removal process, and finally, the metal seed layer 305 is patterned by a corrosion process to complete the manufacture of the housing 303.

In the embodiment of the present application, the housing 303 should not be wettable with the second metal layer 308. The thickness and span of the housing 303 are designed to ensure that the housing 303 flexes downward by less than 50% of the thickness of the sacrificial layer 310 at one atmosphere of pressure. The highly selective etching technique for removing the sacrificial layer 310 should etch the housing 303 by less than one tenth of its thickness prior to etching.

S103: portions of the sacrificial layer 310 are etched to form lateral drill holes 304 between the substrate 301 and the housing 303.

In the embodiment of the present invention, after the housing 303 is manufactured, the sacrificial layer 310 between the housing 303 and the substrate 301 is etched, and the lateral etching hole 304 is formed between the housing 303 and the substrate 301 by etching in a short time. As shown in fig. 3 and 8, the lateral drilled and etched hole 304 serves to form a discontinuous interface for self-aligned fabrication of the nano-via 307, i.e., the housing 303 and the substrate 301 are discontinuous due to the presence of the lateral drilled and etched hole 304. To ensure that the nano-scale via 307 can be naturally formed in the first metal layer 306, the depth of the lateral etching hole 304 is larger than the height of the lateral etching hole 304. The height of the lateral etching hole 304 is the distance between the substrate 301 and the housing 303, and optionally, the height of the lateral etching hole 304 is 0.1 μm to 3 μm. The method for forming the lateral via 304 is essentially to release the sacrificial layer 310 for a short time by an etching process. Alternatively, the transverse etching hole 304 may be formed by wet etching, dry etching, steam etching, or the like.

In the embodiment of the present application, the depth of the lateral undercut hole 304 on the sacrificial layer 310 is slightly greater than the thickness of the sacrificial layer 310 between the housing 303 and the substrate 301, so as to ensure that the sacrificial layer 310 at the opening is completely corroded, but most of the sacrificial layer 310 should be retained, so as to provide support for the housing 303 and protect the MEMS structure, so that the entire structure can withstand the subsequent conventional cleaning process, the photolithography process, the metal layer manufacturing process, and the like. After the transverse drilled and etched hole 304 is formed, the entire structure should be able to withstand subsequent conventional cleaning processes, photolithography processes, metal layer forming processes, and the like. The method used for making the lateral drilled holes 304 should corrode the structural layer 303 of the vacuum envelope 303 and the subsequently fabricated package structure to a degree less than one tenth of its thickness before corrosion. The lateral drill hole 304 is formed by a method that does not leave solid or liquid residues that cannot be removed by cleaning and dry processes and that does not affect the structure of the integrated circuit or MEMS device.

S105: a first metal layer 306 is deposited at the lateral drilled holes 304 using an evaporation or sputtering process, the first metal layer 306 having through holes 307 of nanometer scale, the thickness of the first metal layer 306 being greater than the dimension of the lateral drilled holes 304 in the vertical direction.

In the embodiment of the present application, after the lateral etching hole 304 is fabricated, the device is cleaned by a cleaning process, so as to remove solid or liquid residues left by fabricating the lateral etching hole 304 of the sacrificial layer 310, thereby avoiding the solid or liquid residues from affecting the integrated circuit or the MEMS device structure. Optionally, the cleaning process may adopt methods such as standard cleaning of the integrated circuit RCA, cleaning with an organic solvent, rinsing with deionized water, ultrasonic cleaning, and dry plasma.

In the embodiment of the present application, after the device is cleaned, an evaporation or sputtering process is used to fabricate the first metal layer 306 on the housing 303 and the substrate 301. As shown in fig. 9, due to the existence of the lateral etching hole 304, a discontinuous interface exists between the substrate 301 and the housing 303, and when the first metal layer 306 is evaporated or sputter deposited, a through hole 307 of nanometer scale is naturally formed on the first metal layer 306 at a position corresponding to the lateral etching hole 304. The via 307 extends from the laterally drilled hole 304 up to the upper surface of the first metal layer 306, has a width equal to that of the laterally drilled hole 304 at the laterally drilled hole 304, then rapidly shrinks to several tens to one hundred nanometers, and thereafter, has almost no change in width, and remains at several tens to one hundred nanometers. Its length can be up to approximately ten microns. Since the thickness of the metal layer produced by the metal deposition process of the integrated circuit is generally less than 10 microns, the nano-scale via 307 does not disappear with the change of the metal deposition conditions. The through hole 307 is communicated with the transverse etching hole 304 to form a sacrificial layer 310 release hole, and the sacrificial layer 310 is released through the sacrificial layer 310 release hole in the subsequent sacrificial layer 310 releasing process.

As shown in fig. 9, the embodiment of the present application manufactures the first metal layer 306 by a sputtering or evaporation process, and the nano-via 307 is formed on the first metal layer 306 by self-alignment at the lateral etching hole 304. The first metal layer 306 is formed by a sputtering or evaporation process, wherein the temperature of the substrate 301 heated by the evaporation or sputtering process is lower than the temperature that the device structure can endure, and optionally, the heating temperature is lower than 400 ℃. The first metal layer 306 may be a single metal layer structure, or may be a composite structure including multiple metal layers, and contact surfaces between the multiple metal layers may be mutually wetted, or may not be wetted. Optionally, the material of the first metal layer 306 includes TiW/Cu, Ni/Au, etc. And patterning the metal layer by utilizing a photoetching and corrosion process, and finally removing the photoresist 309 to finish the manufacture of the first metal layer 306. The method of removing the photoresist 309 includes: acetone photoresist removal, organic photoresist removal liquid photoresist removal, plasma photoresist removal and the like. In some embodiments, the first metal layer 306 can also be made by: firstly, a negative pattern of the first metal layer 306 is formed by photoetching, then the first metal layer 306 is sputtered, and meanwhile, the through hole 307 of the nanoscale sacrificial layer 310 is formed in a self-alignment manner, and optionally, the material of the first metal layer 306 comprises TiW/Cu, Ni/Au and the like. Finally, the photoresist 309 and the metal on the photoresist 309 are removed by a conventional photoresist removing process, and the first metal layer 306 is completed.

In the embodiment of the present invention, in order to form the nano-via 307 in a self-aligned manner while depositing the first metal layer 306, a sputtering or evaporation process is required for deposition. The melting point of the first metal layer 306 is higher than that of the second metal layer 308 to be manufactured subsequently, and optionally, the melting point of the first metal layer 306 is higher than 600 ℃. The first metal layer 306 may be a single metal layer, such as titanium, tungsten, copper, gold, nickel, chromium, etc. A complex metal layer, such as TiW/Cu, Ni/Au, etc., may also be used, where the bottom metal layer is made of TiW, Ni, etc. to adhere to the housing 303, and the surface metal layer is made of Cu, Au, etc. to provide a wetting layer with the second metal layer 308.

S107: a second metal layer 308 is deposited on the first metal layer 306, the second metal layer 308 having a melting point lower than the melting point of the first metal layer 306.

In the embodiment of the present application, as shown in fig. 10, after the first metal layer 306 is manufactured, a second metal layer 308 is deposited at the through hole 307 as a sealing metal, and the second metal layer 308 is wet with the upper surface of the first metal layer 306. As shown in fig. 10, one end of the second metal layer 308 is close to the via 307, and the distance between the lower surface of the second metal layer 308 and the via 307 is determined by the photolithography process, and can be generally designed to be the minimum photolithography line width. There are several ways to form the second metal layer 308, as shown in fig. 11, by forming the second metal layer 308 by first sputtering or evaporating the metal over a large area, optionally,the material of the second metal layer 308 includes Sn, In, Sn₂Sb₂S₅And the like. And then, patterning the second metal layer 308 by utilizing a photoetching and corrosion process, finally removing the photoresist 309, and completing the manufacture of the second metal layer 308, wherein the manufactured second metal layer 308 cannot completely block the nano-scale through hole 307. In some embodiments, the second metal layer 308 can also be made by: first, a negative pattern of the second metal layer 308 is formed by photolithography, and then the second metal layer 308 is sputtered or evaporated, and optionally, the material of the second metal layer 308 includes Sn, In, and Sn₂Sb₂S₅And the like. Finally, the photoresist 309 and the metal on the photoresist 309 are removed by a conventional photoresist removing process, so as to complete the fabrication of the second metal layer 308. In other embodiments, the second metal layer 308 can be further formed by: as shown in fig. 12, first, a first metal layer 306 having a continuous surface is sputtered or evaporated in a large area while a first metal layer 306 is fabricated, and a nano-scale metal via 307 is formed in a self-aligned manner; then, a negative pattern of the second metal layer 308 is formed by photolithography, and the photoresist 309 should completely cover the through hole 307 with a nanometer scale so as to prevent the through hole 307 from being sealed by a subsequent electroplating process; next, a second metal layer 308 is electroplated, and optionally, the material of the electroplated second metal layer 308 includes Sn, Sn-Ag-Cu alloy, and the like. And then removing the photoresist 309 by using a conventional photoresist removing process to complete the manufacture of the second metal layer 308. As shown in fig. 13, after the second metal layer 308 is formed, patterning of the first metal layer 306 is performed by using a photolithography or etching process, the photoresist 309 should completely cover the through hole 307, so as to ensure that the through hole 307 with a nanoscale size is not etched away, and patterning of the first metal layer 306 is to ensure that the melted second metal layer 308 only spreads and flows in a designated area around the through hole 307. Finally, the photoresist 309 is removed by a conventional photoresist removal process, and the patterning of the first metal layer 306 is completed. Optionally, the method for removing the photoresist 309 includes: acetone photoresist removal, organic photoresist removal liquid photoresist removal, plasma photoresist removal and the like.

In the embodiment of the present application, the melting point of the second metal layer 308 is lower than that of the first metal layer 306, and the melting point of the second metal layer 308 is lower than that of all materials in the previous process and higher than the temperature of the subsequent packaging process, and optionally, the melting point of the second metal layer 308 ranges from 150 ℃ to 400 ℃. The second metal layer 308 and the upper surface of the first metal layer 306 can be mutually wetted, but the material of the second metal layer 308 is not wetted with the shell 303. The thickness consumed by the molten second metal layer 308 to react with the first metal layer 306 is less than 70% of the thickness of the first metal layer 306. When the packaging structure is packaged, the second metal layer 308 is heated in vacuum, so that the second metal layer 308 is heated and melted to form molten metal liquid, and as the second metal layer 308 is infiltrated into the surface of the first metal layer 306, the molten metal liquid spreads on the surface of the first metal layer 306 under the action of surface tension to automatically seal the nano through hole 307 based on the principle of minimum surface energy, thereby realizing the wafer-level film vacuum packaging. Since the characteristic dimension of the opening on the surface of the through hole 307 is in the nanometer level, based on the principle of lowest energy, the surface of the melted second metal layer 308 tends to shrink, i.e. tends to receive the minimum surface force, and tends to form the minimum surface, therefore, in order to realize sealing, the thickness H of the spread second metal layer 308 needs to satisfy:

where H is the thickness of the second metal layer 308; a is the characteristic dimension of the opening of the through hole 307 on the upper surface of the first metal layer 306, and a is the diameter of the circle when the opening of the through hole 307 on the upper surface of the first metal layer 306 is approximately circular; when the via hole 307 is opened on the upper surface of the first metal layer 306 in an approximately rectangular shape, a is the length of the short side of the rectangular shape; when the opening of the through hole 307 on the upper surface of the first metal layer 306 is approximately elliptical, a is the length of the minor axis of the ellipse; θ is the contact angle of the molten metal on the first metal layer 306.

Because the characteristic dimension of the surface opening of the through hole 307 formed in the first metal layer 306 in a self-aligned manner is in a nanometer scale, only a very thin second metal layer 308 is needed in the subsequent fusion sealing process to realize sealing. When the size of the through hole 307 is as small as tens to one hundred nanometers, the thickness of the spread second metal layer 308 only needs to be more than tens of nanometers to seal the through hole 307, and optionally, the thickness of the second metal layer 308 is less than 10 μm. Since the second metal layer 308 will alloy with the first metal layer 306 during the spreading process in the molten state, the thin second metal layer 308 means that only the thin first metal layer 306 is needed to ensure that the alloying process does not completely consume the first metal layer 306, thereby ensuring the reliability of the process.

S109: and releasing the sacrificial layer 310 through the sacrificial layer 310 release hole to obtain the device to be packaged.

In the embodiment of the present application, as shown in fig. 14, after the second metal layer 308 is manufactured, the sacrificial layer 310 is released through the sacrificial layer 310 release hole. The release of the sacrificial layer 310 adopts SiO₂And (after metal) wet etching process, wherein the etching solution reacts with the sacrificial layer 310 through the nano through hole 307 to release the sacrificial layer 310. In some embodiments, rich O may also be employed₂The release of the sacrificial layer 310, O, is realized by the plasma etching technique₂The plasma reacts with the sacrificial layer 310 structure through the nano-via 307, completing the release of the sacrificial layer 310. Fig. 14 is a schematic structural diagram of a device to be packaged, and as shown in fig. 14, after the sacrificial layer 310 is released, a cavity structure is formed between the housing 303 and the micromechanical structure 302, and the micromechanical structure 302 is located in the cavity structure after the sacrificial layer 310 is released.

In the embodiment of the present application, when the sacrificial layer 310 is completely removed, the sacrificial layer 310 releasing process should corrode the housing 303, the first metal layer 306, and the second metal layer 308 by less than one tenth of the thickness before corrosion. In addition, the sacrificial layer 310 release process should be able to completely remove the sacrificial layer 310 material without leaving solid or liquid residues that cannot be removed by dry processes and without affecting the integrated circuit or MEMS device structure. Alternatively, the sacrificial layer 310 may be removed by wet etching, dry etching, steam etching, or the like.

S111: and heating the device to be packaged at a temperature between the melting point of the second metal layer 308 and the melting point of the first metal layer 306, so that the second metal layer 308 is melted and spread, and the release hole of the sacrificial layer 310 is sealed.

In the embodiment of the application, as shown in fig. 15, after the sacrificial layer 310 is removed, the second metal layer 308 is heated to melt the second metal layer 308, and due to the wetting of the second metal layer 308 and the surface of the first metal layer 306, the molten metal of the molten second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension thereof, so as to seal the nano through hole 307, thereby sealing the release hole of the sacrificial layer 310 and completing the packaging. The heating process may be performed in a vacuum environment or a non-vacuum environment, and may be selected according to the type and operation requirements of the micro-mechanical structure 302. The second metal layer 308 of the embodiment of the present application is melted and reflowed in a vacuum environment, and the heating temperature in the whole process should be higher than the melting point of the second metal layer 308 and lower than the safe temperature that the integrated circuit and the MEMS device can endure.

The embodiment of the application also discloses a packaging device which is prepared by adopting the packaging method.

The vacuum packaging method is compatible with a thin film process and a surface micro-mechanical technology. Since the feature size of the surface opening of the via 307 formed by the self-aligned first metal layer 306 is in the nanometer level, only a thin second metal layer 308 is needed in the subsequent fusion sealing process to realize sealing. Since the second metal layer 308 will alloy with the first metal layer 306 during the melting and spreading process, the thin second metal layer 308 means that only the thin first metal layer 306 is needed to ensure that the alloying process will not completely consume the first metal layer 306, thereby ensuring the reliability of the process. The conventional surface micro-mechanical process is a thin film process, and the technology of forming the nano through hole 307 by self-alignment enables the patent to be compatible with the thin film process and the surface micro-mechanical technology.

The vacuum packaging method is compatible with a metal wiring process. The common processes of integrated circuits such as LPCVD, metal deposition, electroplating and the like and micro-electro-mechanical systems are adopted, the second metal layer 308 with the melting point lower than the temperature endurable by the MEMS device is adopted as sealing metal, the vacuum packaging is realized by spreading and flowing the molten second metal layer 308 under the action of surface tension, and the process is compatible with a metal film process. Thus, Complementary Metal Oxide Semiconductor (CMOS) Metal wiring and other Metal structures may be completed before the first Metal layer 306 is fabricated. The vacuum sealing process that melt seals from making the first metal layer 306 to the second metal layer 308 is a Post-CMOS process.

The vacuum packaging method described in the embodiments of the present application is compatible with conventional low temperature getter processes. The melting temperature of the second metal layer 308 is close to the activation temperature of the low-temperature getter, and almost no gas is emitted in the process, so that the low-temperature getter can be used for absorbing and removing residual gas.

Based on the above alternative embodiments, four alternative embodiments are described below.

Example 1:

in this embodiment, the sacrificial layer 310 is made of thermal SiO oxide₂The shell 303 is made of LPCVD polysilicon, the transverse drilling and etching hole 304 of the sacrificial layer 310 is made of SiO2 (before metal) wet etching process, the first metal layer 306 is made of metal sputtering TiWu/Cu and is self-aligned to form a nano through hole 307, and the second metal layer 308 is made of electroplating lead-free tin. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 16, micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Manufacturing a double-layer sacrificial layer 310 structure: as shown in FIG. 16, the double-layer sacrificial layer 310 structure adopts thermal SiO oxide₂The preparation comprises first using thermal oxidation SiO₂Fabricating the first sacrificial layer 311 by photolithography and SiO process₂The patterning of the first sacrificial layer 311 is realized by a (pre-metal) wet etching process, and the photoresist 309 is removed by a plasma photoresist removal process, so that the first sacrificial layer 311 is manufactured. Then thermal oxidation of SiO is used₂And manufacturing the second sacrificial layer 312, patterning the second sacrificial layer 312 by using photolithography and dry etching processes, and finally removing the photoresist 309 by using a plasma photoresist removing process to complete the manufacturing of the second sacrificial layer 312. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a shell 303: as shown in fig. 16, the housing 303 is first formed by depositing polysilicon by LPCVD, then exposing the etching window of the housing 303 by photolithography, then forming the housing 303 by reactive ion etching, and finally removing the photoresist 309 by Piranha solution wet photoresist removal process to complete the formation of the housing 303.

Manufacturing a transverse etching hole 304: as shown in FIG. 16, the lateral drill hole 304 is made of SiO₂The wet etching process (before metal) is used for manufacturing, wherein the transverse underetching depth of the sacrificial layer 310 is slightly larger than the depth of the sacrificial layer 310 at the opening through short-time etching, so that the sacrificial layer 310 at the opening is completely etched and most of the sacrificial layer 310 is remained, the support is provided for the structural layer and the MEMS structure is protected, and the whole structure can withstand the subsequent conventional cleaning process, the photoetching process, the metal layer manufacturing process and the like.

Cleaning: the cleaning process uses deionized water to wash and remove solid or liquid residues left after the transverse drilling and etching holes 304 of the sacrificial layer 310 are manufactured, so that the influence of the solid or liquid residues on the integrated circuit or the MEMS device structure is avoided.

Depositing a first metal layer 306: as shown in fig. 17 and 18, a first metal layer 306 is formed by first sputtering TiWu/Cu with a continuous surface in a large area and forming a nano-via 307 by self-alignment, and the first metal layer 306 covers the housing 303 and the substrate 301.

Manufacturing a second metal layer 308 for sealing: as shown in fig. 19 and 20, the second metal layer 308 uses the first metal layer 306 deposited in large area in the above steps as a seed layer, and its material is TiWu/Cu; and then photoetching to form a negative pattern of the second metal layer 308, electroplating lead-free tin by adopting an electroplating process, wherein the photoresist 309 is required to completely cover the nano through hole 307 in the step to avoid the closing of the nano through hole 307 caused by the electroplating process, and finally removing the photoresist 309 by adopting an acetone photoresist removing process to prepare the second metal layer 308.

Patterning the first metal layer 306: in this embodiment, the second metal layer 308 is formed by an electroplating process, and the first metal layer 306 is used as a seed layer, so that the first metal layer 306 is continuous. If the first metal layer 306 and the second metal layer 308 are mutually wetted, if the first metal layer 306 is not patterned, the second metal layer 308 will flow freely on the surface of the first metal layer 306 after being melted, and therefore the first metal layer 306 needs to be patterned, so that the second metal layer 308 can only spread in a limited area to seal the nano-via 307. As shown in fig. 21, the patterning of the first metal layer 306 is performed by first etching the first metal layer 306 by photolithography or plasma, in which step the photoresist 309 needs to completely cover the nano-via 307 to avoid removing the nano-via 307 by the plasma etching process, and finally removing the photoresist 309 by the acetone photoresist removing process to complete the patterning of the first metal layer 306. As shown in fig. 22 and 23, a certain distance is formed between the second metal layer 308 and the via hole 307 by photolithography.

The sacrificial layer 310 releases: as shown in fig. 24, the sacrificial layer 310 is released by using a SiO2 (post-metal) wet etching process, and the etching solution reacts with the double-layer sacrificial layer 310 structure through the nano-via 307, so as to release the sacrificial layer 310.

And (3) melting and reflowing the sealed second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 25 and 26, the melting conditions of the seal second metal layer 308 are: (1) a vacuum environment; (2) the temperature is higher than 235 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension thereof, and automatically seals the nano-via 307.

Example 2:

in this embodiment, the sacrificial layer 310 is made of LPCVD silicon dioxide, the housing 303 is made of micro-electroformed low-stress Ni, and the transverse etching holes 304 on the sacrificial layer 310 are made of SiO₂And (after metal) wet etching, wherein the first metal layer 306 is made of metal evaporated Ni/Au, nano through holes 307 are formed in a self-alignment manner, and the second metal layer 308 is made of metal sputtered Sn. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 27, micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Manufacturing a double-layer sacrificial layer 310 structure: as shown in FIG. 27, the dual-layer sacrificial layer 310 is made of LPCVD silicon dioxide by first using LPCVD SiO₂Fabricating the first sacrificial layer 311 by photolithography/SiO₂The patterning of the first sacrificial layer 311 is realized by a (pre-metal) wet etching process, and the photoresist 309 is removed by a plasma photoresist removal process, so that the first sacrificial layer 311 is manufactured. Then LPCVD SiO is adopted₂Fabricating a second sacrificial layer 312 using lightAnd patterning the second sacrificial layer 312 by an etching/dry etching process, and finally removing the photoresist 309 by a plasma photoresist removing process to complete the manufacture of the second sacrificial layer 312. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a shell 303: as shown in fig. 27, the housing 303 is manufactured by firstly sputtering a metal seed layer 305, then forming a negative pattern of the housing 303 by photolithography, then manufacturing the metal housing 303 by using a micro-electroforming low-stress nickel process, and finally removing the photoresist 309 by using an acetone photoresist removal technique. The surface of the nickel is easy to form a dense oxide film in the humid air, and the oxide film is not wet with the second metal layer 308 of the subsequent seal.

Making the lateral etching hole 304 of the sacrificial layer 310: as shown in FIG. 27, the lateral etching hole 304 on the sacrificial layer 310 is made of SiO₂And (after metal) wet etching process.

Manufacturing a first metal layer 306: as shown in fig. 28, the first metal layer 306 is first formed with a negative pattern of the first metal layer 306 by photolithography, then the first metal layer 306 is deposited by metal evaporation Ni/Au process, and self-aligned to form the nano-via 307, and finally the metal layers on the

photoresist

309 and 309 are removed by acetone stripping process to complete the fabrication of the first metal layer 306. As shown in fig. 29 and 30, a through hole 307 of a nanometer scale is naturally formed on the first metal layer 306.

Manufacturing a second metal layer 308 for sealing: as shown in fig. 31 and 32, the second metal layer 308 is first formed with a negative pattern of the second metal layer 308 by using a photolithography technique, then the second metal layer 308 is deposited by using metal sputtering Sn, and finally the photoresist 309 and the metal layer on the photoresist 309 are removed by using an acetone photoresist removal process, thereby completing the fabrication of the second metal layer 308.

The sacrificial layer 310 releases: as shown in FIG. 33, the release of the sacrificial layer 310 is made of SiO₂(Metal rear)And in the wet etching process, the etching solution reacts with the double-layer sacrificial layer 310 structure through the nano through hole 307, so that the sacrificial layer 310 is released.

And (3) melting and reflowing the sealed second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 34 and 35, the melting conditions of the seal second metal layer 308 are: (1) a vacuum environment; (2) the temperature is higher than 235 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension thereof, and the nano-via 307 is automatically sealed.

Example 3:

in this embodiment, the sacrificial layer 310 is made of PECVD silicon dioxide, the housing 303 is made of PECVD polysilicon, the lateral etching hole 304 of the sacrificial layer 310 is made of SiO2 (before metal) wet etching process, the first metal layer 306 is made of metal sputtering Ni/Au and is self-aligned to form the nano-via 307, and the second metal layer 308 is made of metal sputtering In. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 36, micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Manufacturing a double-layer sacrificial layer 310 structure: as shown in FIG. 36, the double-layer sacrificial layer 310 is made of PECVD silicon dioxide, and is first made of PECVD SiO₂Manufacturing the first sacrificial layer 311, patterning the first sacrificial layer 311 by using a photoetching/SiO 2 (before metal) wet etching process, and finally removing the photoresist 309 by using a plasma photoresist removing process to complete the manufacturing of the first sacrificial layer 311. Then adopting PECVD SiO₂And manufacturing a second sacrificial layer 312, then realizing the patterning of the second sacrificial layer 312 by using a photoetching/dry etching process, and finally removing the photoresist 309 by using a plasma photoresist removing process to finish the manufacturing of the second sacrificial layer 312. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a shell 303: as shown in fig. 36, the housing 303 is first formed by depositing polysilicon using PECVD, and then patterning the housing 303 using photolithography/reactive ion etching; finally, the photoresist 309 is removed by an acetone photoresist removal process, and the manufacture of the shell 303 is completed.

Making the lateral etching hole 304 of the sacrificial layer 310: as shown in fig. 36, the lateral drill hole 304 is formed using a SiO2 (pre-metal) wet etch process.

Manufacturing a first metal layer 306: as shown in fig. 37 and 38, the first metal layer 306 is formed by first sputtering Ni/Au and self-aligning to form a nano-via 307; then, exposing the corrosion window of the first metal layer 306 by using a photoetching technology, wherein the photoresist 309 needs to completely cover the nano through hole 307 so as to prevent the nano through hole 307 from being removed by a plasma etching process; finally, the Ni/Au at the etching window is removed by using a plasma etching technology, and the photoresist 309 is removed by using an acetone photoresist removal technology, so that the first metal layer 306 is manufactured.

Manufacturing a second metal layer 308 for sealing: as shown In fig. 39 and 40, the second metal layer 308 is formed by first sputtering In and forming a nano-via 307 by self-alignment; then, exposing the corrosion window of the second metal layer 308 by using a photolithography technique, wherein the nano through hole 307 needs to be completely covered by the photoresist 309 so as to prevent the nano through hole 307 from being removed by a plasma etching process; finally, the In at the etching window is removed by using a plasma etching technology, and the photoresist 309 is removed by using an acetone photoresist removal technology, thereby completing the manufacture of the second metal layer 308.

The sacrificial layer 310 releases: as shown in FIG. 41, the release of the sacrificial layer 310 is made of SiO₂And (after metal) wet etching process, wherein the etching solution reacts with the sacrificial layer 310 through the nano through hole 307, so that the release of the double-layer sacrificial layer 310 is realized.

And (3) melting and reflowing the sealed second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 42 and 43, the melting conditions of the seal second metal layer 308 are: (1) a vacuum environment; (2) the temperature is higher than 157 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension thereof, and the nano-via 307 is automatically sealed.

Example 4:

in this embodiment, the sacrificial layer 310 is a polyimidede PI2610, getter layer 320 is made of sputtered Ti, housing 303 is made of LPCVD silicon nitride, and sacrificial layer 310 is drilled with O in transverse direction to form hole 304₂The first metal layer 306 is made of metal evaporation Ni/Au and is self-aligned to form a nano through hole 307, and the second metal layer 308 is made of sputtered Sn. The method comprises the following specific steps:

manufacturing a micro-mechanical structure 302: as shown in fig. 44, micromechanical structure 302 is fabricated using conventional bulk micromachining processes.

Manufacturing a double-layer sacrificial layer 310 structure: as shown in fig. 44, the double-layer sacrificial layer 310 is made of polyimidePI2610, and is spin-coated with polyimidePI PI2610, and is baked twice to remove part of the solvent, so that the solution is more stable, and the baking conditions are baking at 90 ℃ for 3 minutes and 180 ℃ for 90 seconds; then placing the mixture into a nitrogen environment at 400 ℃ for curing; then depositing a SiC layer as a hard mask for etching the sacrificial layer 310; and then, etching the SiC layer and the polyimide PI2610 layer by utilizing a photoetching technology and an Alcatel GIR300 fluorine etching machine, wherein the etching of the SiC layer adopts CF4, SF6 and O₂The mixed gas of (1), polyimide PI2610 adopts O₂Etching the plasma; then removing the photoresist 309 with acetone; and removing the residual SiC layer by using an Alcatel GIR300 fluorine etching machine to finish the manufacture of the first sacrificial layer 311. Finally, a second sacrificial layer 312 is formed, and the method for forming the second sacrificial layer 312 is the same as that for forming the first sacrificial layer 311. The first sacrificial layer 311 and the second sacrificial layer 312 together form a dual-layer sacrificial layer 310 structure.

Manufacturing a getter layer 320: as shown in fig. 44, the getter layer 320 is formed by first sputtering Ti and then exposing the etching window of the getter layer 320 by using a photolithography technique; finally, Ti at the etching window is removed by using a plasma etching technology, and the photoresist 309 is removed by using an acetone photoresist removal technology, so that the getter layer 320 is manufactured.

Manufacturing a shell 303: as shown in fig. 44, the housing 303 is first formed by depositing low-stress silicon nitride by a PECVD process, then exposing the etching window of the housing 303 by a photolithography technique, forming the housing 303 by a reactive ion etching technique, and finally removing the photoresist 309 by an acetone photoresist removal process.

Making the lateral etching hole 304 of the sacrificial layer 310: as shown in FIG. 45, the lateral etching hole 304 of the sacrificial layer 310 is O₂The plasma etching technology is used for manufacturing, wherein the transverse underetching depth of the sacrificial layer 310 is slightly larger than the depth of the sacrificial layer 310 at the opening through short-time etching, so that the sacrificial layer 310 at the opening is completely corroded and most of the sacrificial layer 310 is remained, a support is provided for a structural layer and an MEMS structure is protected, and the whole structure can withstand the subsequent conventional cleaning process, the photoetching process, the metal layer manufacturing process and the like.

Manufacturing a first metal layer 306: as shown in fig. 46 and 47, the first metal layer 306 first uses metal to evaporate Ni/Au and forms the through hole 307 of the nano-scale metal sacrificial layer 310 in self-alignment; then, exposing the corrosion window of the first metal layer 306 by using a photoetching technology, wherein the photoresist 309 needs to completely cover the nano through hole 307 so as to prevent the nano through hole 307 from being removed by a plasma etching process; finally, the Ni/Au at the etching window is removed by adopting a plasma etching technology, and the photoresist 309 is removed by adopting an acetone photoresist removing technology, so that the first metal layer 306 is manufactured.

Manufacturing a second metal layer 308 for sealing: as shown in fig. 48 and 49, the second metal layer 308 is formed by first forming a negative pattern of the second metal layer 308 by photolithography, then forming the second metal layer 308 by a sputtering Sn process, and finally removing the photoresist 309 and the metal layer on the photoresist 309 by an acetone photoresist removal process, thereby completing the formation of the second metal layer 308.

The sacrificial layer 310 releases: as shown in FIG. 50, the release of the sacrificial layer 310 is O-rich₂Technical realization of plasma etching, O₂The plasma reacts with the double-layer sacrificial layer 310 structure through the nano-via 307, completing the release of the sacrificial layer 310.

And (3) melting and reflowing the sealed second metal layer 308 under vacuum to realize vacuum packaging: as shown in fig. 51 and 52, the melting conditions of the seal second metal layer 308 are: (1) a vacuum environment; (2) the temperature is higher than 235 ℃. The melted second metal layer 308 spreads and flows on the surface of the first metal layer 306 under the action of the surface tension thereof, and the nano-via 307 is automatically sealed.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A wafer level film encapsulation method is characterized by comprising the following steps:

obtaining a chip wafer, wherein the chip wafer comprises a substrate (301), a sacrificial layer (310) and a shell (303), a micromechanical structure (302) is arranged on the substrate (301), and the sacrificial layer (310) is arranged between the micromechanical structure (302) and the shell (303);

etching a portion of the sacrificial layer (310) to form a lateral drill hole (304) between the substrate (301) and the housing (303);

depositing a first metal layer (306) at the transverse drilled and etched hole (304) by adopting an evaporation or sputtering process, wherein the first metal layer (306) is provided with a through hole (307) with a nanometer scale, the through hole (307) is communicated with the transverse drilled and etched hole (304) to form a sacrificial layer (310) release hole, and the thickness of the first metal layer (306) is larger than the size of the transverse drilled and etched hole (304) in the vertical direction;

depositing a second metal layer (308) on the first metal layer (306), the second metal layer (308) having a melting point lower than the melting point of the first metal layer (306);

releasing the sacrificial layer (310) through the sacrificial layer (310) release hole to obtain a device to be packaged;

heating the device to be packaged at a temperature between the melting point of the second metal layer (308) and the melting point of the first metal layer (306) so that the second metal layer (308) is melted and spread, thereby sealing the sacrificial layer (310) release holes.

2. The packaging method according to claim 1, wherein the size of the lateral etching hole (304) in the horizontal direction is larger than the size of the lateral etching hole (304) in the vertical direction.

3. The encapsulation method according to claim 2, wherein the lateral drill hole (304) has a dimension in a vertical direction of 0.1 μm to 3 μm.

4. The packaging method according to claim 1, wherein the depositing a first metal layer (306) at the lateral drill hole (304) using an evaporation or sputtering process comprises:

heating the substrate (301) at a temperature below 400 ℃.

5. The encapsulation method according to claim 4, wherein the melting point of the first metal layer (306) is higher than 600 ℃ and the melting point of the second metal layer (308) ranges from 150 ℃ to 400 ℃.

6. The method of claim 1, wherein the surfaces of the second metal layer (308) opposite the first metal layer (306) are wetted with each other.

7. The encapsulation method according to claim 6, wherein the thickness of the second metal layer (308) satisfies the following relationship:

wherein H is the thickness of the second metal layer (308);

a is the characteristic dimension of the opening of the through hole (307) on the upper surface of the first metal layer (306);

θ is a contact angle of the molten metal liquid on the first metal layer (306).

8. The encapsulation method according to claim 7, characterized in that the thickness of the second metal layer (308) is less than 10 μm.

9. The packaging method according to claim 1, wherein the heating the device to be packaged comprises:

and heating the device to be packaged in a vacuum environment.

10. A packaged device, characterized in that it is prepared by the packaging method according to any one of claims 1 to 9.